Spelling: Fix the a spelling error by changing mmaped to mmapped.
There may not be a formally correct spelling for the past tense of mmap, but mmapped is the spelling Google doesn't try to autocorrect. This makes sense because it mirrors the past tense of map->mapped and not the past tense of cape->caped. --HG-- rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh
This commit is contained in:
parent
e8b982e247
commit
579c5f0b65
13 changed files with 29 additions and 29 deletions
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@ -50,7 +50,7 @@ isa_switch_hdrs = Split('''
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kernel_stats.hh
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kernel_stats.hh
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locked_mem.hh
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locked_mem.hh
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microcode_rom.hh
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microcode_rom.hh
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mmaped_ipr.hh
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mmapped_ipr.hh
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mt.hh
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mt.hh
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process.hh
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process.hh
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predecoder.hh
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predecoder.hh
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@ -28,8 +28,8 @@
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* Authors: Ali Saidi
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* Authors: Ali Saidi
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*/
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*/
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#ifndef __ARCH_ALPHA_MMAPED_IPR_HH__
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#ifndef __ARCH_ALPHA_MMAPPED_IPR_HH__
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#define __ARCH_ALPHA_MMAPED_IPR_HH__
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#define __ARCH_ALPHA_MMAPPED_IPR_HH__
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/**
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/**
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* @file
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* @file
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@ -60,4 +60,4 @@ handleIprWrite(ThreadContext *xc, Packet *pkt)
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} // namespace AlphaISA
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} // namespace AlphaISA
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#endif // __ARCH_ALPHA_MMAPED_IPR_HH__
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#endif // __ARCH_ALPHA_MMAPPED_IPR_HH__
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@ -30,8 +30,8 @@
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* Stephen Hines
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* Stephen Hines
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*/
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*/
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#ifndef __ARCH_ARM_MMAPED_IPR_HH__
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#ifndef __ARCH_ARM_MMAPPED_IPR_HH__
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#define __ARCH_ARM_MMAPED_IPR_HH__
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#define __ARCH_ARM_MMAPPED_IPR_HH__
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/**
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/**
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* @file
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* @file
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@ -28,8 +28,8 @@
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* Authors: Ali Saidi
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* Authors: Ali Saidi
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*/
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*/
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#ifndef __ARCH_MIPS_MMAPED_IPR_HH__
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#ifndef __ARCH_MIPS_MMAPPED_IPR_HH__
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#define __ARCH_MIPS_MMAPED_IPR_HH__
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#define __ARCH_MIPS_MMAPPED_IPR_HH__
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/**
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/**
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* @file
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* @file
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@ -32,8 +32,8 @@
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* Timothy M. Jones
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* Timothy M. Jones
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*/
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*/
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#ifndef __ARCH_POWER_MMAPED_IPR_HH__
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#ifndef __ARCH_POWER_MMAPPED_IPR_HH__
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#define __ARCH_POWER_MMAPED_IPR_HH__
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#define __ARCH_POWER_MMAPPED_IPR_HH__
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/**
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/**
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* @file
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* @file
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@ -63,4 +63,4 @@ handleIprWrite(ThreadContext *xc, Packet *pkt)
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} // namespace PowerISA
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} // namespace PowerISA
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#endif // __ARCH_POWER_MMAPED_IPR_HH__
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#endif // __ARCH_POWER_MMAPPED_IPR_HH__
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@ -28,8 +28,8 @@
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* Authors: Ali Saidi
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* Authors: Ali Saidi
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*/
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*/
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#ifndef __ARCH_SPARC_MMAPED_IPR_HH__
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#ifndef __ARCH_SPARC_MMAPPED_IPR_HH__
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#define __ARCH_SPARC_MMAPED_IPR_HH__
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#define __ARCH_SPARC_MMAPPED_IPR_HH__
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/**
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/**
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* @file
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* @file
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@ -816,7 +816,7 @@ handleSparcErrorRegAccess:
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regAccessOk:
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regAccessOk:
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handleMmuRegAccess:
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handleMmuRegAccess:
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DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
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DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
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req->setFlags(Request::MMAPED_IPR);
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req->setFlags(Request::MMAPPED_IPR);
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req->setPaddr(req->getVaddr());
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req->setPaddr(req->getVaddr());
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return NoFault;
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return NoFault;
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};
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};
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@ -37,8 +37,8 @@
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* Authors: Gabe Black
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* Authors: Gabe Black
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*/
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*/
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#ifndef __ARCH_X86_MMAPEDIPR_HH__
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#ifndef __ARCH_X86_MMAPPEDIPR_HH__
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#define __ARCH_X86_MMAPEDIPR_HH__
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#define __ARCH_X86_MMAPPEDIPR_HH__
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/**
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/**
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* @file
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* @file
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@ -89,4 +89,4 @@ namespace X86ISA
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}
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}
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};
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};
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#endif // __ARCH_X86_MMAPEDIPR_HH__
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#endif // __ARCH_X86_MMAPPEDIPR_HH__
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@ -179,7 +179,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc)
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panic("CPUID memory space not yet implemented!\n");
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panic("CPUID memory space not yet implemented!\n");
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} else if (prefix == IntAddrPrefixMSR) {
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} else if (prefix == IntAddrPrefixMSR) {
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vaddr = vaddr >> 3;
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vaddr = vaddr >> 3;
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req->setFlags(Request::MMAPED_IPR);
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req->setFlags(Request::MMAPPED_IPR);
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Addr regNum = 0;
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Addr regNum = 0;
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switch (vaddr & ~IntAddrPrefixMask) {
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switch (vaddr & ~IntAddrPrefixMask) {
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case 0x10:
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case 0x10:
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@ -508,7 +508,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc)
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// space.
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// space.
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assert(!(IOPort & ~0xFFFF));
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assert(!(IOPort & ~0xFFFF));
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if (IOPort == 0xCF8 && req->getSize() == 4) {
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if (IOPort == 0xCF8 && req->getSize() == 4) {
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req->setFlags(Request::MMAPED_IPR);
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req->setFlags(Request::MMAPPED_IPR);
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req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
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req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
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} else if ((IOPort & ~mask(2)) == 0xCFC) {
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} else if ((IOPort & ~mask(2)) == 0xCFC) {
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req->setFlags(Request::UNCACHEABLE);
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req->setFlags(Request::UNCACHEABLE);
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@ -29,7 +29,7 @@
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*/
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*/
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#include "arch/locked_mem.hh"
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#include "arch/locked_mem.hh"
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#include "arch/mmaped_ipr.hh"
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#include "arch/mmapped_ipr.hh"
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#include "arch/utility.hh"
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#include "arch/utility.hh"
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#include "base/bigint.hh"
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#include "base/bigint.hh"
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#include "config/the_isa.hh"
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#include "config/the_isa.hh"
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@ -334,7 +334,7 @@ AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
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Packet::Broadcast);
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Packet::Broadcast);
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pkt.dataStatic(data);
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pkt.dataStatic(data);
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if (req->isMmapedIpr())
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if (req->isMmappedIpr())
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dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
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dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
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else {
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else {
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if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
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if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
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@ -501,7 +501,7 @@ AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
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Packet pkt = Packet(req, cmd, Packet::Broadcast);
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Packet pkt = Packet(req, cmd, Packet::Broadcast);
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pkt.dataStatic(data);
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pkt.dataStatic(data);
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if (req->isMmapedIpr()) {
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if (req->isMmappedIpr()) {
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dcache_latency +=
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dcache_latency +=
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TheISA::handleIprWrite(thread->getTC(), &pkt);
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TheISA::handleIprWrite(thread->getTC(), &pkt);
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} else {
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} else {
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@ -41,7 +41,7 @@
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*/
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*/
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#include "arch/locked_mem.hh"
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#include "arch/locked_mem.hh"
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#include "arch/mmaped_ipr.hh"
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#include "arch/mmapped_ipr.hh"
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#include "arch/utility.hh"
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#include "arch/utility.hh"
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#include "base/bigint.hh"
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#include "base/bigint.hh"
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#include "config/the_isa.hh"
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#include "config/the_isa.hh"
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@ -264,7 +264,7 @@ bool
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TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
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TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
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{
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{
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RequestPtr req = pkt->req;
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RequestPtr req = pkt->req;
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if (req->isMmapedIpr()) {
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if (req->isMmappedIpr()) {
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Tick delay;
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Tick delay;
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delay = TheISA::handleIprRead(thread->getTC(), pkt);
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delay = TheISA::handleIprRead(thread->getTC(), pkt);
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new IprEvent(pkt, this, nextCycle(curTick() + delay));
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new IprEvent(pkt, this, nextCycle(curTick() + delay));
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@ -401,7 +401,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
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{
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{
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pkt1 = pkt2 = NULL;
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pkt1 = pkt2 = NULL;
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assert(!req1->isMmapedIpr() && !req2->isMmapedIpr());
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assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
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if (req->getFlags().isSet(Request::NO_ACCESS)) {
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if (req->getFlags().isSet(Request::NO_ACCESS)) {
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buildPacket(pkt1, req, read);
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buildPacket(pkt1, req, read);
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TimingSimpleCPU::handleWritePacket()
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TimingSimpleCPU::handleWritePacket()
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{
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{
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RequestPtr req = dcache_pkt->req;
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RequestPtr req = dcache_pkt->req;
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if (req->isMmapedIpr()) {
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if (req->isMmappedIpr()) {
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Tick delay;
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Tick delay;
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delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
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delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
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new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
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new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
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fatal("Insufficient memory to allocate compression state for %s\n",
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fatal("Insufficient memory to allocate compression state for %s\n",
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filename);
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filename);
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// unmap file that was mmaped in the constructor
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// unmap file that was mmapped in the constructor
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// This is done here to make sure that gzip and open don't muck with our
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// This is done here to make sure that gzip and open don't muck with our
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// nice large space of memory before we reallocate it
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// nice large space of memory before we reallocate it
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munmap((char*)pmemAddr, size());
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munmap((char*)pmemAddr, size());
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@ -70,7 +70,7 @@ class Request : public FastAlloc
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/** The request is to an uncacheable address. */
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/** The request is to an uncacheable address. */
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static const FlagsType UNCACHEABLE = 0x00001000;
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static const FlagsType UNCACHEABLE = 0x00001000;
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/** This request is to a memory mapped register. */
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/** This request is to a memory mapped register. */
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static const FlagsType MMAPED_IPR = 0x00002000;
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static const FlagsType MMAPPED_IPR = 0x00002000;
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/** This request is a clear exclusive. */
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/** This request is a clear exclusive. */
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static const FlagsType CLEAR_LL = 0x00004000;
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static const FlagsType CLEAR_LL = 0x00004000;
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bool isLocked() const { return _flags.isSet(LOCKED); }
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bool isLocked() const { return _flags.isSet(LOCKED); }
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bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
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bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
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bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
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bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
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bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
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bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
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bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
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bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
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};
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};
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