Spelling: Fix the a spelling error by changing mmaped to mmapped.

There may not be a formally correct spelling for the past tense of mmap, but
mmapped is the spelling Google doesn't try to autocorrect. This makes sense
because it mirrors the past tense of map->mapped and not the past tense of
cape->caped.

--HG--
rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh
rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh
rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh
rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh
rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh
rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh

src/arch/SConscript

@@ -50,7 +50,7 @@ isa_switch_hdrs = Split('''
         kernel_stats.hh
         locked_mem.hh
         microcode_rom.hh
-        mmaped_ipr.hh
+        mmapped_ipr.hh
         mt.hh
         process.hh
         predecoder.hh

src/arch/alpha/mmapped_ipr.hh

@@ -28,8 +28,8 @@
  * Authors: Ali Saidi
  */
 
-#ifndef __ARCH_ALPHA_MMAPED_IPR_HH__
+#ifndef __ARCH_ALPHA_MMAPPED_IPR_HH__
-#define __ARCH_ALPHA_MMAPED_IPR_HH__
+#define __ARCH_ALPHA_MMAPPED_IPR_HH__
 
 /**
  * @file
@@ -60,4 +60,4 @@ handleIprWrite(ThreadContext *xc, Packet *pkt)
 
 } // namespace AlphaISA
 
-#endif // __ARCH_ALPHA_MMAPED_IPR_HH__
+#endif // __ARCH_ALPHA_MMAPPED_IPR_HH__

src/arch/arm/mmapped_ipr.hh

@@ -30,8 +30,8 @@
  *          Stephen Hines
  */
 
-#ifndef __ARCH_ARM_MMAPED_IPR_HH__
+#ifndef __ARCH_ARM_MMAPPED_IPR_HH__
-#define __ARCH_ARM_MMAPED_IPR_HH__
+#define __ARCH_ARM_MMAPPED_IPR_HH__
 
 /**
  * @file

src/arch/mips/mmapped_ipr.hh

@@ -28,8 +28,8 @@
  * Authors: Ali Saidi
  */
 
-#ifndef __ARCH_MIPS_MMAPED_IPR_HH__
+#ifndef __ARCH_MIPS_MMAPPED_IPR_HH__
-#define __ARCH_MIPS_MMAPED_IPR_HH__
+#define __ARCH_MIPS_MMAPPED_IPR_HH__
 
 /**
  * @file

src/arch/power/mmapped_ipr.hh

@@ -32,8 +32,8 @@
  *          Timothy M. Jones
  */
 
-#ifndef __ARCH_POWER_MMAPED_IPR_HH__
+#ifndef __ARCH_POWER_MMAPPED_IPR_HH__
-#define __ARCH_POWER_MMAPED_IPR_HH__
+#define __ARCH_POWER_MMAPPED_IPR_HH__
 
 /**
  * @file
@@ -63,4 +63,4 @@ handleIprWrite(ThreadContext *xc, Packet *pkt)
 
 } // namespace PowerISA
 
-#endif // __ARCH_POWER_MMAPED_IPR_HH__
+#endif // __ARCH_POWER_MMAPPED_IPR_HH__

src/arch/sparc/mmapped_ipr.hh

@@ -28,8 +28,8 @@
  * Authors: Ali Saidi
  */
 
-#ifndef __ARCH_SPARC_MMAPED_IPR_HH__
+#ifndef __ARCH_SPARC_MMAPPED_IPR_HH__
-#define __ARCH_SPARC_MMAPED_IPR_HH__
+#define __ARCH_SPARC_MMAPPED_IPR_HH__
 
 /**
  * @file

src/arch/sparc/tlb.cc

@@ -816,7 +816,7 @@ handleSparcErrorRegAccess:
 regAccessOk:
 handleMmuRegAccess:
     DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
-    req->setFlags(Request::MMAPED_IPR);
+    req->setFlags(Request::MMAPPED_IPR);
     req->setPaddr(req->getVaddr());
     return NoFault;
 };

src/arch/x86/mmapped_ipr.hh

@@ -37,8 +37,8 @@
  * Authors: Gabe Black
  */
 
-#ifndef __ARCH_X86_MMAPEDIPR_HH__
+#ifndef __ARCH_X86_MMAPPEDIPR_HH__
-#define __ARCH_X86_MMAPEDIPR_HH__
+#define __ARCH_X86_MMAPPEDIPR_HH__
 
 /**
  * @file
@@ -89,4 +89,4 @@ namespace X86ISA
     }
 };
 
-#endif // __ARCH_X86_MMAPEDIPR_HH__
+#endif // __ARCH_X86_MMAPPEDIPR_HH__

src/arch/x86/tlb.cc

@@ -179,7 +179,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc)
         panic("CPUID memory space not yet implemented!\n");
     } else if (prefix == IntAddrPrefixMSR) {
         vaddr = vaddr >> 3;
-        req->setFlags(Request::MMAPED_IPR);
+        req->setFlags(Request::MMAPPED_IPR);
         Addr regNum = 0;
         switch (vaddr & ~IntAddrPrefixMask) {
           case 0x10:
@@ -508,7 +508,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc)
         // space.
         assert(!(IOPort & ~0xFFFF));
         if (IOPort == 0xCF8 && req->getSize() == 4) {
-            req->setFlags(Request::MMAPED_IPR);
+            req->setFlags(Request::MMAPPED_IPR);
             req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
         } else if ((IOPort & ~mask(2)) == 0xCFC) {
             req->setFlags(Request::UNCACHEABLE);

src/cpu/simple/atomic.cc

@@ -29,7 +29,7 @@
  */
 
 #include "arch/locked_mem.hh"
-#include "arch/mmaped_ipr.hh"
+#include "arch/mmapped_ipr.hh"
 #include "arch/utility.hh"
 #include "base/bigint.hh"
 #include "config/the_isa.hh"
@@ -334,7 +334,7 @@ AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
                     Packet::Broadcast);
             pkt.dataStatic(data);
 
-            if (req->isMmapedIpr())
+            if (req->isMmappedIpr())
                 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
             else {
                 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
@@ -501,7 +501,7 @@ AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
                 Packet pkt = Packet(req, cmd, Packet::Broadcast);
                 pkt.dataStatic(data);
 
-                if (req->isMmapedIpr()) {
+                if (req->isMmappedIpr()) {
                     dcache_latency +=
                         TheISA::handleIprWrite(thread->getTC(), &pkt);
                 } else {

src/cpu/simple/timing.cc

@@ -41,7 +41,7 @@
  */
 
 #include "arch/locked_mem.hh"
-#include "arch/mmaped_ipr.hh"
+#include "arch/mmapped_ipr.hh"
 #include "arch/utility.hh"
 #include "base/bigint.hh"
 #include "config/the_isa.hh"
@@ -264,7 +264,7 @@ bool
 TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
 {
     RequestPtr req = pkt->req;
-    if (req->isMmapedIpr()) {
+    if (req->isMmappedIpr()) {
         Tick delay;
         delay = TheISA::handleIprRead(thread->getTC(), pkt);
         new IprEvent(pkt, this, nextCycle(curTick() + delay));
@@ -401,7 +401,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
 {
     pkt1 = pkt2 = NULL;
 
-    assert(!req1->isMmapedIpr() && !req2->isMmapedIpr());
+    assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
 
     if (req->getFlags().isSet(Request::NO_ACCESS)) {
         buildPacket(pkt1, req, read);
@@ -536,7 +536,7 @@ bool
 TimingSimpleCPU::handleWritePacket()
 {
     RequestPtr req = dcache_pkt->req;
-    if (req->isMmapedIpr()) {
+    if (req->isMmappedIpr()) {
         Tick delay;
         delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
         new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));

src/mem/physical.cc

@@ -548,7 +548,7 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
         fatal("Insufficient memory to allocate compression state for %s\n",
                 filename);
 
-    // unmap file that was mmaped in the constructor
+    // unmap file that was mmapped in the constructor
     // This is done here to make sure that gzip and open don't muck with our
     // nice large space of memory before we reallocate it
     munmap((char*)pmemAddr, size());

src/mem/request.hh

@@ -70,7 +70,7 @@ class Request : public FastAlloc
     /** The request is to an uncacheable address. */
     static const FlagsType UNCACHEABLE                 = 0x00001000;
     /** This request is to a memory mapped register. */
-    static const FlagsType MMAPED_IPR                  = 0x00002000;
+    static const FlagsType MMAPPED_IPR                  = 0x00002000;
     /** This request is a clear exclusive. */
     static const FlagsType CLEAR_LL                    = 0x00004000;
 
@@ -453,7 +453,7 @@ class Request : public FastAlloc
     bool isLocked() const { return _flags.isSet(LOCKED); }
     bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
     bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
-    bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
+    bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
     bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
 };