some small general fixes to make everythign work nicely with other ISAs, now we can merge back with newmem.
exetrace.cc: wrap this variable between FULL_SYSTEM #ifs mmaped_ipr.hh: fix for build miscregfile.cc: fixes for HPSTATE access during SE mode src/arch/sparc/miscregfile.cc: fixes for HPSTATE access during SE mode src/arch/mips/mmaped_ipr.hh: fix for build src/cpu/exetrace.cc: wrap this variable between FULL_SYSTEM #ifs --HG-- extra : convert_revision : c5b9d56ab99018a91d04de47ba1d5ca7768590bb
This commit is contained in:
parent
fbc796b347
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3 changed files with 18 additions and 5 deletions
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@ -37,8 +37,10 @@
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* ISA-specific helper functions for memory mapped IPR accesses.
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* ISA-specific helper functions for memory mapped IPR accesses.
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*/
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*/
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#include "base/misc.hh"
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#include "mem/packet.hh"
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#include "mem/packet.hh"
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class ThreadContext;
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namespace MipsISA
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namespace MipsISA
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{
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{
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@ -48,7 +50,6 @@ handleIprRead(ThreadContext *xc, Packet *pkt)
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panic("No implementation for handleIprRead in MIPS\n");
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panic("No implementation for handleIprRead in MIPS\n");
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}
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}
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inline Tick
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inline Tick
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handleIprWrite(ThreadContext *xc, Packet *pkt)
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handleIprWrite(ThreadContext *xc, Packet *pkt)
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{
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{
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@ -341,7 +341,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
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case MISCREG_SOFTINT:
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case MISCREG_SOFTINT:
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case MISCREG_TICK_CMPR:
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case MISCREG_TICK_CMPR:
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case MISCREG_STICK_CMPR:
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case MISCREG_STICK_CMPR:
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case MISCREG_HPSTATE:
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case MISCREG_HINTP:
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case MISCREG_HINTP:
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case MISCREG_HTSTATE:
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case MISCREG_HTSTATE:
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case MISCREG_HTBA:
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case MISCREG_HTBA:
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@ -357,9 +356,16 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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case MISCREG_HPSTATE:
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return readFSRegWithEffect(miscReg, tc);
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return readFSRegWithEffect(miscReg, tc);
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#else
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#else
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panic("Accessing Fullsystem register is SE mode\n");
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case MISCREG_HPSTATE:
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//HPSTATE is special because because sometimes in privilege checks for instructions
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//it will read HPSTATE to make sure the priv. level is ok
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//So, we'll just have to tell it it isn't, instead of panicing.
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return 0;
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panic("Accessing Fullsystem register %s in SE mode\n",getMiscRegName(miscReg));
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#endif
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#endif
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}
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}
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@ -633,7 +639,6 @@ void MiscRegFile::setRegWithEffect(int miscReg,
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case MISCREG_SOFTINT:
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case MISCREG_SOFTINT:
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case MISCREG_TICK_CMPR:
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case MISCREG_TICK_CMPR:
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case MISCREG_STICK_CMPR:
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case MISCREG_STICK_CMPR:
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case MISCREG_HPSTATE:
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case MISCREG_HINTP:
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case MISCREG_HINTP:
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case MISCREG_HTSTATE:
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case MISCREG_HTSTATE:
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case MISCREG_HTBA:
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case MISCREG_HTBA:
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@ -649,10 +654,15 @@ void MiscRegFile::setRegWithEffect(int miscReg,
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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case MISCREG_HPSTATE:
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setFSRegWithEffect(miscReg, val, tc);
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setFSRegWithEffect(miscReg, val, tc);
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return;
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return;
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#else
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#else
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panic("Accessing Fullsystem register is SE mode\n");
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case MISCREG_HPSTATE:
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//HPSTATE is special because normal trap processing saves HPSTATE when
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//it goes into a trap, and restores it when it returns.
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return;
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panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
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#endif
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#endif
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}
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}
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setReg(miscReg, val);
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setReg(miscReg, val);
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@ -57,7 +57,9 @@
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using namespace std;
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using namespace std;
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using namespace TheISA;
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using namespace TheISA;
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#if THE_ISA == SPARC_ISA && FULL_SYSTEM
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static int diffcount = 0;
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static int diffcount = 0;
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#endif
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namespace Trace {
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namespace Trace {
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SharedData *shared_data = NULL;
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SharedData *shared_data = NULL;
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