couple more bug fixes for intel nic

src/dev/i8254xGBe.cc:
src/dev/i8254xGBe.hh:
    couple more bug fixes

--HG--
extra : convert_revision : ae5b806528c1ec06f0091e1f6e50fc0721057ddb
This commit is contained in:
Ali Saidi 2007-05-14 16:37:00 -04:00
parent ea4e6f2e3d
commit 57104ea5f9
3 changed files with 30 additions and 6 deletions

View file

@ -1,7 +1,4 @@
echo "switching cpus" insmod /modules/devtime.ko dataAddr=0x9000008 count=100
m5 switchcpu
echo "done"
insmod /modules/devtime.ko dataAddr=0x9000004 count=100
rmmod devtime rmmod devtime
insmod /modules/devtime.ko dataAddr=0x1a0000300 count=100 insmod /modules/devtime.ko dataAddr=0x1a0000300 count=100
rmmod devtime rmmod devtime

View file

@ -656,7 +656,7 @@ IGbE::RxDescCache::writePacket(EthPacketPtr packet)
return false; return false;
pktPtr = packet; pktPtr = packet;
pktDone = false;
igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf), igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf),
packet->length, &pktEvent, packet->data); packet->length, &pktEvent, packet->data);
return true; return true;
@ -683,8 +683,12 @@ IGbE::RxDescCache::pktComplete()
uint8_t status = RXDS_DD | RXDS_EOP; uint8_t status = RXDS_DD | RXDS_EOP;
uint8_t err = 0; uint8_t err = 0;
IpPtr ip(pktPtr); IpPtr ip(pktPtr);
if (ip) { if (ip) {
DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", ip->id());
if (igbe->regs.rxcsum.ipofld()) { if (igbe->regs.rxcsum.ipofld()) {
DPRINTF(EthernetDesc, "Checking IP checksum\n"); DPRINTF(EthernetDesc, "Checking IP checksum\n");
status |= RXDS_IPCS; status |= RXDS_IPCS;
@ -715,7 +719,10 @@ IGbE::RxDescCache::pktComplete()
err |= RXDE_TCPE; err |= RXDE_TCPE;
} }
} }
} // if ip } else { // if ip
DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n");
}
desc->status = htole(status); desc->status = htole(status);
desc->errors = htole(err); desc->errors = htole(err);
@ -912,10 +919,20 @@ IGbE::TxDescCache::pktComplete()
DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2); DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2);
if (DTRACE(EthernetDesc)) {
IpPtr ip(pktPtr);
if (ip)
DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n",
ip->id());
else
DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n");
}
// Checksums are only ofloaded for new descriptor types // Checksums are only ofloaded for new descriptor types
if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) { if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) {
DPRINTF(EthernetDesc, "Calculating checksums for packet\n"); DPRINTF(EthernetDesc, "Calculating checksums for packet\n");
IpPtr ip(pktPtr); IpPtr ip(pktPtr);
if (TxdOp::ixsm(desc)) { if (TxdOp::ixsm(desc)) {
ip->sum(0); ip->sum(0);
ip->sum(cksum(ip)); ip->sum(cksum(ip));
@ -1192,6 +1209,7 @@ IGbE::rxStateMachine()
// If the packet is done check for interrupts/descriptors/etc // If the packet is done check for interrupts/descriptors/etc
if (rxDescCache.packetDone()) { if (rxDescCache.packetDone()) {
rxDmaPacket = false;
DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n"); DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n");
int descLeft = rxDescCache.descLeft(); int descLeft = rxDescCache.descLeft();
switch (regs.rctl.rdmts()) { switch (regs.rctl.rdmts()) {
@ -1236,6 +1254,12 @@ IGbE::rxStateMachine()
return; return;
} }
if (rxDmaPacket) {
DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
rxTick = false;
return;
}
if (!rxDescCache.descUnused()) { if (!rxDescCache.descUnused()) {
DPRINTF(EthernetSM, "RXS: No descriptors available in cache, stopping ticking\n"); DPRINTF(EthernetSM, "RXS: No descriptors available in cache, stopping ticking\n");
rxTick = false; rxTick = false;
@ -1262,6 +1286,7 @@ IGbE::rxStateMachine()
rxFifo.pop(); rxFifo.pop();
DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n"); DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
rxTick = false; rxTick = false;
rxDmaPacket = true;
} }
void void

View file

@ -80,6 +80,8 @@ class IGbE : public PciDev
bool txTick; bool txTick;
bool txFifoTick; bool txFifoTick;
bool rxDmaPacket;
// Event and function to deal with RDTR timer expiring // Event and function to deal with RDTR timer expiring
void rdtrProcess() { void rdtrProcess() {
rxDescCache.writeback(0); rxDescCache.writeback(0);