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ISA: Replace the translate functions in the TLBs with translateAtomic.

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This commit is contained in:
Gabe Black 2009-02-25 10:15:44 -08:00
parent a1aba01a02
commit 5605079b1f
21 changed files with 40 additions and 38 deletions
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4
src/arch/alpha/tlb.cc
View file

@ -317,7 +317,7 @@ ITB::regStats()
}
Fault
ITB::translate(RequestPtr &req, ThreadContext *tc)
ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
if (FULL_SYSTEM && PcPAL(req->getPC()))
@ -479,7 +479,7 @@ DTB::regStats()
}
Fault
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
{
Addr pc = tc->readPC();

4
src/arch/alpha/tlb.hh
View file

@ -131,7 +131,7 @@ class ITB : public TLB
ITB(const Params *p);
virtual void regStats();
Fault translate(RequestPtr &req, ThreadContext *tc);
Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
};
class DTB : public TLB
@ -155,7 +155,7 @@ class DTB : public TLB
DTB(const Params *p);
virtual void regStats();
Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
};
} // namespace AlphaISA

4
src/arch/mips/tlb.cc
View file

@ -310,7 +310,7 @@ TLB::regStats()
}
Fault
ITB::translate(RequestPtr &req, ThreadContext *tc)
ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
{
#if !FULL_SYSTEM
Process * p = tc->getProcessPtr();
@ -427,7 +427,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
}
Fault
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
{
#if !FULL_SYSTEM
Process * p = tc->getProcessPtr();

5
src/arch/mips/tlb.hh
View file

@ -145,7 +145,7 @@ class ITB : public TLB {
typedef MipsTLBParams Params;
ITB(const Params *p);
Fault translate(RequestPtr &req, ThreadContext *tc);
Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
};
class DTB : public TLB {
@ -153,7 +153,8 @@ class DTB : public TLB {
typedef MipsTLBParams Params;
DTB(const Params *p);
Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
Fault translateAtomic(RequestPtr &req, ThreadContext *tc,
bool write = false);
};
class UTB : public ITB, public DTB {

4
src/arch/sparc/tlb.cc
View file

@ -436,7 +436,7 @@ DTB::writeSfsr(Addr a, bool write, ContextType ct,
}
Fault
ITB::translate(RequestPtr &req, ThreadContext *tc)
ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
{
uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
@ -549,7 +549,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
}
Fault
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
{
/*
* @todo this could really use some profiling and fixing to make

4
src/arch/sparc/tlb.hh
View file

@ -177,7 +177,7 @@ class ITB : public TLB
cacheEntry = NULL;
}
Fault translate(RequestPtr &req, ThreadContext *tc);
Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
private:
void writeSfsr(bool write, ContextType ct,
bool se, FaultTypes ft, int asi);
@ -199,7 +199,7 @@ class DTB : public TLB
cacheEntry[1] = NULL;
}
Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);

11
src/arch/x86/tlb.cc
View file

@ -190,7 +190,8 @@ TLB::demapPage(Addr va, uint64_t asn)
template<class TlbFault>
Fault
TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
TLB::translateAtomic(RequestPtr &req, ThreadContext *tc,
bool write, bool execute)
{
Addr vaddr = req->getVaddr();
DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
@ -662,15 +663,15 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
};
Fault
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
{
return TLB::translate<FakeDTLBFault>(req, tc, write, false);
return TLB::translateAtomic<FakeDTLBFault>(req, tc, write, false);
}
Fault
ITB::translate(RequestPtr &req, ThreadContext *tc)
ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
{
return TLB::translate<FakeITLBFault>(req, tc, false, true);
return TLB::translateAtomic<FakeITLBFault>(req, tc, false, true);
}
#if FULL_SYSTEM

6
src/arch/x86/tlb.hh
View file

@ -138,7 +138,7 @@ namespace X86ISA
EntryList entryList;
template<class TlbFault>
Fault translate(RequestPtr &req, ThreadContext *tc,
Fault translateAtomic(RequestPtr &req, ThreadContext *tc,
bool write, bool execute);
public:
@ -159,7 +159,7 @@ namespace X86ISA
_allowNX = false;
}
Fault translate(RequestPtr &req, ThreadContext *tc);
Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
friend class DTB;
};
@ -172,7 +172,7 @@ namespace X86ISA
{
_allowNX = true;
}
Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);

4
src/cpu/base_dyn_inst.hh
View file

@ -860,7 +860,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
req->setThreadContext(thread->contextId(), threadNumber);
fault = cpu->dtb->translate(req, thread->getTC(), false);
fault = cpu->dtb->translateAtomic(req, thread->getTC(), false);
if (req->isUncacheable())
isUncacheable = true;
@ -916,7 +916,7 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
req->setThreadContext(thread->contextId(), threadNumber);
fault = cpu->dtb->translate(req, thread->getTC(), true);
fault = cpu->dtb->translateAtomic(req, thread->getTC(), true);
if (req->isUncacheable())
isUncacheable = true;

4
src/cpu/checker/cpu.cc
View file

@ -159,7 +159,7 @@ CheckerCPU::read(Addr addr, T &data, unsigned flags)
memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
dtb->translate(memReq, tc, false);
dtb->translateAtomic(memReq, tc, false);
PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
@ -229,7 +229,7 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
dtb->translate(memReq, tc, true);
dtb->translateAtomic(memReq, tc, true);
// Can compare the write data and result only if it's cacheable,
// not a store conditional, or is a store conditional that

2
src/cpu/checker/cpu_impl.hh
View file

@ -155,7 +155,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
fetch_PC, thread->contextId(),
inst->threadNumber);
bool succeeded = itb->translate(memReq, thread);
bool succeeded = itb->translateAtomic(memReq, thread);
if (!succeeded) {
if (inst->getFault() == NoFault) {

4
src/cpu/inorder/resources/tlb_unit.cc
View file

@ -98,7 +98,7 @@ TLBUnit::execute(int slot_idx)
case FetchLookup:
{
tlb_req->fault =
this->cpu->itb->translate(tlb_req->memReq,
this->cpu->itb->translateAtomic(tlb_req->memReq,
cpu->thread[tid]->getTC());
if (tlb_req->fault != NoFault) {
@ -129,7 +129,7 @@ TLBUnit::execute(int slot_idx)
tid, seq_num, tlb_req->memReq->getVaddr());
tlb_req->fault =
this->cpu->itb->translate(tlb_req->memReq,
this->cpu->itb->translateAtomic(tlb_req->memReq,
cpu->thread[tid]->getTC());
if (tlb_req->fault != NoFault) {

2
src/cpu/o3/fetch_impl.hh
View file

@ -599,7 +599,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
memReq[tid] = mem_req;
// Translate the instruction request.
fault = cpu->itb->translate(mem_req, cpu->thread[tid]->getTC());
fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC());
// In the case of faults, the fetch stage may need to stall and wait
// for the ITB miss to be handled.

2
src/cpu/ozone/front_end_impl.hh
View file

@ -480,7 +480,7 @@ FrontEnd<Impl>::fetchCacheLine()
PC, cpu->thread->contextId());
// Translate the instruction request.
fault = cpu->itb->translate(memReq, thread);
fault = cpu->itb->translateAtomic(memReq, thread);
// Now do the timing access to see whether or not the instruction
// exists within the cache.

4
src/cpu/ozone/inorder_back_end.hh
View file

@ -204,7 +204,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
Fault fault = cpu->dtb->translate(memReq, thread->getTC(), false);
Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), false);
// if we have a cache, do cache access too
if (fault == NoFault && dcacheInterface) {
@ -245,7 +245,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
Fault fault = cpu->dtb->translate(memReq, thread->getTC(), true);
Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), true);
if (fault == NoFault && dcacheInterface) {
memReq->cmd = Write;

4
src/cpu/simple/atomic.cc
View file

@ -314,7 +314,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
req->setVirt(0, addr, dataSize, flags, thread->readPC());
// translate to physical address
Fault fault = thread->dtb->translate(req, tc, false);
Fault fault = thread->dtb->translateAtomic(req, tc, false);
// Now do the access.
if (fault == NoFault) {
@ -452,7 +452,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
req->setVirt(0, addr, dataSize, flags, thread->readPC());
// translate to physical address
Fault fault = thread->dtb->translate(req, tc, true);
Fault fault = thread->dtb->translateAtomic(req, tc, true);
// Now do the access.
if (fault == NoFault) {

2
src/cpu/simple/base.cc
View file

@ -347,7 +347,7 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
Addr fetchPC = (threadPC & PCMask) + fetchOffset;
req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
Fault fault = thread->itb->translate(req, tc);
Fault fault = thread->itb->translateAtomic(req, tc);
return fault;
}

2
src/cpu/simple/timing.cc
View file

@ -314,7 +314,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
Fault
TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr &req, bool read)
{
Fault fault = thread->dtb->translate(req, tc, !read);
Fault fault = thread->dtb->translateAtomic(req, tc, !read);
MemCmd cmd;
if (fault != NoFault) {
delete req;

2
src/cpu/simple_thread.hh
View file

@ -139,7 +139,7 @@ class SimpleThread : public ThreadState
/***************************************************************
* SimpleThread functions to provide CPU with access to various
* state, and to provide address translation methods.
* state.
**************************************************************/
/** Returns the pointer to this SimpleThread's ThreadContext. Used

2
src/sim/tlb.cc
View file

@ -34,7 +34,7 @@
#include "sim/tlb.hh"
Fault
GenericTLB::translate(RequestPtr req, ThreadContext * tc, bool)
GenericTLB::translateAtomic(RequestPtr req, ThreadContext * tc, bool)
{
#if FULL_SYSTEM
panic("Generic translation shouldn't be used in full system mode.\n");

2
src/sim/tlb.hh
View file

@ -58,7 +58,7 @@ class GenericTLB : public BaseTLB
public:
void demapPage(Addr vaddr, uint64_t asn);
Fault translate(RequestPtr req, ThreadContext *tc, bool=false);
Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool=false);
};
#endif // __ARCH_SPARC_TLB_HH__