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Merge zizzer:/bk/sparcfs

Browse source 
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 07119747d9b08ea51f21942e36f22afcc62f16e1
This commit is contained in:
Lisa Hsu 2006-12-01 15:04:48 -05:00
commit 55b4ea0444
14 changed files with 3292 additions and 24 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
configs/boot/nat-netperf-maerts-client.rcS
View file

@ -41,7 +41,6 @@ eval $SHORT
echo "netperf benchmark" echo "netperf benchmark"
echo $LONG echo $LONG
/sbin/m5 ivlb 1
/sbin/m5 resetstats /sbin/m5 resetstats
/sbin/m5 dumpresetstats 200000000 2000000000 /sbin/m5 dumpresetstats 200000000 2000000000
/sbin/m5 checkpoint 200000000 2000000000 /sbin/m5 checkpoint 200000000 2000000000

2
configs/boot/netperf-maerts-client.rcS
View file

@ -21,7 +21,7 @@ echo "100000" > /proc/sys/net/core/netdev_max_backlog
echo -n "waiting for server..." echo -n "waiting for server..."
/usr/bin/netcat -c -l -p 8000 /usr/bin/netcat -c -l -p 8000
BINARY=/benchmarks/netperf/netperf BINARY=/benchmarks/netperf-bin/netperf
TEST="TCP_MAERTS" TEST="TCP_MAERTS"
SHORT_ARGS="-l -100k" SHORT_ARGS="-l -100k"
LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144" LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144"

4
tests/SConscript
View file

@ -205,7 +205,9 @@ if env['FULL_SYSTEM']:
configs += ['tsunami-simple-atomic', configs += ['tsunami-simple-atomic',
'tsunami-simple-timing', 'tsunami-simple-timing',
'tsunami-simple-atomic-dual', 'tsunami-simple-atomic-dual',
'tsunami-simple-timing-dual'] 'tsunami-simple-timing-dual',
'twosys-tsunami-simple-atomic']
else: else:
configs += ['simple-atomic', 'simple-timing', 'o3-timing'] configs += ['simple-atomic', 'simple-timing', 'o3-timing']

47
tests/configs/twosys-tsunami-simple-atomic.py Normal file
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@ -0,0 +1,47 @@
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Lisa Hsu
import m5
from m5.objects import *
m5.AddToPath('../configs/common')
from FSConfig import *
from Benchmarks import *
test_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-stream-client.rcS'))
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
test_sys.cpu.connectMemPorts(test_sys.membus)
drive_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-server.rcS'))
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
drive_sys.cpu.connectMemPorts(drive_sys.membus)
root = makeDualRoot(test_sys, drive_sys, "ethertrace")
maxtick = 199999999

41
tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 48159 # Simulator instruction rate (inst/s) host_inst_rate 158849 # Simulator instruction rate (inst/s)
host_mem_usage 179620 # Number of bytes of host memory used host_mem_usage 179428 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host host_seconds 0.03 # Real time elapsed on the host
host_tick_rate 15510230 # Simulator tick rate (ticks/s) host_tick_rate 50697812 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4863 # Number of instructions simulated sim_insts 4863 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated sim_seconds 0.000002 # Number of seconds simulated
@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu
system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3977.572464 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 3977.572464 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1131 # number of overall hits system.cpu.dcache.overall_hits 1131 # number of overall hits
system.cpu.dcache.overall_miss_latency 548905 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 548905 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses
@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu
system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3977.960938 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 3977.960938 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 4608 # number of overall hits system.cpu.icache.overall_hits 4608 # number of overall hits
system.cpu.icache.overall_miss_latency 1018358 # number of overall miss cycles system.cpu.icache.overall_miss_latency 1018358 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses
@ -143,49 +143,48 @@ system.cpu.icache.total_refs 4608 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 394 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses 391 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2985.429668 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency 2985.429668 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1984.429668 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1984.429668 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1167303 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency 1167303 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.992386 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 775912 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency 775912 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992386 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.007673 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 394 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2985.429668 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 2985.429668 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 1167303 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 1167303 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992386 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 775912 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 775912 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.992386 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 394 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2985.429668 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 2985.429668 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 3 # number of overall hits system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 1167303 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 1167303 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992386 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 391 # number of overall misses system.cpu.l2cache.overall_misses 391 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 775912 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 775912 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.992386 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -202,7 +201,7 @@ system.cpu.l2cache.replacements 0 # nu
system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 195.424915 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 195.424915 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles

1205
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini Normal file
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File diff suppressed because it is too large Load diff

1101
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out Normal file
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File diff suppressed because it is too large Load diff

111
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console Normal file
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@ -0,0 +1,111 @@
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
Got Configuration 623
memsize 8000000 pages 4000
First free page after ROM 0xFFFFFC0000018000
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
CPU Clock at 1000000 MHz IntrClockFrequency=1024
Booting with 1 processor(s)
KSP: 0x20043FE8 PTBR 0x20
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
Memory cluster 0 [0 - 392]
Memory cluster 1 [392 - 15992]
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
unix_boot_mem ends at FFFFFC0000076000
k_argc = 0
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
CallbackFixup 0 18000, t7=FFFFFC000070C000
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
Major Options: SMP LEGACY_START VERBOSE_MCHECK
Command line: root=/dev/hda1 console=ttyS0
memcluster 0, usage 1, start 0, end 392
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0
PID hash table entries: 1024 (order: 10, 32768 bytes)
Using epoch = 1900
Console: colour dummy device 80x25
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
Mount-cache hash table entries: 512
SMP mode deactivated.
Brought up 1 CPUs
SMP: Total of 1 processors activated (1998756.81 BogoMIPS).
NET: Registered protocol family 16
EISA bus registered
pci: enabling save/restore of SRM state
SCSI subsystem initialized
srm_env: version 0.0.5 loaded successfully
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
Initializing Cryptographic API
rtc: Standard PC (1900) epoch (1900) detected
Real Time Clock Driver v1.12
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing.
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg
tun: Universal TUN/TAP device driver, 1.6
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB
hda: 409248 sectors (209 MB), CHS=406/16/63, UDMA(33)
hda: cache flushes not supported
hda: hda1
hdb: max request size: 128KiB
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
hdb: cache flushes not supported
hdb: unknown partition table
mice: PS/2 mouse device common for all mice
NET: Registered protocol family 2
IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
TCP established hash table entries: 16384 (order: 5, 262144 bytes)
TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
TCP: Hash tables configured (established 16384 bind 16384)
TCP reno registered
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
ip_tables: (C) 2000-2002 Netfilter core team
arp_tables: (C) 2002 David S. Miller
TCP bic registered
Initializing IPsec netlink socket
NET: Registered protocol family 1
NET: Registered protocol family 17
NET: Registered protocol family 15
Bridge firewalling registered
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 224k freed
init started: BusyBox v1.1.0 (2006.10.31-01:25+0000) multi-call binary
mounting filesystems...
loading script...
setting up network...
eth0: link now 1000F mbps, full duplex and up.
running netserver...
Starting netserver at port 12865
signal client to begin...done.
starting bash...
#

120
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console Normal file
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@ -0,0 +1,120 @@
M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
Got Configuration 623
memsize 8000000 pages 4000
First free page after ROM 0xFFFFFC0000018000
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
CPU Clock at 1000000 MHz IntrClockFrequency=1024
Booting with 1 processor(s)
KSP: 0x20043FE8 PTBR 0x20
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
Memory cluster 0 [0 - 392]
Memory cluster 1 [392 - 15992]
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
unix_boot_mem ends at FFFFFC0000076000
k_argc = 0
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
CallbackFixup 0 18000, t7=FFFFFC000070C000
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
Major Options: SMP LEGACY_START VERBOSE_MCHECK
Command line: root=/dev/hda1 console=ttyS0
memcluster 0, usage 1, start 0, end 392
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0
PID hash table entries: 1024 (order: 10, 32768 bytes)
Using epoch = 1900
Console: colour dummy device 80x25
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes)
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes)
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
Mount-cache hash table entries: 512
SMP mode deactivated.
Brought up 1 CPUs
SMP: Total of 1 processors activated (1998756.81 BogoMIPS).
NET: Registered protocol family 16
EISA bus registered
pci: enabling save/restore of SRM state
SCSI subsystem initialized
srm_env: version 0.0.5 loaded successfully
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
Initializing Cryptographic API
rtc: Standard PC (1900) epoch (1900) detected
Real Time Clock Driver v1.12
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
loop: loaded (max 8 devices)
nbd: registered device at major 43
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing.
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg
tun: Universal TUN/TAP device driver, 1.6
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
PIIX4: IDE controller at PCI slot 0000:00:00.0
PIIX4: chipset revision 0
PIIX4: 100% native mode on irq 31
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
hda: M5 IDE Disk, ATA DISK drive
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB
hda: 409248 sectors (209 MB), CHS=406/16/63, UDMA(33)
hda: cache flushes not supported
hda: hda1
hdb: max request size: 128KiB
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
hdb: cache flushes not supported
hdb: unknown partition table
mice: PS/2 mouse device common for all mice
NET: Registered protocol family 2
IP route cache hash table entries: 4096 (order: 2, 32768 bytes)
TCP established hash table entries: 16384 (order: 5, 262144 bytes)
TCP bind hash table entries: 16384 (order: 5, 262144 bytes)
TCP: Hash tables configured (established 16384 bind 16384)
TCP reno registered
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
ip_tables: (C) 2000-2002 Netfilter core team
arp_tables: (C) 2002 David S. Miller
TCP bic registered
Initializing IPsec netlink socket
NET: Registered protocol family 1
NET: Registered protocol family 17
NET: Registered protocol family 15
Bridge firewalling registered
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 224k freed
init started: BusyBox v1.1.0 (2006.10.31-01:25+0000) multi-call binary
mounting filesystems...
loading script...
setting up network...
eth0: link now 1000F mbps, full duplex and up.
waiting for server...server ready
starting test...
netperf warmup
/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -l -100k
TCP STREAM TEST to 10.0.0.1 : dirty data
Recv Send Send
Socket Socket Message Elapsed
Size Size Size Time Throughput
bytes bytes bytes secs. 10^6bits/sec
5000000 5000000 5000000 1.29 30.91
netperf benchmark
/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144
TCP STREAM TEST to 10.0.0.1 : dirty data

476
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt Normal file
View file

@ -0,0 +1,476 @@
---------- Begin Simulation Statistics ----------
drivesys.cpu.dtb.accesses 401302 # DTB accesses
drivesys.cpu.dtb.acv 40 # DTB access violations
drivesys.cpu.dtb.hits 624298 # DTB hits
drivesys.cpu.dtb.misses 569 # DTB misses
drivesys.cpu.dtb.read_accesses 268057 # DTB read accesses
drivesys.cpu.dtb.read_acv 30 # DTB read access violations
drivesys.cpu.dtb.read_hits 393538 # DTB read hits
drivesys.cpu.dtb.read_misses 487 # DTB read misses
drivesys.cpu.dtb.write_accesses 133245 # DTB write accesses
drivesys.cpu.dtb.write_acv 10 # DTB write access violations
drivesys.cpu.dtb.write_hits 230760 # DTB write hits
drivesys.cpu.dtb.write_misses 82 # DTB write misses
drivesys.cpu.idle_fraction 1.000000 # Percentage of idle cycles
drivesys.cpu.itb.accesses 1337980 # ITB accesses
drivesys.cpu.itb.acv 22 # ITB acv
drivesys.cpu.itb.hits 1337786 # ITB hits
drivesys.cpu.itb.misses 194 # ITB misses
drivesys.cpu.kern.callpal 4443 # number of callpals executed
drivesys.cpu.kern.callpal_swpctx 70 1.58% 1.58% # number of callpals executed
drivesys.cpu.kern.callpal_tbi 5 0.11% 1.69% # number of callpals executed
drivesys.cpu.kern.callpal_swpipl 3654 82.24% 83.93% # number of callpals executed
drivesys.cpu.kern.callpal_rdps 359 8.08% 92.01% # number of callpals executed
drivesys.cpu.kern.callpal_rdusp 1 0.02% 92.03% # number of callpals executed
drivesys.cpu.kern.callpal_rti 322 7.25% 99.28% # number of callpals executed
drivesys.cpu.kern.callpal_callsys 25 0.56% 99.84% # number of callpals executed
drivesys.cpu.kern.callpal_imb 7 0.16% 100.00% # number of callpals executed
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
drivesys.cpu.kern.inst.hwrei 5483 # number of hwrei instructions executed
drivesys.cpu.kern.inst.quiesce 215 # number of quiesce instructions executed
drivesys.cpu.kern.ipl_count 4191 # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count_0 1189 28.37% 28.37% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count_21 10 0.24% 28.61% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count_22 205 4.89% 33.50% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count_31 2787 66.50% 100.00% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_good 2593 # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_ticks 199572064366 # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks_0 199571744403 100.00% 100.00% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks_31 300713 0.00% 100.00% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_used 0.618707 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used_31 0.426624 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.mode_good_kernel 110
drivesys.cpu.kern.mode_good_user 107
drivesys.cpu.kern.mode_good_idle 3
drivesys.cpu.kern.mode_switch_kernel 174 # number of protection mode switches
drivesys.cpu.kern.mode_switch_user 107 # number of protection mode switches
drivesys.cpu.kern.mode_switch_idle 218 # number of protection mode switches
drivesys.cpu.kern.mode_switch_good 0.440882 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_ticks_kernel 263475 0.24% 0.24% # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks_user 1278343 1.18% 1.43% # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks_idle 106483912 98.57% 100.00% # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed
drivesys.cpu.kern.syscall 22 # number of syscalls executed
drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed
drivesys.cpu.kern.syscall_6 3 13.64% 18.18% # number of syscalls executed
drivesys.cpu.kern.syscall_17 2 9.09% 27.27% # number of syscalls executed
drivesys.cpu.kern.syscall_97 1 4.55% 31.82% # number of syscalls executed
drivesys.cpu.kern.syscall_99 2 9.09% 40.91% # number of syscalls executed
drivesys.cpu.kern.syscall_101 2 9.09% 50.00% # number of syscalls executed
drivesys.cpu.kern.syscall_102 3 13.64% 63.64% # number of syscalls executed
drivesys.cpu.kern.syscall_104 1 4.55% 68.18% # number of syscalls executed
drivesys.cpu.kern.syscall_105 3 13.64% 81.82% # number of syscalls executed
drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # number of syscalls executed
drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed
drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed
drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles
drivesys.cpu.numCycles 1959293 # number of cpu cycles simulated
drivesys.cpu.num_insts 1959077 # Number of instructions executed
drivesys.cpu.num_refs 626286 # Number of memory references
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
drivesys.tsunami.ethernet.coalescedRxDesc 1 # average number of RxDesc's coalesced into each post
drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
drivesys.tsunami.ethernet.descDMAReads 5 # Number of descriptors the device read w/ DMA
drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
drivesys.tsunami.ethernet.descDmaReadBytes 120 # number of descriptor bytes read w/ DMA
drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
drivesys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU
drivesys.tsunami.ethernet.postedRxDesc 6 # number of RxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.postedTxIdle 4 # number of TxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
drivesys.tsunami.ethernet.rxBandwidth 38400 # Receive Bandwidth (bits/s)
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
drivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device
drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s)
drivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received
drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device
drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
drivesys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s)
drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes
drivesys.tsunami.ethernet.totPackets 13 # Total Packets
drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR
drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.totalTxIdle 5 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
drivesys.tsunami.ethernet.txBandwidth 31920 # Transmit Bandwidth (bits/s)
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
drivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s)
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
host_inst_rate 38374803 # Simulator instruction rate (inst/s)
host_mem_usage 411180 # Number of bytes of host memory used
host_seconds 7.20 # Real time elapsed on the host
host_tick_rate 27794359444 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 276122825 # Number of instructions simulated
sim_seconds 0.200001 # Number of seconds simulated
sim_ticks 200000789468 # Number of ticks simulated
testsys.cpu.dtb.accesses 335402 # DTB accesses
testsys.cpu.dtb.acv 161 # DTB access violations
testsys.cpu.dtb.hits 1163399 # DTB hits
testsys.cpu.dtb.misses 3815 # DTB misses
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
testsys.cpu.dtb.read_acv 80 # DTB read access violations
testsys.cpu.dtb.read_hits 658556 # DTB read hits
testsys.cpu.dtb.read_misses 3287 # DTB read misses
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
testsys.cpu.dtb.write_acv 81 # DTB write access violations
testsys.cpu.dtb.write_hits 504843 # DTB write hits
testsys.cpu.dtb.write_misses 528 # DTB write misses
testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles
testsys.cpu.itb.accesses 1249804 # ITB accesses
testsys.cpu.itb.acv 69 # ITB acv
testsys.cpu.itb.hits 1248307 # ITB hits
testsys.cpu.itb.misses 1497 # ITB misses
testsys.cpu.kern.callpal 13124 # number of callpals executed
testsys.cpu.kern.callpal_swpctx 440 3.35% 3.35% # number of callpals executed
testsys.cpu.kern.callpal_tbi 20 0.15% 3.51% # number of callpals executed
testsys.cpu.kern.callpal_swpipl 11075 84.39% 87.89% # number of callpals executed
testsys.cpu.kern.callpal_rdps 359 2.74% 90.63% # number of callpals executed
testsys.cpu.kern.callpal_wrusp 3 0.02% 90.65% # number of callpals executed
testsys.cpu.kern.callpal_rdusp 3 0.02% 90.67% # number of callpals executed
testsys.cpu.kern.callpal_rti 1040 7.92% 98.60% # number of callpals executed
testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed
testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
testsys.cpu.kern.inst.hwrei 19054 # number of hwrei instructions executed
testsys.cpu.kern.inst.quiesce 377 # number of quiesce instructions executed
testsys.cpu.kern.ipl_count 12503 # number of times we switched to this ipl
testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count_21 183 1.46% 41.94% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count_22 205 1.64% 43.58% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count_31 7054 56.42% 100.00% # number of times we switched to this ipl
testsys.cpu.kern.ipl_good 10498 # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good_21 183 1.74% 49.90% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_ticks 199569923608 # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks_0 199569308038 100.00% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks_21 30857 0.00% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks_31 567083 0.00% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_used 0.839638 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.mode_good_kernel 654
testsys.cpu.kern.mode_good_user 649
testsys.cpu.kern.mode_good_idle 5
testsys.cpu.kern.mode_switch_kernel 1100 # number of protection mode switches
testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches
testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches
testsys.cpu.kern.mode_switch_good 0.614085 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good_kernel 0.594545 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches
testsys.cpu.kern.mode_ticks_kernel 1821232 2.16% 2.16% # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.42% # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks_idle 81402474 96.58% 100.00% # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 440 # number of times the context was actually changed
testsys.cpu.kern.syscall 83 # number of syscalls executed
testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed
testsys.cpu.kern.syscall_3 7 8.43% 12.05% # number of syscalls executed
testsys.cpu.kern.syscall_4 1 1.20% 13.25% # number of syscalls executed
testsys.cpu.kern.syscall_6 7 8.43% 21.69% # number of syscalls executed
testsys.cpu.kern.syscall_17 7 8.43% 30.12% # number of syscalls executed
testsys.cpu.kern.syscall_19 2 2.41% 32.53% # number of syscalls executed
testsys.cpu.kern.syscall_20 1 1.20% 33.73% # number of syscalls executed
testsys.cpu.kern.syscall_33 3 3.61% 37.35% # number of syscalls executed
testsys.cpu.kern.syscall_45 10 12.05% 49.40% # number of syscalls executed
testsys.cpu.kern.syscall_48 5 6.02% 55.42% # number of syscalls executed
testsys.cpu.kern.syscall_54 1 1.20% 56.63% # number of syscalls executed
testsys.cpu.kern.syscall_59 3 3.61% 60.24% # number of syscalls executed
testsys.cpu.kern.syscall_71 15 18.07% 78.31% # number of syscalls executed
testsys.cpu.kern.syscall_74 4 4.82% 83.13% # number of syscalls executed
testsys.cpu.kern.syscall_97 2 2.41% 85.54% # number of syscalls executed
testsys.cpu.kern.syscall_98 2 2.41% 87.95% # number of syscalls executed
testsys.cpu.kern.syscall_101 2 2.41% 90.36% # number of syscalls executed
testsys.cpu.kern.syscall_102 2 2.41% 92.77% # number of syscalls executed
testsys.cpu.kern.syscall_104 1 1.20% 93.98% # number of syscalls executed
testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed
testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed
testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles
testsys.cpu.numCycles 3566237 # number of cpu cycles simulated
testsys.cpu.num_insts 3564671 # Number of instructions executed
testsys.cpu.num_refs 1173698 # Number of memory references
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
testsys.tsunami.ethernet.descDMAReads 8 # Number of descriptors the device read w/ DMA
testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
testsys.tsunami.ethernet.descDmaReadBytes 192 # number of descriptor bytes read w/ DMA
testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
testsys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU
testsys.tsunami.ethernet.postedRxDesc 4 # number of RxDesc interrupts posted to CPU
testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
testsys.tsunami.ethernet.postedTxIdle 6 # number of TxIdle interrupts posted to CPU
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
testsys.tsunami.ethernet.rxBandwidth 31920 # Receive Bandwidth (bits/s)
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device
testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s)
testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received
testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device
testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
testsys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s)
testsys.tsunami.ethernet.totBytes 1758 # Total Bytes
testsys.tsunami.ethernet.totPackets 13 # Total Packets
testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR
testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
testsys.tsunami.ethernet.totalTxIdle 8 # total number of TxIdle written to ISR
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
testsys.tsunami.ethernet.txBandwidth 38400 # Transmit Bandwidth (bits/s)
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s)
testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted
testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
drivesys.cpu.dtb.accesses 0 # DTB accesses
drivesys.cpu.dtb.acv 0 # DTB access violations
drivesys.cpu.dtb.hits 0 # DTB hits
drivesys.cpu.dtb.misses 0 # DTB misses
drivesys.cpu.dtb.read_accesses 0 # DTB read accesses
drivesys.cpu.dtb.read_acv 0 # DTB read access violations
drivesys.cpu.dtb.read_hits 0 # DTB read hits
drivesys.cpu.dtb.read_misses 0 # DTB read misses
drivesys.cpu.dtb.write_accesses 0 # DTB write accesses
drivesys.cpu.dtb.write_acv 0 # DTB write access violations
drivesys.cpu.dtb.write_hits 0 # DTB write hits
drivesys.cpu.dtb.write_misses 0 # DTB write misses
drivesys.cpu.idle_fraction 1 # Percentage of idle cycles
drivesys.cpu.itb.accesses 0 # ITB accesses
drivesys.cpu.itb.acv 0 # ITB acv
drivesys.cpu.itb.hits 0 # ITB hits
drivesys.cpu.itb.misses 0 # ITB misses
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
drivesys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed
drivesys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
drivesys.cpu.kern.mode_good_kernel 0
drivesys.cpu.kern.mode_good_user 0
drivesys.cpu.kern.mode_good_idle 0
drivesys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches
drivesys.cpu.kern.mode_switch_user 0 # number of protection mode switches
drivesys.cpu.kern.mode_switch_idle 0 # number of protection mode switches
drivesys.cpu.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good_kernel <err: div-0> # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good_user <err: div-0> # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
drivesys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed
drivesys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles
drivesys.cpu.numCycles 0 # number of cpu cycles simulated
drivesys.cpu.num_insts 0 # Number of instructions executed
drivesys.cpu.num_refs 0 # Number of memory references
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
drivesys.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
drivesys.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
drivesys.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
drivesys.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
drivesys.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
drivesys.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
drivesys.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
drivesys.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
drivesys.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
drivesys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
host_inst_rate 76361400719 # Simulator instruction rate (inst/s)
host_mem_usage 411180 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
host_tick_rate 203621244 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 276122825 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
sim_ticks 785978 # Number of ticks simulated
testsys.cpu.dtb.accesses 0 # DTB accesses
testsys.cpu.dtb.acv 0 # DTB access violations
testsys.cpu.dtb.hits 0 # DTB hits
testsys.cpu.dtb.misses 0 # DTB misses
testsys.cpu.dtb.read_accesses 0 # DTB read accesses
testsys.cpu.dtb.read_acv 0 # DTB read access violations
testsys.cpu.dtb.read_hits 0 # DTB read hits
testsys.cpu.dtb.read_misses 0 # DTB read misses
testsys.cpu.dtb.write_accesses 0 # DTB write accesses
testsys.cpu.dtb.write_acv 0 # DTB write access violations
testsys.cpu.dtb.write_hits 0 # DTB write hits
testsys.cpu.dtb.write_misses 0 # DTB write misses
testsys.cpu.idle_fraction 1 # Percentage of idle cycles
testsys.cpu.itb.accesses 0 # ITB accesses
testsys.cpu.itb.acv 0 # ITB acv
testsys.cpu.itb.hits 0 # ITB hits
testsys.cpu.itb.misses 0 # ITB misses
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
testsys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed
testsys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
testsys.cpu.kern.mode_good_kernel 0
testsys.cpu.kern.mode_good_user 0
testsys.cpu.kern.mode_good_idle 0
testsys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches
testsys.cpu.kern.mode_switch_user 0 # number of protection mode switches
testsys.cpu.kern.mode_switch_idle 0 # number of protection mode switches
testsys.cpu.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good_kernel <err: div-0> # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good_user <err: div-0> # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
testsys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 0 # number of times the context was actually changed
testsys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles
testsys.cpu.numCycles 0 # number of cpu cycles simulated
testsys.cpu.num_insts 0 # Number of instructions executed
testsys.cpu.num_refs 0 # Number of memory references
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
testsys.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
testsys.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
testsys.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
testsys.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
testsys.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
testsys.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
testsys.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
testsys.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
testsys.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
testsys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
testsys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
testsys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
---------- End Simulation Statistics ----------

8
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr Normal file
View file

@ -0,0 +1,8 @@
0: testsys.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006
Listening for console connection on port 3456
0: drivesys.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006
Listening for console connection on port 3457
0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7001
warn: Entering event queue @ 0. Starting simulation...
warn: Obsolete M5 instruction ivlb encountered.

17
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout Normal file
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@ -0,0 +1,17 @@
M5 Simulator System
Copyright (c) 2001-2006
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 29 2006 16:48:25
M5 started Fri Dec 1 01:07:49 2006
M5 executing on zed.eecs.umich.edu
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py long/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
WTF
9685900: testsys.sim_console: attach console 0
3327958029: drivesys.sim_console: attach console 0
Resetting stats at cycle 4100234765800!
Resetting stats at cycle 4300235555268!
Exiting @ tick 4300236341246 because checkpoint

28
tests/quick/80.netperf-stream/test.py Normal file
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@ -0,0 +1,28 @@
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Lisa Hsu

155
util/make_release.py Executable file
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@ -0,0 +1,155 @@
#!/usr/bin/env python
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Ali Saidi
# Steve Reinhardt
# Nathan Binkert
import os
import re
import shutil
import sys
from glob import glob
from os import system
from os.path import basename, dirname, exists, isdir, isfile, join as joinpath
def mkdir(*args):
path = joinpath(*args)
os.mkdir(path)
def touch(*args):
path = joinpath(*args)
os.utime(path, None)
def rmtree(*args):
path = joinpath(*args)
for match in glob(path):
if isdir(match):
shutil.rmtree(match)
else:
os.unlink(match)
def remove(*args):
path = joinpath(*args)
for match in glob(path):
if not isdir(match):
os.unlink(match)
def movedir(srcdir, destdir, dir):
src = joinpath(srcdir, dir)
dest = joinpath(destdir, dir)
if not isdir(src):
raise AttributeError
os.makedirs(dirname(dest))
shutil.move(src, dest)
if not isdir('BitKeeper'):
sys.exit('Not in the top level of an m5 tree!')
usage = '%s <destdir> <release name>' % sys.argv[0]
if len(sys.argv) != 3:
sys.exit(usage)
destdir = sys.argv[1]
releasename = sys.argv[2]
if exists(destdir):
if not isdir(destdir):
raise AttributeError, '%s exists, but is not a directory' % destdir
rmtree(destdir)
release_dir = joinpath(destdir, 'release', releasename)
encumbered_dir = joinpath(destdir, 'encumbered', releasename)
mkdir(destdir)
mkdir(destdir, 'release')
mkdir(destdir, 'encumbered')
mkdir(release_dir)
mkdir(encumbered_dir)
system('bk export -tplain -w -r+ %s' % release_dir)
# make sure scons doesn't try to run flex unnecessarily
touch(release_dir, 'src/encumbered/eio/exolex.cc')
# get rid of non-shipping code
rmtree(release_dir, 'src/encumbered/dev')
rmtree(release_dir, 'src/cpu/ozone')
rmtree(release_dir, 'src/mem/cache/tags/split*.cc')
rmtree(release_dir, 'src/mem/cache/tags/split*.hh')
rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.cc')
rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.hh')
rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.cc')
rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.hh')
rmtree(release_dir, 'src/oldmem')
rmtree(release_dir, 'configs/fullsys')
rmtree(release_dir, 'configs/test')
rmtree(release_dir, 'configs/splash2')
rmtree(release_dir, 'tests/long/*/ref')
rmtree(release_dir, 'tests/old')
# get rid of some of private scripts
remove(release_dir, 'util/chgcopyright')
remove(release_dir, 'util/make_release.py')
# fix up the SConscript to deal with files we've removed
mem_expr = re.compile('.*mem/cache/(tags/split|prefetch/(ghb|stride)).*')
inscript = file(joinpath(release_dir, 'src', 'SConscript'), 'r').readlines()
outscript = file(joinpath(release_dir, 'src', 'SConscript'), 'w')
for line in inscript:
if mem_expr.match(line):
continue
outscript.write(line)
outscript.close()
benches = [ 'bzip2', 'eon', 'gzip', 'mcf', 'parser', 'perlbmk',
'twolf', 'vortex' ]
for bench in benches:
rmtree(release_dir, 'tests', 'test-progs', bench)
movedir(release_dir, encumbered_dir, 'src/encumbered')
movedir(release_dir, encumbered_dir, 'tests/test-progs/anagram')
movedir(release_dir, encumbered_dir, 'tests/quick/20.eio-short')
def taritup(directory, destdir, filename):
basedir = dirname(directory)
tarball = joinpath(destdir, filename)
tardir = basename(directory)
system('cd %s; tar cfj %s %s' % (basedir, tarball, tardir))
taritup(release_dir, destdir, '%s.tar.bz2' % releasename)
taritup(encumbered_dir, destdir, '%s-encumbered.tar.bz2' % releasename)
print "release created in %s" % destdir
print "don't forget to tag the repository! The following command will do it:"
print "bk tag %s" % releasename