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Fixups towards compiling.

Browse source 
arch/alpha/types.hh:
    Moved the DependenceTags enum from types to constants.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
    Corrected a misspelling of PriviledgeOpcode and PrivilegedAction.
arch/sparc/isa/formats.isa:
    Fixups towards compiling. Added a few additional instruction formats.

--HG--
extra : convert_revision : 4c5506877b71b8a5c8c45db41192cf759cdac374
This commit is contained in:
Gabe Black 2006-03-16 13:58:50 -05:00
parent 67a1b7a61b
commit 558cc7f775
16 changed files with 1010 additions and 747 deletions
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13
arch/alpha/types.hh
View file

@ -38,19 +38,6 @@ namespace AlphaISA
typedef uint64_t ExtMachInst; typedef uint64_t ExtMachInst;
typedef uint8_t RegIndex; typedef uint8_t RegIndex;
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 40,
Ctrl_Base_DepTag = 72,
Fpcr_DepTag = 72, // floating point control register
Uniq_DepTag = 73,
Lock_Flag_DepTag = 74,
Lock_Addr_DepTag = 75,
IPR_Base_DepTag = 76
};
typedef uint64_t IntReg; typedef uint64_t IntReg;
// floating point register file entry type // floating point register file entry type

16
arch/sparc/faults.cc
View file

@ -89,10 +89,10 @@ TrapType IllegalInstruction::_trapType = 0x010;
FaultPriority IllegalInstruction::_priority = 7; FaultPriority IllegalInstruction::_priority = 7;
FaultStat IllegalInstruction::_count; FaultStat IllegalInstruction::_count;
FaultName PrivelegedOpcode::_name = "priv_opcode"; FaultName PrivilegedOpcode::_name = "priv_opcode";
TrapType PrivelegedOpcode::_trapType = 0x011; TrapType PrivilegedOpcode::_trapType = 0x011;
FaultPriority PrivelegedOpcode::_priority = 6; FaultPriority PrivilegedOpcode::_priority = 6;
FaultStat PrivelegedOpcode::_count; FaultStat PrivilegedOpcode::_count;
FaultName UnimplementedLDD::_name = "unimp_ldd"; FaultName UnimplementedLDD::_name = "unimp_ldd";
TrapType UnimplementedLDD::_trapType = 0x012; TrapType UnimplementedLDD::_trapType = 0x012;
@ -159,10 +159,10 @@ TrapType STDFMemAddressNotAligned::_trapType = 0x036;
FaultPriority STDFMemAddressNotAligned::_priority = 10; FaultPriority STDFMemAddressNotAligned::_priority = 10;
FaultStat STDFMemAddressNotAligned::_count; FaultStat STDFMemAddressNotAligned::_count;
FaultName PrivelegedAction::_name = "priv_action"; FaultName PrivilegedAction::_name = "priv_action";
TrapType PrivelegedAction::_trapType = 0x037; TrapType PrivilegedAction::_trapType = 0x037;
FaultPriority PrivelegedAction::_priority = 11; FaultPriority PrivilegedAction::_priority = 11;
FaultStat PrivelegedAction::_count; FaultStat PrivilegedAction::_count;
FaultName LDQFMemAddressNotAligned::_name = "unalign_ldqf"; FaultName LDQFMemAddressNotAligned::_name = "unalign_ldqf";
TrapType LDQFMemAddressNotAligned::_trapType = 0x038; TrapType LDQFMemAddressNotAligned::_trapType = 0x038;

4
arch/sparc/faults.hh
View file

@ -216,7 +216,7 @@ class IllegalInstruction : public SparcFault
FaultStat & countStat() {return _count;} FaultStat & countStat() {return _count;}
}; };
class PrivelegedOpcode : public SparcFault class PrivilegedOpcode : public SparcFault
{ {
private: private:
static FaultName _name; static FaultName _name;
@ -412,7 +412,7 @@ class STDFMemAddressNotAligned : public SparcFault
FaultStat & countStat() {return _count;} FaultStat & countStat() {return _count;}
}; };
class PrivelegedAction : public SparcFault class PrivilegedAction : public SparcFault
{ {
private: private:
static FaultName _name; static FaultName _name;

15
arch/sparc/isa/base.isa
View file

@ -48,6 +48,8 @@ output header {{
std::string generateDisassembly(Addr pc, std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const; const SymbolTable *symtab) const;
void printReg(std::ostream &os, int reg) const;
}; };
bool passesCondition(condCodes codes, condTest condition); bool passesCondition(condCodes codes, condTest condition);
@ -55,6 +57,17 @@ output header {{
output decoder {{ output decoder {{
void
SparcStaticInst::printReg(std::ostream &os, int reg) const
{
if (reg < FP_Base_DepTag) {
ccprintf(os, "r%d", reg);
}
else {
ccprintf(os, "f%d", reg - FP_Base_DepTag);
}
}
std::string SparcStaticInst::generateDisassembly(Addr pc, std::string SparcStaticInst::generateDisassembly(Addr pc,
const SymbolTable *symtab) const const SymbolTable *symtab) const
{ {
@ -124,6 +137,8 @@ output decoder {{
case OverflowSet: case OverflowSet:
return codes.v; return codes.v;
} }
panic("Tried testing condition nonexistant "
"condition code %d", condition);
} }
}}; }};

324
arch/sparc/isa/decoder.isa
View file

@ -3,10 +3,12 @@
// The actual decoder specification // The actual decoder specification
// //
decode OP default Trap::unknown({{IllegalInstruction}}) { decode OP default Unknown::unknown()
{
0x0: decode OP2 { 0x0: decode OP2
//0x0: Trap::illtrap({{IllegalInstruction}}); //ILLTRAP {
//Throw an illegal instruction acception
0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
0x1: Branch::bpcc({{ 0x1: Branch::bpcc({{
switch((CC12 << 1) | CC02) switch((CC12 << 1) | CC02)
{ {
@ -14,21 +16,21 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
case 3: case 3:
fault = new IllegalInstruction; fault = new IllegalInstruction;
case 0: case 0:
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2)) if(passesCondition(CcrIcc, COND2))
;//branchHere ;//branchHere
break; break;
case 2: case 2:
if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND2)) if(passesCondition(CcrXcc, COND2))
;//branchHere ;//branchHere
break; break;
} }
}});//BPcc }});//BPcc
0x2: Branch::bicc({{ 0x2: Branch::bicc({{
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2)) if(passesCondition(CcrIcc, COND2))
;//branchHere ;//branchHere
}});//Bicc }});//Bicc
0x3: Branch::bpr({{ 0x3: Branch::bpr({{
switch(RCOND) switch(RCOND2)
{ {
case 0: case 0:
case 4: case 4:
@ -61,8 +63,8 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
}}); //BPr }}); //BPr
//SETHI (or NOP if rd == 0 and imm == 0) //SETHI (or NOP if rd == 0 and imm == 0)
0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}}); 0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
0x6: Trap::fbfcc({{throw fp_disabled;}}); //FBfcc 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
} }
0x1: Branch::call({{ 0x1: Branch::call({{
//branch here //branch here
@ -104,7 +106,7 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
}});//XNOR }});//XNOR
0x08: addc({{ 0x08: addc({{
int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; int64_t carryin = CcrIccC;
Rd = Rs1.sdw + val2 + carryin; Rd = Rs1.sdw + val2 + carryin;
}});//ADDC }});//ADDC
0x09: mulx({{ 0x09: mulx({{
@ -114,28 +116,28 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
0x0A: umul({{ 0x0A: umul({{
uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw); uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
xc->regs.MiscRegs.yFields.value = resTemp<63:32>; YValue = resTemp<63:32>;
}});//UMUL }});//UMUL
0x0B: smul({{ 0x0B: smul({{
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw); int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>; rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
xc->regs.MiscRegs.yFields.value = resTemp<63:32>; YValue = resTemp<63:32>;
}});//SMUL }});//SMUL
0x0C: subc({{ 0x0C: subc({{
int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1; int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1;
int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; int64_t carryin = CcrIccC;
Rd.sdw = Rs1.sdw + val2 + carryin; Rd.sdw = Rs1.sdw + val2 + carryin;
}});//SUBC }});//SUBC
0x0D: udivx({{ 0x0D: udivx({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
if(val2 == 0) throw division_by_zero; if(val2 == 0) fault = new DivisionByZero;
Rd.udw = Rs1.udw / val2; else Rd.udw = Rs1.udw / val2;
}});//UDIVX }});//UDIVX
0x0E: udiv({{ 0x0E: udiv({{
uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>); uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
if(val2 == 0) if(val2 == 0)
fault = new DivisionByZero; fault = new DivisionByZero;
resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32) resTemp = (uint64_t)((YValue << 32)
| Rs1.udw<31:0>) / val2; | Rs1.udw<31:0>) / val2;
int32_t overflow = (resTemp<63:32> != 0); int32_t overflow = (resTemp<63:32> != 0);
if(overflow) if(overflow)
@ -148,7 +150,7 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
if(val2 == 0) if(val2 == 0)
fault = new DivisionByZero; fault = new DivisionByZero;
Rd.sdw = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rd.sdw = (int64_t)((YValue << 32) |
Rs1.sdw<31:0>) / val2; Rs1.sdw<31:0>) / val2;
resTemp = Rd.sdw; resTemp = Rd.sdw;
int32_t overflow = (resTemp<63:31> != 0); int32_t overflow = (resTemp<63:31> != 0);
@ -206,7 +208,7 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
{{0}},{{0}},{{0}},{{0}});//XNORcc {{0}},{{0}},{{0}},{{0}});//XNORcc
0x18: addccc({{ 0x18: addccc({{
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; int64_t carryin = CcrIccC;
Rd = resTemp = Rs1 + val2 + carryin;}}, Rd = resTemp = Rs1 + val2 + carryin;}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
+ carryin)}}, + carryin)}},
@ -218,16 +220,16 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
0x1A: umulcc({{ 0x1A: umulcc({{
uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}, YValue = resTemp<63:32>;}},
{{0}},{{0}},{{0}},{{0}});//UMULcc {{0}},{{0}},{{0}},{{0}});//UMULcc
0x1B: smulcc({{ 0x1B: smulcc({{
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>; Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}} YValue = resTemp<63:32>;}}
,{{0}},{{0}},{{0}},{{0}});//SMULcc ,{{0}},{{0}},{{0}},{{0}});//SMULcc
0x1C: subccc({{ 0x1C: subccc({{
int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2); int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; int64_t carryin = CcrIccC;
Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
{{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}}, {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
@ -236,16 +238,19 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
);//SUBCcc );//SUBCcc
0x1D: udivxcc({{ 0x1D: udivxcc({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw); uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
if(val2 == 0) throw division_by_zero; if(val2 == 0) fault = new DivisionByZero;
Rd.udw = Rs1.udw / val2;}} else Rd.udw = Rs1.udw / val2;}}
,{{0}},{{0}},{{0}},{{0}});//UDIVXcc ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
0x1E: udivcc({{ 0x1E: udivcc({{
uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>); uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
if(val2 == 0) throw division_by_zero; if(val2 == 0) fault = new DivisionByZero;
resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2; else
{
resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2;
int32_t overflow = (resTemp<63:32> != 0); int32_t overflow = (resTemp<63:32> != 0);
if(overflow) rd.udw = resTemp = 0xFFFFFFFF; if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
else rd.udw = resTemp;}}, else rd.udw = resTemp;
} }},
{{0}}, {{0}},
{{overflow}}, {{overflow}},
{{0}}, {{0}},
@ -253,13 +258,16 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
);//UDIVcc );//UDIVcc
0x1F: sdivcc({{ 0x1F: sdivcc({{
int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>); int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
if(val2 == 0) throw division_by_zero; if(val2 == 0) fault = new DivisionByZero;
Rd.sdw = resTemp = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2; else
{
Rd.sdw = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2;
int32_t overflow = (resTemp<63:31> != 0); int32_t overflow = (resTemp<63:31> != 0);
int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
if(overflow) rd.udw = resTemp = 0x7FFFFFFF; if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000; else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
else rd.udw = resTemp;}}, else rd.udw = resTemp;
} }},
{{0}}, {{0}},
{{overflow || underflow}}, {{overflow || underflow}},
{{0}}, {{0}},
@ -287,7 +295,7 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
Rd = resTemp = Rs1 + val2; Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
if(overflow) throw tag_overflow;}}, if(overflow) fault = new TagOverflow;}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
{{overflow}}, {{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
@ -297,7 +305,7 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2); int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
Rd = resTemp = Rs1 + val2; Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
if(overflow) throw tag_overflow;}}, if(overflow) fault = new TagOverflow;}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
{{overflow}}, {{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
@ -308,12 +316,12 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
int32_t multiplier = Rs1<31:0>; int32_t multiplier = Rs1<31:0>;
int32_t savedLSB = Rs1<0:>; int32_t savedLSB = Rs1<0:>;
multiplier = multipler<31:1> | multiplier = multipler<31:1> |
((xc->regs.MiscRegs.ccrFields.iccFields.n ((CcrIccN
^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32); ^ CcrIccV) << 32);
if(!xc->regs.MiscRegs.yFields.value<0:>) if(!YValue<0:>)
multiplicand = 0; multiplicand = 0;
Rd = resTemp = multiplicand + multiplier; Rd = resTemp = multiplicand + multiplier;
xc->regs.MiscRegs.yFields.value = xc->regs.MiscRegs.yFields.value<31:1> | (savedLSB << 31);}}, YValue = YValue<31:1> | (savedLSB << 31);}},
{{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
{{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
{{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
@ -335,40 +343,47 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
} }
0x28: decode RS1 { 0x28: decode RS1 {
0x0: rdy({{Rd = xc->regs.MiscRegs.yFields.value;}}); //RDY 0x0: rdy({{Rd = YValue;}}); //RDY
0x2: rdccr({{Rd = xc->regs.MiscRegs.ccr;}}); //RDCCR 0x2: rdccr({{Rd = Ccr;}}); //RDCCR
0x3: rdasi({{Rd = xc->regs.MiscRegs.asi;}}); //RDASI 0x3: rdasi({{Rd = Asi;}}); //RDASI
0x4: rdtick({{ 0x4: PrivTick::rdtick({{Rd = Tick;}});
if(xc->regs.MiscRegs.pstateFields.priv == 0 &&
xc->regs.MiscRegs.tickFields.npt == 1)
throw privileged_action;
Rd = xc->regs.MiscRegs.tick;
}});//RDTICK
0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC 0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
0x6: rdfprs({{Rd = xc->regs.MiscRegs.fprs;}}); //RDFPRS 0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS
0xF: decode I { 0xF: decode I {
0x0: Noop::membar({{//Membar isn't needed yet}}); //MEMBAR 0x0: Noop::membar({{//Membar isn't needed yet}});
0x1: Noop::stbar({{//Stbar isn/'t needed yet}}); //STBAR 0x1: Noop::stbar({{//Stbar isn't needed yet}});
} }
} }
0x2A: decode RS1 { 0x2A: decode RS1 {
0x0: rdprtpc({{checkPriv Rd = xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl];}}); format Priv
0x1: rdprtnpc({{checkPriv Rd = xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl];}}); {
0x2: rdprtstate({{checkPriv Rd = xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl];}}); 0x0: rdprtpc({{
0x3: rdprtt({{checkPriv Rd = xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl];}}); Rd = xc->readMiscReg(MISCREG_TPC_BASE + tl);
0x4: rdprtick({{checkPriv Rd = xc->regs.MiscRegs.tick;}}); }});
0x5: rdprtba({{checkPriv Rd = xc->regs.MiscRegs.tba;}}); 0x1: rdprtnpc({{
0x6: rdprpstate({{checkPriv Rd = xc->regs.MiscRegs.pstate;}}); Rd = xc->readMiscReg(MISCREG_TNPC_BASE + tl);
0x7: rdprtl({{checkPriv Rd = xc->regs.MiscRegs.tl;}}); }});
0x8: rdprpil({{checkPriv Rd = xc->regs.MiscRegs.pil;}}); 0x2: rdprtstate({{
0x9: rdprcwp({{checkPriv Rd = xc->regs.MiscRegs.cwp;}}); Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + tl);
0xA: rdprcansave({{checkPriv Rd = xc->regs.MiscRegs.cansave;}}); }});
0xB: rdprcanrestore({{checkPriv Rd = xc->regs.MiscRegs.canrestore;}}); 0x3: rdprtt({{
0xC: rdprcleanwin({{checkPriv Rd = xc->regs.MiscRegs.cleanwin;}}); Rd = xc->readMiscReg(MISCREG_TT_BASE + tl);
0xD: rdprotherwin({{checkPriv Rd = xc->regs.MiscRegs.otherwin;}}); }});
0xE: rdprwstate({{checkPriv Rd = xc->regs.MiscRegs.wstate;}}); 0x4: rdprtick({{Rd = Tick;}});
0xF: rdprfq({{throw illegal_instruction;}}); //The floating point queue isn't implemented right now. 0x5: rdprtba({{Rd = Tba;}});
0x6: rdprpstate({{Rd = Pstate;}});
0x7: rdprtl({{Rd = Tl;}});
0x8: rdprpil({{Rd = Pil;}});
0x9: rdprcwp({{Rd = Cwp;}});
0xA: rdprcansave({{Rd = Cansave;}});
0xB: rdprcanrestore({{Rd = CanRestore;}});
0xC: rdprcleanwin({{Rd = Cleanwin;}});
0xD: rdprotherwin({{Rd = Otherwin;}});
0xE: rdprwstate({{Rd = Wstate;}});
}
//The floating point queue isn't implemented right now.
0xF: Trap::rdprfq({{fault = IllegalInstruction;}});
0x1F: Priv::rdprver({{Rd = Ver;}});
} }
0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW 0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
0x2C: movcc({{ 0x2C: movcc({{
@ -376,25 +391,25 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
switch(ccBank) switch(ccBank)
{ {
case 0: case 1: case 2: case 3: case 0: case 1: case 2: case 3:
throw fp_disabled; fault = new FpDisabled;
break; break;
case 5: case 7: case 5: case 7:
throw illegal_instruction; fault = new IllegalInstruction;
break; break;
case 4: case 4:
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND4)) if(passesCondition(CcrIcc, COND4))
Rd = (I ? SIMM11.sdw : RS2); Rd = (I ? SIMM11.sdw : RS2);
break; break;
case 6: case 6:
if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND4)) if(passesCondition(CcrXcc, COND4))
Rd = (I ? SIMM11.sdw : RS2); Rd = (I ? SIMM11.sdw : RS2);
break; break;
} }
}});//MOVcc }});//MOVcc
0x2D: sdivx({{ 0x2D: sdivx({{
int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
if(val2 == 0) throw division_by_zero; if(val2 == 0) fault = new DivisionByZero;
Rd.sdw = Rs1.sdw / val2; else Rd.sdw = Rs1.sdw / val2;
}});//SDIVX }});//SDIVX
0x2E: decode RS1 { 0x2E: decode RS1 {
0x0: IntegerOp::popc({{ 0x0: IntegerOp::popc({{
@ -409,10 +424,10 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
} }
0x2F: movr({{ 0x2F: movr({{
uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw); uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw);
switch(RCOND) switch(RCOND3)
{ {
case 0: case 4: case 0: case 4:
throw illegal_instruction; fault = IllegalInstruction;
break; break;
case 1: case 1:
if(Rs1 == 0) Rd = val2; if(Rs1 == 0) Rd = val2;
@ -437,110 +452,80 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
0x30: decode RD { 0x30: decode RD {
0x0: wry({{ 0x0: wry({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.y = Rs1 ^ val2; Y = Rs1 ^ val2;
}});//WRY }});//WRY
0x2: wrccr({{ 0x2: wrccr({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.ccr = Rs1 ^ val2; Ccr = Rs1 ^ val2;
}});//WRCCR }});//WRCCR
0x3: wrasi({{ 0x3: wrasi({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.asi = Rs1 ^ val2; Asi = Rs1 ^ val2;
}});//WRASI }});//WRASI
0x6: wrfprs({{ 0x6: wrfprs({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.asi = Rs1 ^ val2; Asi = Rs1 ^ val2;
}});//WRFPRS }});//WRFPRS
0xF: Trap::sir({{software_initiated_reset}}); //SIR 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
} }
0x31: decode FCN { 0x31: decode FCN {
0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED 0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED
0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED 0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED
} }
0x32: decode RD { 0x32: decode RD {
0x0: wrprtpc({{checkPriv format Priv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); {
xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2; 0x0: wrprtpc({{
xc->setMiscReg(MISCREG_TPC_BASE + tl,
Rs1 ^ Rs2_or_imm13);
}}); }});
0x1: wrprtnpc({{checkPriv 0x1: wrprtnpc({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); xc->setMiscReg(MISCREG_TNPC_BASE + tl,
xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2; Rs1 ^ Rs2_or_imm13);
}}); }});
0x2: wrprtstate({{checkPriv 0x2: wrprtstate({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); xc->setMiscReg(MISCREG_TSTATE_BASE + tl,
xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2; Rs1 ^ Rs2_or_imm13);
}}); }});
0x3: wrprtt({{checkPriv 0x3: wrprtt({{
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw); xc->setMiscReg(MISCREG_TT_BASE + tl,
xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2; Rs1 ^ Rs2_or_imm13);
}});
0x4: wrprtick({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.tick = Rs1 ^ val2;
}});
0x5: wrprtba({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.tba = Rs1 ^ val2;
}});
0x6: wrprpstate({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.pstate = Rs1 ^ val2;
}});
0x7: wrprtl({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.tl = Rs1 ^ val2;
}});
0x8: wrprpil({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.pil = Rs1 ^ val2;
}});
0x9: wrprcwp({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.cwp = Rs1 ^ val2;
}});
0xA: wrprcansave({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.cansave = Rs1 ^ val2;
}});
0xB: wrprcanrestore({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.canrestore = Rs1 ^ val2;
}});
0xC: wrprcleanwin({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.cleanwin = Rs1 ^ val2;
}});
0xD: wrprotherwin({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.otherwin = Rs1 ^ val2;
}});
0xE: wrprwstate({{checkPriv
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
xc->regs.MiscRegs.wstate = Rs1 ^ val2;
}}); }});
0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}});
0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
}
} }
0x34: Trap::fpop1({{Throw fp_disabled;}}); //FPOP1 0x34: Trap::fpop1({{fault = new FpDisabled;}});
0x35: Trap::fpop2({{Throw fp_disabled;}}); //FPOP2 0x35: Trap::fpop2({{fault = new FpDisabled;}});
0x38: Branch::jmpl({{//Stuff}}); //JMPL 0x38: Branch::jmpl({{//Stuff}}); //JMPL
0x39: Branch::return({{//Other Stuff}}); //RETURN 0x39: Branch::return({{//Other Stuff}}); //RETURN
0x3A: Trap::tcc({{ 0x3A: decode CC04
switch((CC14 << 1) | (CC04 << 0))
{ {
case 1: case 3: // If CC04 == 1, it's an illegal instruction
throw illegal_instruction; 0x0: decode CC14
case 0: {
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>)) 0x0: Trap::tcci({{
throw trap_instruction; if(passesCondition(ccr_icc, machInst<25:28>))
break; fault = new TrapInstruction;
case 2: }});
if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>)) 0x1: Trap::tccx({{
throw trap_instruction; if(passesCondition(ccr_xcc, machInst<25:28>))
break; fault = new TrapInstruction;
}});
}
} }
}}); //Tcc
0x3B: BasicOperate::flush({{//Lala}}); //FLUSH 0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
0x3C: BasicOperate::save({{//leprechauns); //SAVE 0x3C: BasicOperate::save({{//leprechauns); //SAVE
0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE 0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
@ -610,39 +595,30 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
Rd.uw = Mem.uw; Rd.uw = Mem.uw;
Mem.uw = temp; Mem.uw = temp;
}}); //SWAPA }}); //SWAPA
0x20: Trap::ldf({{throw fp_disabled;}}); //LDF 0x20: Trap::ldf({{fault = new FpDisabled;}});
0x21: decode X { 0x21: decode X {
0x0: Trap::ldfsr({{throw fp_disabled;}}); //LDFSR 0x0: Trap::ldfsr({{fault = new FpDisabled;}});
0x1: Trap::ldxfsr({{throw fp_disabled;}}); //LDXFSR 0x1: Trap::ldxfsr({{fault = new FpDisabled;}});
} }
0x22: Trap::ldqf({{throw fp_disabled;}}); //LDQF 0x22: Trap::ldqf({{fault = new FpDisabled;}});
0x23: Trap::lddf({{throw fp_disabled;}}); //LDDF 0x23: Trap::lddf({{fault = new FpDisabled;}});
0x24: Trap::stf({{throw fp_disabled;}}); //STF 0x24: Trap::stf({{fault = new FpDisabled;}});
0x25: decode X { 0x25: decode X {
0x0: Trap::stfsr({{throw fp_disabled;}}); //STFSR 0x0: Trap::stfsr({{fault = new FpDisabled;}});
0x1: Trap::stxfsr({{throw fp_disabled;}}); //STXFSR 0x1: Trap::stxfsr({{fault = new FpDisabled;}});
} }
0x26: Trap::stqf({{throw fp_disabled;}}); //STQF 0x26: Trap::stqf({{fault = new FpDisabled;}});
0x27: Trap::stdf({{throw fp_disabled;}}); //STDF 0x27: Trap::stdf({{fault = new FpDisabled;}});
0x2D: Noop::prefetch({{ }}); //PREFETCH 0x2D: Noop::prefetch({{ }}); //PREFETCH
0x30: Trap::ldfa({{return new FpDisabled;}});
0x30: Trap::ldfa({{throw fp_disabled;}}); //LDFA 0x32: Trap::ldqfa({{fault = new FpDisabled;}});
0x33: Trap::lddfa({{fault = new FpDisabled;}});
0x32: Trap::ldqfa({{throw fp_disabled;}}); //LDQFA 0x34: Trap::stfa({{fault = new FpDisabled;}});
0x33: Trap::lddfa({{throw fp_disabled;}}); //LDDFA 0x35: Trap::stqfa({{fault = new FpDisabled;}});
0x34: Trap::stfa({{throw fp_disabled;}}); //STFA 0x36: Trap::stdfa({{fault = new FpDisabled;}});
0x35: Trap::stqfa({{throw fp_disabled;}}); //STQFA
0x36: Trap::stdfa({{throw fp_disabled;}}); //STDFA
0x3C: Cas::casa( 0x3C: Cas::casa(
{{uint64_t val = Mem.uw; {{uint64_t val = Mem.uw;

11
arch/sparc/isa/formats.isa
View file

@ -5,12 +5,21 @@
//Include the integerOp and integerOpCc format //Include the integerOp and integerOpCc format
##include "m5/arch/sparc/isa/formats/integerop.isa" ##include "m5/arch/sparc/isa/formats/integerop.isa"
//Include the mem format //Include the memory format
##include "m5/arch/sparc/isa/formats/mem.isa" ##include "m5/arch/sparc/isa/formats/mem.isa"
//Include the compare and swap format
##include "m5/arch/sparc/isa/formats/cas.isa"
//Include the trap format //Include the trap format
##include "m5/arch/sparc/isa/formats/trap.isa" ##include "m5/arch/sparc/isa/formats/trap.isa"
//Include the "unknown" format
##include "m5/arch/sparc/isa/formats/unknown.isa"
//Include the priveleged mode format
##include "m5/arch/sparc/isa/formats/priv.isa"
//Include the branch format //Include the branch format
##include "m5/arch/sparc/isa/formats/branch.isa" ##include "m5/arch/sparc/isa/formats/branch.isa"

3
arch/sparc/isa/formats/branch.isa
View file

@ -34,7 +34,6 @@ def template BranchExecute {{
{ {
//Attempt to execute the instruction //Attempt to execute the instruction
Fault fault = NoFault; Fault fault = NoFault;
checkPriv;
%(op_decl)s; %(op_decl)s;
%(op_rd)s; %(op_rd)s;
@ -57,6 +56,6 @@ def format Branch(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop) header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop) decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop) decode_block = BasicDecode.subst(iop)
exec_output = BranchExecute.subst(iop) exec_output = BranchExecute.subst(iop)
}}; }};

57
arch/sparc/isa/formats/integerop.isa
View file

@ -11,7 +11,7 @@ output header {{
{ {
protected: protected:
// Constructor // Constructor
IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : IntegerOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass) SparcStaticInst(mnem, _machInst, __opClass)
{ {
} }
@ -30,44 +30,35 @@ output decoder {{
}}; }};
def template IntegerExecute {{ def template IntegerExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{ {
Fault fault;
//These are set to constants when the execute method //These are set to constants when the execute method
//is generated //is generated
bool useCc = ; bool useCc = ;
bool checkPriv = ;
//Attempt to execute the instruction
try
{
checkPriv;
%(op_decl)s; %(op_decl)s;
%(op_rd)s; %(op_rd)s;
%(code)s; %(code)s;
}
//If we have an exception for some reason,
//deal with it
catch(SparcException except)
{
//Deal with exception
return No_Fault;
}
//Write the resulting state to the execution context //Write the resulting state to the execution context
if(fault == NoFault)
{
%(op_wb)s; %(op_wb)s;
if(useCc) if(useCc)
{ {
xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63); CcrIccN = Rd & (1 << 63);
xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0); CcrIccZ = (Rd == 0);
xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue; CcrIccV = ivValue;
xc->regs.miscRegFile.ccrFields.iccFields.c = icValue; CcrIccC = icValue;
xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31); CcrXccN = Rd & (1 << 31);
xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0); CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue; CcrXccV = xvValue;
xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue; CcrXccC = xcValue;
} }
return No_Fault; }
return fault;
} }
}}; }};
@ -75,19 +66,13 @@ def template IntegerExecute {{
def format IntegerOp(code, *opt_flags) {{ def format IntegerOp(code, *opt_flags) {{
orig_code = code orig_code = code
cblk = CodeBlock(code) cblk = CodeBlock(code)
checkPriv = (code.find('checkPriv') != -1)
code.replace('checkPriv', '')
if checkPriv:
code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
else:
code.replace('checkPriv;', '')
for (marker, value) in (('ivValue', '0'), ('icValue', '0'), for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
('xvValue', '0'), ('xcValue', '0')): ('xvValue', '0'), ('xcValue', '0')):
code.replace(marker, value) code.replace(marker, value)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop) header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop) decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop) decode_block = BasicDecode.subst(iop)
exec_output = IntegerExecute.subst(iop) exec_output = IntegerExecute.subst(iop)
}}; }};
@ -95,18 +80,12 @@ def format IntegerOp(code, *opt_flags) {{
def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
orig_code = code orig_code = code
cblk = CodeBlock(code) cblk = CodeBlock(code)
checkPriv = (code.find('checkPriv') != -1)
code.replace('checkPriv', '')
if checkPriv:
code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
else:
code.replace('checkPriv;', '')
for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
('xvValue', xvValue), ('xcValue', xcValue)): ('xvValue', xvValue), ('xcValue', xcValue)):
code.replace(marker, value) code.replace(marker, value)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop) header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop) decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop) decode_block = BasicDecode.subst(iop)
exec_output = IntegerExecute.subst(iop) exec_output = IntegerExecute.subst(iop)
}}; }};

15
arch/sparc/isa/formats/mem.isa
View file

@ -12,7 +12,7 @@ output header {{
protected: protected:
// Constructor // Constructor
Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass) SparcStaticInst(mnem, _machInst, __opClass)
{ {
} }
@ -56,18 +56,7 @@ def format Mem(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop) header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop) decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop) decode_block = BasicDecode.subst(iop)
exec_output = MemExecute.subst(iop) exec_output = MemExecute.subst(iop)
exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;'); exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
}}; }};
def format Cas(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = MemExecute.subst(iop)
exec_output.replace('ea_code', 'EA = R1;');
}};

4
arch/sparc/isa/formats/noop.isa
View file

@ -11,7 +11,7 @@ output header {{
{ {
protected: protected:
// Constructor // Constructor
Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : Noop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass) SparcStaticInst(mnem, _machInst, __opClass)
{ {
} }
@ -45,6 +45,6 @@ def format Noop(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop) header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop) decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop) decode_block = BasicDecode.subst(iop)
exec_output = NoopExecute.subst(iop) exec_output = NoopExecute.subst(iop)
}}; }};

172
arch/sparc/isa/formats/priv.isa Normal file
View file

@ -0,0 +1,172 @@
////////////////////////////////////////////////////////////////////
//
// Privelege mode instructions
//
output header {{
/**
* Base class for privelege mode operations.
*/
class Priv : public SparcStaticInst
{
protected:
// Constructor
Priv(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
/**
* Base class for user mode "tick" access.
*/
class PrivTick : public SparcStaticInst
{
protected:
// Constructor
PrivTick(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
/**
* Base class for privelege mode operations with immediates.
*/
class PrivImm : public Priv
{
protected:
// Constructor
PrivImm(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
Priv(mnem, _machInst, __opClass), imm(SIMM13)
{
}
uint32_t imm;
};
/**
* Base class for user mode "tick" access with immediates.
*/
class PrivTickImm : public PrivTick
{
protected:
// Constructor
PrivTickImm(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
PrivTick(mnem, _machInst, __opClass), imm(SIMM13)
{
}
uint32_t imm;
};
}};
output decoder {{
std::string Priv::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Privileged Instruction";
}
std::string PrivTick::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Regular access to Tick";
}
}};
def template PrivExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
//If the processor isn't in privileged mode, fault out right away
if(!pstate_priv)
return new PrivilegedOpCode
%(code)s;
%(op_wb)s;
}
}};
def template PrivTickExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
//If the processor isn't in privileged mode, fault out right away
if(!pstate_priv && tick_npt)
return new PrivilegedAction
%(code)s;
%(op_wb)s;
}
}};
def template Rb2OrImm13Decode {{
{
return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
: (SparcStaticInst *)(new %(class_name)s(machInst)));
}
}};
// Primary format for integer operate instructions:
def format Priv(code, *opt_flags) {{
uses_imm = (code.find('Rs2_or_imm13') != -1)
if uses_imm:
orig_code = code
code = re.sub(r'Rs2_or_imm', 'Rs2', orig_code)
imm_code = re.sub(r'Rs2_or_imm(\.\w+)?', 'imm', orig_code)
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Priv', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = PrivExecute.subst(iop)
if uses_imm:
imm_cblk = CodeBlock(imm_code)
imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', imm_cblk,
opt_flags)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += PrivExecute.subst(imm_iop)
decode_block = Rb2OrImm13Decode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
}};
// Primary format for integer operate instructions:
def format PrivTick(code, *opt_flags) {{
uses_imm = (code.find('Rs2_or_imm13') != -1)
if uses_imm:
orig_code = code
code = re.sub(r'Rs2_or_imm', 'Rs2', orig_code)
imm_code = re.sub(r'Rs2_or_imm(\.\w+)?', 'imm', orig_code)
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'PrivTick', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = PrivTickExecute.subst(iop)
if uses_imm:
imm_cblk = CodeBlock(imm_code)
imm_iop = InstObjParams(name, Name + 'Imm', 'PrivTickImm', imm_cblk,
opt_flags)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += PrivTickExecute.subst(imm_iop)
decode_block = Rb2OrImm13Decode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
}};

13
arch/sparc/isa/formats/trap.isa
View file

@ -5,14 +5,15 @@
output header {{ output header {{
/** /**
* Base class for integer operations. * Base class for trap instructions,
* or instructions that always fault.
*/ */
class Trap : public SparcStaticInst class Trap : public SparcStaticInst
{ {
protected: protected:
// Constructor // Constructor
Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : Trap(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass) SparcStaticInst(mnem, _machInst, __opClass)
{ {
} }
@ -34,18 +35,18 @@ def template TrapExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
//TODO: set up a software fault and return it. Fault fault = NoFault;
return NoFault; %(code)s
return fault;
} }
}}; }};
// Primary format for integer operate instructions:
def format Trap(code, *opt_flags) {{ def format Trap(code, *opt_flags) {{
orig_code = code orig_code = code
cblk = CodeBlock(code) cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop) header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop) decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop) decode_block = BasicDecode.subst(iop)
exec_output = TrapExecute.subst(iop) exec_output = TrapExecute.subst(iop)
}}; }};

46
arch/sparc/isa/formats/unknown.isa Normal file
View file

@ -0,0 +1,46 @@
////////////////////////////////////////////////////////////////////
//
// Unknown instructions
//
output header {{
/**
* Class for Unknown/Illegal instructions
*/
class Unknown : public SparcStaticInst
{
public:
// Constructor
Unknown(ExtMachInst _machInst) :
SparcStaticInst("unknown", _machInst, No_OpClass)
{
}
%(BasicExecDeclare)s
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string Unknown::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Unknown instruction\n";
}
}};
output exec {{
Fault Unknown::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
return new IllegalInstruction;
}
}};
def format Unknown() {{
decode_block = 'return new Unknown(machInst);\n'
}};

2
arch/sparc/isa/includes.isa
View file

@ -39,5 +39,7 @@ output exec {{
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/exetrace.hh" #include "cpu/exetrace.hh"
#include "sim/sim_exit.hh" #include "sim/sim_exit.hh"
using namespace SparcISA;
}}; }};

81
arch/sparc/isa/operands.isa
View file

@ -27,5 +27,84 @@ def operands {{
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
'R0': ('IntReg', 'udw', '0', None, 1), 'R0': ('IntReg', 'udw', '0', None, 1),
'R16': ('IntReg', 'udw', '16', None, 1) 'R16': ('IntReg', 'udw', '16', None, 1),
# Control registers
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
'PstateIe': ('ControlReg', 'udw', 'MISCREG_PSTATE_IE', None, 3),
'PstatePriv': ('ControlReg', 'udw', 'MISCREG_PSTATE_PRIV', None, 4),
'PstateAm': ('ControlReg', 'udw', 'MISCREG_PSTATE_AM', None, 5),
'PstatePef': ('ControlReg', 'udw', 'MISCREG_PSTATE_PEF', None, 6),
'PstateRed': ('ControlReg', 'udw', 'MISCREG_PSTATE_RED', None, 7),
'PstateMm': ('ControlReg', 'udw', 'MISCREG_PSTATE_MM', None, 8),
'PstateTle': ('ControlReg', 'udw', 'MISCREG_PSTATE_TLE', None, 9),
'PstateCle': ('ControlReg', 'udw', 'MISCREG_PSTATE_CLE', None, 10),
'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 11),
'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 12),
'YValue': ('ControlReg', 'udw', 'MISCREG_Y_VALUE', None, 13),
'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 14),
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
#'Tt': ('ControlReg', 'udw', 'MISCREG_TT_BASE + tl', None, 16),
'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 17),
'CcrIcc': ('ControlReg', 'udw', 'MISCREG_CCR_ICC', None, 18),
'CcrIccC': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_C', None, 19),
'CcrIccV': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_V', None, 20),
'CcrIccZ': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_Z', None, 21),
'CcrIccN': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_N', None, 22),
'CcrXcc': ('ControlReg', 'udw', 'MISCREG_CCR_XCC', None, 23),
'CcrXccC': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22),
'CcrXccV': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23),
'CcrXccZ': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24),
'CcrXccN': ('ControlReg', 'udw', 'MISCREG_XCC_N', None, 25),
'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27),
#'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 29),
'TickCounter': ('ControlReg', 'udw', 'MISCREG_TICK_COUNTER', None, 32),
'TickNpt': ('ControlReg', 'udw', 'MISCREG_TICK_NPT', None, 33),
'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34),
'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35),
'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37),
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38),
'WstateNormal': ('ControlReg', 'udw', 'MISCREG_WSTATE_NORMAL', None,39),
'WstateOther': ('ControlReg', 'udw', 'MISCREG_WSTATE_OTHER', None, 40),
'Ver': ('ControlReg', 'udw', 'MISCREG_VER', None, 41),
'VerMaxwin': ('ControlReg', 'udw', 'MISCREG_VER_MAXWIN', None, 42),
'VerMaxtl': ('ControlReg', 'udw', 'MISCREG_VER_MAXTL', None, 43),
'VerMask': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 44),
'VerImpl': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 45),
'VerManuf': ('ControlReg', 'udw', 'MISCREG_VER_MANUF', None, 46),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 47),
'FsrCexc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC', None, 48),
'FsrCexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NXC', None, 49),
'FsrCexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_DZC', None, 50),
'FsrCexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_UFC', None, 51),
'FsrCexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_OFC', None, 52),
'FsrCexcNvc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NVC', None, 53),
'FsrAexc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC', None, 54),
'FsrAexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_NXC', None, 55),
'FsrAexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_DZC', None, 56),
'FsrAexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_UFC', None, 57),
'FsrAexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_OFC', None, 58),
'FsrAexcNvc': ('ControlReg', 'udw', 'MISCREC_FSR_AEXC_NVC', None, 59),
'FsrFcc0': ('ControlReg', 'udw', 'MISCREG_FSR_FCC0', None, 60),
'FsrQne': ('ControlReg', 'udw', 'MISCREG_FSR_QNE', None, 61),
'FsrFtt': ('ControlReg', 'udw', 'MISCREG_FSR_FTT', None, 62),
'FsrVer': ('ControlReg', 'udw', 'MISCREG_FSR_VER', None, 63),
'FsrNs': ('ControlReg', 'udw', 'MISCREG_FSR_NS', None, 64),
'FsrTem': ('ControlReg', 'udw', 'MISCREG_FSR_TEM', None, 65),
'FsrTemNxm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NXM', None, 66),
'FsrTemDzm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_DZM', None, 67),
'FsrTemUfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_UFM', None, 68),
'FsrTemOfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_OFM', None, 69),
'FsrTemNvm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NVM', None, 70),
'FsrRd': ('ControlReg', 'udw', 'MISCREG_FSR_RD', None, 71),
'FsrFcc1': ('ControlReg', 'udw', 'MISCREG_FSR_FCC1', None, 72),
'FsrFcc2': ('ControlReg', 'udw', 'MISCREG_FSR_FCC2', None, 73),
'FsrFcc3': ('ControlReg', 'udw', 'MISCREG_FSR_FCC3', None, 74),
'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 75),
'FprsDl': ('ControlReg', 'udw', 'MISCREG_FPRS_DL', None, 76),
'FprsDu': ('ControlReg', 'udw', 'MISCREG_FPRS_DU', None, 77),
'FprsFef': ('ControlReg', 'udw', 'MISCREG_FPRS_FEF', None, 78)
}}; }};

11
arch/sparc/isa_traits.hh
View file

@ -83,6 +83,15 @@ class SyscallReturn
namespace SparcISA namespace SparcISA
{ {
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 32,
Ctrl_Base_DepTag = 96,
};
//This makes sure the big endian versions of certain functions are used. //This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest; using namespace BigEndianGuest;
@ -140,7 +149,7 @@ namespace SparcISA
void unserialize(Checkpoint *cp, const std::string &section); void unserialize(Checkpoint *cp, const std::string &section);
StaticInstPtr decodeInst(MachInst); StaticInstPtr decodeInst(ExtMachInst);
// return a no-op instruction... used for instruction fetch faults // return a no-op instruction... used for instruction fetch faults
extern const MachInst NoopMachInst; extern const MachInst NoopMachInst;