diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index e0e4d9a15..dbee7f46c 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -90,9 +90,8 @@ InOrderCPU::TickEvent::description()
 
 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
                                Fault fault, ThreadID _tid, DynInstPtr inst,
-                               unsigned event_pri_offset)
-    : Event(Event::Priority((unsigned int)CPU_Tick_Pri + event_pri_offset)),
-      cpu(_cpu)
+                               CPUEventPri event_pri)
+    : Event(event_pri), cpu(_cpu)
 {
     setEvent(e_type, fault, _tid, inst);
 }
@@ -836,10 +835,10 @@ InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
 void
 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
                              ThreadID tid, DynInstPtr inst, 
-                             unsigned delay, unsigned event_pri_offset)
+                             unsigned delay, CPUEventPri event_pri)
 {
     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
-                                       event_pri_offset);
+                                       event_pri);
 
     Tick sked_tick = nextCycle(curTick() + ticks(delay));
     if (delay >= 0) {
@@ -1064,7 +1063,7 @@ InOrderCPU::activateNextReadyContext(int delay)
     // threads after we've finished deactivating, squashing,etc.
     // other threads
     scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0], 
-                     delay, 5);
+                     delay, ActivateNextReadyThread_Pri);
 
     // Be sure to signal that there's some activity so the CPU doesn't
     // deschedule itself.
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index f60258c96..051a790db 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -190,6 +190,11 @@ class InOrderCPU : public BaseCPU
 
     static std::string eventNames[NumCPUEvents];
 
+    enum CPUEventPri {
+        InOrderCPU_Pri                 = Event::CPU_Tick_Pri,
+        ActivateNextReadyThread_Pri    = Event::CPU_Tick_Pri + 10
+    };
+
     /** Define CPU Event */
     class CPUEvent : public Event
     {
@@ -206,7 +211,7 @@ class InOrderCPU : public BaseCPU
       public:
         /** Constructs a CPU event. */
         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
-                 ThreadID _tid, DynInstPtr inst, unsigned event_pri_offset);
+                 ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
 
         /** Set Type of Event To Be Scheduled */
         void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
@@ -235,7 +240,7 @@ class InOrderCPU : public BaseCPU
     /** Schedule a CPU Event */
     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
                           DynInstPtr inst, unsigned delay = 0,
-                          unsigned event_pri_offset = 0);
+                          CPUEventPri event_pri = InOrderCPU_Pri);
 
   public:
     /** Interface between the CPU and CPU resources. */
diff --git a/src/cpu/inorder/resource_pool.cc b/src/cpu/inorder/resource_pool.cc
index d5b3a5115..0713783b3 100644
--- a/src/cpu/inorder/resource_pool.cc
+++ b/src/cpu/inorder/resource_pool.cc
@@ -508,7 +508,7 @@ ResourcePool::ResPoolEvent::ResPoolEvent(ResourcePool *_resPool,
                                          int stage_num,
                                          InstSeqNum seq_num,
                                          ThreadID _tid)
-    : Event(CPU_Tick_Pri), resPool(_resPool),
+    : Event(ResPool_Pri), resPool(_resPool),
       eventType(e_type), inst(_inst), seqNum(seq_num),
       stageNum(stage_num), tid(_tid)
 { }
diff --git a/src/cpu/inorder/resource_pool.hh b/src/cpu/inorder/resource_pool.hh
index 85c0f70f6..51eb41338 100644
--- a/src/cpu/inorder/resource_pool.hh
+++ b/src/cpu/inorder/resource_pool.hh
@@ -67,6 +67,10 @@ class ResourcePool {
         Default
     };
 
+    enum ResPoolEventPri {
+        ResPool_Pri =  InOrderCPU::InOrderCPU_Pri - 5
+    };
+
     class ResPoolEvent : public Event
     {
       protected:
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc
index 024f38fdd..b79b17cdc 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc
@@ -165,7 +165,8 @@ FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
             // A Trap Caused This Fault and will update the pc state
             // when done trapping
             DPRINTF(InOrderFetchSeq, "[tid:%i] Blocking due to fault @ "
-                    "[sn:%i].\n", inst->seqNum);
+                    "[sn:%i].%s %s \n", inst->seqNum,
+                    inst->instName(), inst->pcState());
             pcValid[tid] = false;
         } else {
             TheISA::PCState nextPC;