arch, cpu: Do not forward snoops to table walker
This patch simplifies the overall CPU by changing the TLB caches such that they do not forward snoops to the table walker port(s). Note that only ARM and X86 are affected. There is no reason for the ports to snoop as they do not actually take any action, and from a performance point of view we are better of not snooping more than we have to. Should it at a later point be required to snoop for a particular TLB design it is easy enough to add it back.
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4 changed files with 3 additions and 42 deletions
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@ -79,4 +79,5 @@ class PageTableWalkerCache(BaseCache):
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mshrs = 10
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size = '1kB'
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tgts_per_mshr = 12
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forward_snoops = False
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is_top_level = True
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@ -174,7 +174,7 @@ class O3_ARM_v7aWalkCache(BaseCache):
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assoc = 8
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write_buffers = 16
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is_top_level = True
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forward_snoops = False
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# L2 Cache
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class O3_ARM_v7aL2(BaseCache):
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@ -57,40 +57,8 @@ class Stage2MMU : public SimObject
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protected:
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/**
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* A snooping DMA port that currently does nothing besides
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* extending the DMA port to accept snoops without
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* complaining. Currently we take no action on any snoops.
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*/
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class SnoopingDmaPort : public DmaPort
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{
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protected:
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virtual void recvTimingSnoopReq(PacketPtr pkt)
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{ }
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virtual Tick recvAtomicSnoop(PacketPtr pkt)
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{ return 0; }
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virtual void recvFunctionalSnoop(PacketPtr pkt)
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{ }
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virtual bool isSnooping() const { return true; }
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public:
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/**
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* A snooping DMA port merely calls the construtor of the DMA
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* port.
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*/
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SnoopingDmaPort(MemObject *dev, System *s) :
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DmaPort(dev, s)
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{ }
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};
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/** Port to issue translation requests from */
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SnoopingDmaPort port;
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DmaPort port;
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/** Request id for requests generated by this MMU */
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MasterID masterId;
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@ -70,15 +70,7 @@ namespace X86ISA
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Walker *walker;
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bool recvTimingResp(PacketPtr pkt);
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/**
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* Snooping a coherence request, do nothing.
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*/
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void recvTimingSnoopReq(PacketPtr pkt) { }
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Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
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void recvFunctionalSnoop(PacketPtr pkt) { }
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void recvReqRetry();
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bool isSnooping() const { return true; }
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};
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friend class WalkerPort;
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