params: Deprecate old-style constructors; update most SimObject constructors.

SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed.  Subclasses
that still rely on that behavior must call the parent initializer as
  : SimObject(makeParams(name))

--HG--
extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed

src/arch/alpha/tlb.cc

@@ -41,8 +41,6 @@
 #include "base/trace.hh"
 #include "config/alpha_tlaser.hh"
 #include "cpu/thread_context.hh"
-#include "params/AlphaDTB.hh"
-#include "params/AlphaITB.hh"
 
 using namespace std;
 using namespace EV5;
@@ -59,8 +57,8 @@ bool uncacheBit40 = false;
 
 #define MODE2MASK(X)			(1 << (X))
 
-TLB::TLB(const string &name, int s)
+TLB::TLB(const Params *p)
-    : SimObject(name), size(s), nlu(0)
+    : SimObject(p), size(p->size), nlu(0)
 {
     table = new TlbEntry[size];
     memset(table, 0, sizeof(TlbEntry[size]));
@@ -286,8 +284,8 @@ TLB::unserialize(Checkpoint *cp, const string &section)
 //
 //  Alpha ITB
 //
-ITB::ITB(const std::string &name, int size)
+ITB::ITB(const Params *p)
-    : TLB(name, size)
+    : TLB(p)
 {}
 
 
@@ -400,8 +398,8 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
 //
 //  Alpha DTB
 //
- DTB::DTB(const std::string &name, int size)
+ DTB::DTB(const Params *p)
-     : TLB(name, size)
+     : TLB(p)
 {}
 
 void
@@ -624,11 +622,11 @@ TLB::index(bool advance)
 AlphaISA::ITB *
 AlphaITBParams::create()
 {
-    return new AlphaISA::ITB(name, size);
+    return new AlphaISA::ITB(this);
 }
 
 AlphaISA::DTB *
 AlphaDTBParams::create()
 {
-    return new AlphaISA::DTB(name, size);
+    return new AlphaISA::DTB(this);
 }

src/arch/alpha/tlb.hh

@@ -41,6 +41,8 @@
 #include "arch/alpha/vtophys.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
+#include "params/AlphaDTB.hh"
+#include "params/AlphaITB.hh"
 #include "sim/faults.hh"
 #include "sim/sim_object.hh"
 
@@ -64,7 +66,8 @@ namespace AlphaISA
         TlbEntry *lookup(Addr vpn, uint8_t asn);
 
       public:
-        TLB(const std::string &name, int size);
+        typedef AlphaTLBParams Params;
+        TLB(const Params *p);
         virtual ~TLB();
 
         int getsize() const { return size; }
@@ -113,7 +116,8 @@ namespace AlphaISA
         mutable Stats::Formula accesses;
 
       public:
-        ITB(const std::string &name, int size);
+        typedef AlphaITBParams Params;
+        ITB(const Params *p);
         virtual void regStats();
 
         Fault translate(RequestPtr &req, ThreadContext *tc);
@@ -136,7 +140,8 @@ namespace AlphaISA
         Stats::Formula accesses;
 
       public:
-        DTB(const std::string &name, int size);
+        typedef AlphaDTBParams Params;
+        DTB(const Params *p);
         virtual void regStats();
 
         Fault translate(RequestPtr &req, ThreadContext *tc, bool write);

src/arch/mips/tlb.cc

@@ -31,8 +31,6 @@
 #include <cstring>
 
 #include "arch/mips/tlb.hh"
-#include "params/MipsDTB.hh"
-#include "params/MipsITB.hh"
 
 namespace MipsISA {
     Fault
@@ -69,11 +67,11 @@ namespace MipsISA {
 MipsISA::ITB *
 MipsITBParams::create()
 {
-    return new MipsISA::ITB(name);
+    return new MipsISA::ITB(this);
 }
 
 MipsISA::DTB *
 MipsDTBParams::create()
 {
-    return new MipsISA::DTB(name);
+    return new MipsISA::DTB(this);
 }

src/arch/mips/tlb.hh

@@ -31,6 +31,8 @@
 #ifndef __ARCH_MIPS_TLB_HH__
 #define __ARCH_MIPS_TLB_HH__
 
+#include "params/MipsDTB.hh"
+#include "params/MipsITB.hh"
 #include "sim/tlb.hh"
 
 namespace MipsISA
@@ -48,7 +50,8 @@ namespace MipsISA
     class TLB : public GenericTLB
     {
       public:
-        TLB(const std::string &name) : GenericTLB(name)
+        typedef MipsTLBParams Params;
+        TLB(const Params *p) : GenericTLB(p)
         {}
 
         Fault translate(RequestPtr req, ThreadContext *tc, bool=false);
@@ -57,14 +60,16 @@ namespace MipsISA
     class ITB : public TLB
     {
       public:
-        ITB(const std::string &name) : TLB(name)
+        typedef MipsITBParams Params;
+        ITB(const Params *p) : TLB(p)
         {}
     };
 
     class DTB : public TLB
     {
       public:
-        DTB(const std::string &name) : TLB(name)
+        typedef MipsDTBParams Params;
+        DTB(const Params *p) : TLB(p)
         {}
     };
 };

src/arch/sparc/tlb.cc

@@ -39,16 +39,14 @@
 #include "cpu/base.hh"
 #include "mem/packet_access.hh"
 #include "mem/request.hh"
-#include "params/SparcDTB.hh"
-#include "params/SparcITB.hh"
 #include "sim/system.hh"
 
 /* @todo remove some of the magic constants.  -- ali
  * */
 namespace SparcISA {
 
-TLB::TLB(const std::string &name, int s)
+TLB::TLB(const Params *p)
-    : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
+    : SimObject(p), size(p->size), usedEntries(0), lastReplaced(0),
       cacheValid(false)
 {
     // To make this work you'll have to change the hypervisor and OS
@@ -1437,11 +1435,11 @@ DTB::unserialize(Checkpoint *cp, const std::string &section)
 SparcISA::ITB *
 SparcITBParams::create()
 {
-    return new SparcISA::ITB(name, size);
+    return new SparcISA::ITB(this);
 }
 
 SparcISA::DTB *
 SparcDTBParams::create()
 {
-    return new SparcISA::DTB(name, size);
+    return new SparcISA::DTB(this);
 }

src/arch/sparc/tlb.hh

@@ -36,6 +36,8 @@
 #include "base/misc.hh"
 #include "config/full_system.hh"
 #include "mem/request.hh"
+#include "params/SparcDTB.hh"
+#include "params/SparcITB.hh"
 #include "sim/faults.hh"
 #include "sim/sim_object.hh"
 
@@ -147,7 +149,8 @@ class TLB : public SimObject
     void writeTagAccess(Addr va, int context);
 
   public:
-    TLB(const std::string &name, int size);
+    typedef SparcTLBParams Params;
+    TLB(const Params *p);
 
     void dumpAll();
 
@@ -163,7 +166,8 @@ class TLB : public SimObject
 class ITB : public TLB
 {
   public:
-    ITB(const std::string &name, int size) : TLB(name, size)
+    typedef SparcITBParams Params;
+    ITB(const Params *p) : TLB(p)
     {
         cacheEntry = NULL;
     }
@@ -182,7 +186,8 @@ class DTB : public TLB
   protected:
     uint64_t sfar;
   public:
-    DTB(const std::string &name, int size) : TLB(name, size)
+    typedef SparcDTBParams Params;
+    DTB(const Params *p) : TLB(p)
     {
         sfar = 0;
         cacheEntry[0] = NULL;

src/cpu/base.cc

@@ -95,12 +95,12 @@ CPUProgressEvent::description()
 
 #if FULL_SYSTEM
 BaseCPU::BaseCPU(Params *p)
-    : MemObject(p->name), clock(p->clock), instCnt(0),
+    : MemObject(makeParams(p->name)), clock(p->clock), instCnt(0),
       params(p), number_of_threads(p->numberOfThreads), system(p->system),
       phase(p->phase)
 #else
 BaseCPU::BaseCPU(Params *p)
-    : MemObject(p->name), clock(p->clock), params(p),
+    : MemObject(makeParams(p->name)), clock(p->clock), params(p),
       number_of_threads(p->numberOfThreads), system(p->system),
       phase(p->phase)
 #endif

src/cpu/exetrace.cc

@@ -39,7 +39,6 @@
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "enums/OpClass.hh"
-#include "params/ExeTracer.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -116,5 +115,5 @@ Trace::ExeTracerRecord::dump()
 Trace::ExeTracer *
 ExeTracerParams::create()
 {
-    return new Trace::ExeTracer(name);
+    return new Trace::ExeTracer(this);
 };

src/cpu/exetrace.hh

@@ -36,6 +36,7 @@
 #include "cpu/static_inst.hh"
 #include "sim/host.hh"
 #include "sim/insttracer.hh"
+#include "params/ExeTracer.hh"
 
 class ThreadContext;
 
@@ -57,8 +58,8 @@ class ExeTracerRecord : public InstRecord
 class ExeTracer : public InstTracer
 {
   public:
-
+    typedef ExeTracerParams Params;
-    ExeTracer(const std::string & name) : InstTracer(name)
+    ExeTracer(const Params *params) : InstTracer(params)
     {}
 
     InstRecord *

src/cpu/func_unit.cc

@@ -32,8 +32,6 @@
 
 #include "base/misc.hh"
 #include "cpu/func_unit.hh"
-#include "params/OpDesc.hh"
-#include "params/FUDesc.hh"
 
 using namespace std;
 
@@ -120,7 +118,7 @@ FuncUnit::issueLatency(OpClass capability)
 OpDesc *
 OpDescParams::create()
 {
-    return new OpDesc(name, opClass, opLat, issueLat);
+    return new OpDesc(this);
 }
 
 //
@@ -129,5 +127,5 @@ OpDescParams::create()
 FUDesc *
 FUDescParams::create()
 {
-    return new FUDesc(name, opList, count);
+    return new FUDesc(this);
 }

src/cpu/func_unit.hh

@@ -36,6 +36,8 @@
 #include <vector>
 
 #include "cpu/op_class.hh"
+#include "params/OpDesc.hh"
+#include "params/FUDesc.hh"
 #include "sim/sim_object.hh"
 
 ////////////////////////////////////////////////////////////////////////////
@@ -51,8 +53,9 @@ struct OpDesc : public SimObject
     unsigned    opLat;
     unsigned    issueLat;
 
-    OpDesc(std::string name, OpClass c, unsigned o, unsigned i)
+    OpDesc(const OpDescParams *p)
-        : SimObject(name), opClass(c), opLat(o), issueLat(i) {};
+        : SimObject(p), opClass(p->opClass), opLat(p->opLat),
+          issueLat(p->issueLat) {};
 };
 
 struct FUDesc : public SimObject
@@ -60,12 +63,12 @@ struct FUDesc : public SimObject
     std::vector<OpDesc *> opDescList;
     unsigned         number;
 
-    FUDesc(std::string name, std::vector<OpDesc *> l, unsigned n)
+    FUDesc(const FUDescParams *p)
-        : SimObject(name), opDescList(l), number(n) {};
+        : SimObject(p), opDescList(p->opList), number(p->count) {};
 };
 
-typedef std::vector<OpDesc *>::iterator OPDDiterator;
+typedef std::vector<OpDesc *>::const_iterator OPDDiterator;
-typedef std::vector<FUDesc *>::iterator FUDDiterator;
+typedef std::vector<FUDesc *>::const_iterator FUDDiterator;
 
 
 

src/cpu/inteltrace.cc

@@ -36,7 +36,6 @@
 #include "cpu/exetrace.hh"
 #include "cpu/inteltrace.hh"
 #include "cpu/static_inst.hh"
-#include "params/IntelTrace.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -66,5 +65,5 @@ Trace::IntelTraceRecord::dump()
 Trace::IntelTrace *
 IntelTraceParams::create()
 {
-    return new Trace::IntelTrace(name);
+    return new Trace::IntelTrace(this);
 };

src/cpu/inteltrace.hh

@@ -34,6 +34,7 @@
 
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
+#include "params/IntelTrace.hh"
 #include "sim/host.hh"
 #include "sim/insttracer.hh"
 
@@ -58,7 +59,7 @@ class IntelTrace : public InstTracer
 {
   public:
 
-    IntelTrace(const std::string & name) : InstTracer(name)
+    IntelTrace(const IntelTraceParams *p) : InstTracer(p)
     {}
 
     IntelTraceRecord *

src/cpu/intr_control.cc

@@ -35,13 +35,12 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/intr_control.hh"
-#include "params/IntrControl.hh"
 #include "sim/sim_object.hh"
 
 using namespace std;
 
-IntrControl::IntrControl(const string &name, System *s)
+IntrControl::IntrControl(const Params *p)
-    : SimObject(name), sys(s)
+    : SimObject(p), sys(p->sys)
 {}
 
 void
@@ -79,5 +78,5 @@ IntrControl::clear(int cpu_id, int int_num, int index)
 IntrControl *
 IntrControlParams::create()
 {
-    return new IntrControl(name, sys);
+    return new IntrControl(this);
 }

src/cpu/intr_control.hh

@@ -35,6 +35,7 @@
 #include <vector>
 #include "base/misc.hh"
 #include "cpu/base.hh"
+#include "params/IntrControl.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 
@@ -43,7 +44,8 @@ class IntrControl : public SimObject
 {
   public:
     System *sys;
-    IntrControl(const std::string &name, System *s);
+    typedef IntrControlParams Params;
+    IntrControl(const Params *p);
 
     void clear(int int_num, int index = 0);
     void post(int int_num, int index = 0);

src/cpu/legiontrace.cc

@@ -53,7 +53,6 @@
 #include "cpu/legiontrace.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
-#include "params/LegionTrace.hh"
 #include "sim/system.hh"
 
 #if FULL_SYSTEM
@@ -596,5 +595,5 @@ Trace::LegionTraceRecord::dump()
 Trace::LegionTrace *
 LegionTraceParams::create()
 {
-    return new Trace::LegionTrace(name);
+    return new Trace::LegionTrace(this);
 };

src/cpu/legiontrace.hh

@@ -34,6 +34,7 @@
 
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
+#include "params/LegionTrace.hh"
 #include "sim/host.hh"
 #include "sim/insttracer.hh"
 
@@ -56,8 +57,8 @@ class LegionTraceRecord : public InstRecord
 class LegionTrace : public InstTracer
 {
   public:
-
+    typedef LegionTraceParams Params;
-    LegionTrace(const std::string & name) : InstTracer(name)
+    LegionTrace(const Params *p) : InstTracer(p)
     {}
 
     LegionTraceRecord *

src/cpu/memtest/MemTest.py

@@ -26,12 +26,12 @@
 #
 # Authors: Nathan Binkert
 
-from m5.SimObject import SimObject
+from MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 from m5 import build_env
 
-class MemTest(SimObject):
+class MemTest(MemObject):
     type = 'MemTest'
     max_loads = Param.Counter(0, "number of loads to execute")
     atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")

src/cpu/memtest/memtest.cc

@@ -46,7 +46,6 @@
 #include "mem/packet.hh"
 //#include "mem/physical.hh"
 #include "mem/request.hh"
-#include "params/MemTest.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
 
@@ -119,37 +118,24 @@ MemTest::sendPkt(PacketPtr pkt) {
 
 }
 
-MemTest::MemTest(const string &name,
+MemTest::MemTest(const Params *p)
-//		 MemInterface *_cache_interface,
+    : MemObject(p),
-//		 PhysicalMemory *main_mem,
-//		 PhysicalMemory *check_mem,
-                 unsigned _memorySize,
-                 unsigned _percentReads,
-                 unsigned _percentFunctional,
-                 unsigned _percentUncacheable,
-                 unsigned _progressInterval,
-                 unsigned _percentSourceUnaligned,
-                 unsigned _percentDestUnaligned,
-                 Addr _traceAddr,
-                 Counter _max_loads,
-                 bool _atomic)
-    : MemObject(name),
       tickEvent(this),
       cachePort("test", this),
       funcPort("functional", this),
       retryPkt(NULL),
 //      mainMem(main_mem),
 //      checkMem(check_mem),
-      size(_memorySize),
+      size(p->memory_size),
-      percentReads(_percentReads),
+      percentReads(p->percent_reads),
-      percentFunctional(_percentFunctional),
+      percentFunctional(p->percent_functional),
-      percentUncacheable(_percentUncacheable),
+      percentUncacheable(p->percent_uncacheable),
-      progressInterval(_progressInterval),
+      progressInterval(p->progress_interval),
-      nextProgressMessage(_progressInterval),
+      nextProgressMessage(p->progress_interval),
-      percentSourceUnaligned(_percentSourceUnaligned),
+      percentSourceUnaligned(p->percent_source_unaligned),
-      percentDestUnaligned(percentDestUnaligned),
+      percentDestUnaligned(p->percent_dest_unaligned),
-      maxLoads(_max_loads),
+      maxLoads(p->max_loads),
-      atomic(_atomic)
+      atomic(p->atomic)
 {
     vector<string> cmd;
     cmd.push_back("/bin/ls");
@@ -161,7 +147,7 @@ MemTest::MemTest(const string &name,
     funcPort.snoopRangeSent = true;
 
     // Needs to be masked off once we know the block size.
-    traceBlockAddr = _traceAddr;
+    traceBlockAddr = p->trace_addr;
     baseAddr1 = 0x100000;
     baseAddr2 = 0x400000;
     uncacheAddr = 0x800000;
@@ -411,12 +397,5 @@ MemTest::doRetry()
 MemTest *
 MemTestParams::create()
 {
-    return new MemTest(name,
+    return new MemTest(this);
-#if 0
-                       cache->getInterface(), main_mem, check_mem,
-#endif
-                       memory_size, percent_reads, percent_functional,
-                       percent_uncacheable, progress_interval,
-                       percent_source_unaligned, percent_dest_unaligned,
-                       trace_addr, max_loads, atomic);
 }

src/cpu/memtest/memtest.hh

@@ -35,6 +35,7 @@
 #include <set>
 
 #include "base/statistics.hh"
+#include "params/MemTest.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_exit.hh"
 #include "sim/sim_object.hh"
@@ -46,18 +47,8 @@ class Packet;
 class MemTest : public MemObject
 {
   public:
-
+    typedef MemTestParams Params;
-    MemTest(const std::string &name,
+    MemTest(const Params *p);
-            unsigned _memorySize,
-            unsigned _percentReads,
-            unsigned _percentFunctional,
-            unsigned _percentUncacheable,
-            unsigned _progressInterval,
-            unsigned _percentSourceUnaligned,
-            unsigned _percentDestUnaligned,
-            Addr _traceAddr,
-            Counter _max_loads,
-            bool _atomic);
 
     virtual void init();
 

src/cpu/o3/fu_pool.cc

@@ -32,7 +32,6 @@
 
 #include "cpu/o3/fu_pool.hh"
 #include "cpu/func_unit.hh"
-#include "params/FUPool.hh"
 
 using namespace std;
 
@@ -69,8 +68,8 @@ FUPool::~FUPool()
 
 
 // Constructor
-FUPool::FUPool(string name, vector<FUDesc *> paramList)
+FUPool::FUPool(const Params *p)
-    : SimObject(name)
+    : SimObject(p)
 {
     numFU = 0;
 
@@ -84,6 +83,7 @@ FUPool::FUPool(string name, vector<FUDesc *> paramList)
     //
     //  Iterate through the list of FUDescData structures
     //
+    const vector<FUDesc *> &paramList =  p->FUList;
     for (FUDDiterator i = paramList.begin(); i != paramList.end(); ++i) {
 
         //
@@ -278,5 +278,5 @@ FUPool::takeOverFrom()
 FUPool *
 FUPoolParams::create()
 {
-    return new FUPool(name, FUList);
+    return new FUPool(this);
 }

src/cpu/o3/fu_pool.hh

@@ -38,6 +38,7 @@
 
 #include "base/sched_list.hh"
 #include "cpu/op_class.hh"
+#include "params/FUPool.hh"
 #include "sim/sim_object.hh"
 
 class FUDesc;
@@ -116,9 +117,9 @@ class FUPool : public SimObject
     typedef std::vector<FuncUnit *>::iterator fuListIterator;
 
   public:
-
+    typedef FUPoolParams Params;
     /** Constructs a FU pool. */
-    FUPool(std::string name, std::vector<FUDesc *> l);
+    FUPool(const Params *p);
     ~FUPool();
 
     /** Annotates units that provide memory operations. Included only because

src/dev/alpha/tsunami.cc

@@ -42,15 +42,14 @@
 #include "dev/alpha/tsunami_pchip.hh"
 #include "dev/alpha/tsunami_io.hh"
 #include "dev/alpha/tsunami.hh"
-#include "params/Tsunami.hh"
 #include "sim/system.hh"
 
 using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-Tsunami::Tsunami(const string &name, System *s, IntrControl *ic)
+Tsunami::Tsunami(const Params *p)
-    : Platform(name, ic), system(s)
+    : Platform(p), system(p->system)
 {
     // set the back pointer from the system to myself
     system->platform = this;
@@ -117,5 +116,5 @@ Tsunami::unserialize(Checkpoint *cp, const std::string &section)
 Tsunami *
 TsunamiParams::create()
 {
-    return new Tsunami(name, system, intrctrl);
+    return new Tsunami(this);
 }

src/dev/alpha/tsunami.hh

@@ -38,6 +38,7 @@
 #define __DEV_TSUNAMI_HH__
 
 #include "dev/platform.hh"
+#include "params/Tsunami.hh"
 
 class IdeController;
 class TsunamiCChip;
@@ -80,13 +81,8 @@ class Tsunami : public Platform
     int ipi_pending[Tsunami::Max_CPUs];
 
   public:
-    /**
+    typedef TsunamiParams Params;
-     * Constructor for the Tsunami Class.
+    Tsunami(const Params *p);
-     * @param name name of the object
-     * @param s system the object belongs to
-     * @param intctrl pointer to the interrupt controller
-     */
-    Tsunami(const std::string &name, System *s, IntrControl *intctrl);
 
     /**
      * Return the interrupting frequency to AlphaAccess

src/dev/disk_image.cc

@@ -45,8 +45,6 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "dev/disk_image.hh"
-#include "params/CowDiskImage.hh"
-#include "params/RawDiskImage.hh"
 #include "sim/sim_exit.hh"
 #include "sim/byteswap.hh"
 
@@ -56,10 +54,9 @@ using namespace std;
 //
 // Raw Disk image
 //
-RawDiskImage::RawDiskImage(const string &name, const string &filename,
+RawDiskImage::RawDiskImage(const Params* p)
-                           bool rd_only)
+    : DiskImage(p), disk_size(0)
-    : DiskImage(name), disk_size(0)
+{ open(p->image_file, p->read_only); }
-{ open(filename, rd_only); }
 
 RawDiskImage::~RawDiskImage()
 { close(); }
@@ -147,7 +144,7 @@ RawDiskImage::write(const uint8_t *data, off_t offset)
 RawDiskImage *
 RawDiskImageParams::create()
 {
-    return new RawDiskImage(name, image_file, read_only);
+    return new RawDiskImage(this);
 }
 
 ////////////////////////////////////////////////////////////////////////
@@ -157,10 +154,6 @@ RawDiskImageParams::create()
 const int CowDiskImage::VersionMajor = 1;
 const int CowDiskImage::VersionMinor = 0;
 
-CowDiskImage::CowDiskImage(const string &name, DiskImage *kid, int hash_size)
-    : DiskImage(name), child(kid), table(NULL)
-{ init(hash_size); }
-
 class CowDiskCallback : public Callback
 {
   private:
@@ -171,17 +164,20 @@ class CowDiskCallback : public Callback
     void process() { image->save(); delete this; }
 };
 
-CowDiskImage::CowDiskImage(const string &name, DiskImage *kid, int hash_size,
+CowDiskImage::CowDiskImage(const Params *p)
-                           const string &file, bool read_only)
+    : DiskImage(p), filename(p->image_file), child(p->child), table(NULL)
-    : DiskImage(name), filename(file), child(kid), table(NULL)
 {
-    if (!open(filename)) {
+    if (filename.empty()) {
-        assert(!read_only && "why have a non-existent read only file?");
+        init(p->table_size);
-        init(hash_size);
+    } else {
-    }
+        if (!open(filename)) {
+            assert(!p->read_only && "why have a non-existent read only file?");
+            init(p->table_size);
+        }
 
-    if (!read_only)
+        if (!p->read_only)
-        registerExitCallback(new CowDiskCallback(this));
+            registerExitCallback(new CowDiskCallback(this));
+    }
 }
 
 CowDiskImage::~CowDiskImage()
@@ -426,9 +422,5 @@ CowDiskImage::unserialize(Checkpoint *cp, const string &section)
 CowDiskImage *
 CowDiskImageParams::create()
 {
-    if (((string)image_file).empty())
+    return new CowDiskImage(this);
-        return new CowDiskImage(name, child, table_size);
-    else
-        return new CowDiskImage(name, child, table_size,
-                                image_file, read_only);
 }

src/dev/disk_image.hh

@@ -39,6 +39,9 @@
 
 #include "base/hashmap.hh"
 #include "sim/sim_object.hh"
+#include "params/DiskImage.hh"
+#include "params/CowDiskImage.hh"
+#include "params/RawDiskImage.hh"
 
 #define SectorSize (512)
 
@@ -51,7 +54,8 @@ class DiskImage : public SimObject
     bool initialized;
 
   public:
-    DiskImage(const std::string &name) : SimObject(name), initialized(false) {}
+    typedef DiskImageParams Params;
+    DiskImage(const Params *p) : SimObject(p), initialized(false) {}
     virtual ~DiskImage() {}
 
     virtual off_t size() const = 0;
@@ -72,8 +76,8 @@ class RawDiskImage : public DiskImage
     mutable off_t disk_size;
 
   public:
-    RawDiskImage(const std::string &name, const std::string &filename,
+    typedef RawDiskImageParams Params;
-                 bool rd_only);
+    RawDiskImage(const Params *p);
     ~RawDiskImage();
 
     void close();
@@ -113,9 +117,8 @@ class CowDiskImage : public DiskImage
     SectorTable *table;
 
   public:
-    CowDiskImage(const std::string &name, DiskImage *kid, int hash_size);
+    typedef CowDiskImageParams Params;
-    CowDiskImage(const std::string &name, DiskImage *kid, int hash_size,
+    CowDiskImage(const Params *p);
-                 const std::string &filename, bool read_only);
     ~CowDiskImage();
 
     void init(int hash_size);

src/dev/etherbus.hh

@@ -40,6 +40,7 @@
 #include "dev/etherobject.hh"
 #include "params/EtherBus.hh"
 #include "sim/sim_object.hh"
+#include "params/EtherBus.hh"
 
 class EtherDump;
 class EtherInt;

src/dev/etherdump.cc

@@ -40,13 +40,13 @@
 #include "base/misc.hh"
 #include "base/output.hh"
 #include "dev/etherdump.hh"
-#include "params/EtherDump.hh"
 #include "sim/core.hh"
 
 using std::string;
 
-EtherDump::EtherDump(const string &name, const string &file, int max)
+EtherDump::EtherDump(const Params *p)
-    : SimObject(name), stream(file.c_str()), maxlen(max)
+    : SimObject(p), stream(simout.resolve(p->file).c_str()),
+      maxlen(p->maxlen)
 {
 }
 
@@ -119,5 +119,5 @@ EtherDump::dumpPacket(EthPacketPtr &packet)
 EtherDump *
 EtherDumpParams::create()
 {
-    return new EtherDump(name, simout.resolve(file), maxlen);
+    return new EtherDump(this);
 }

src/dev/etherdump.hh

@@ -38,6 +38,7 @@
 #include <fstream>
 #include "dev/etherpkt.hh"
 #include "sim/sim_object.hh"
+#include "params/EtherDump.hh"
 
 /*
  * Simple object for creating a simple pcap style packet trace
@@ -53,7 +54,8 @@ class EtherDump : public SimObject
     Tick curtime;
 
   public:
-    EtherDump(const std::string &name, const std::string &file, int max);
+    typedef EtherDumpParams Params;
+    EtherDump(const Params *p);
 
     inline void dump(EthPacketPtr &pkt) { dumpPacket(pkt); }
 };

src/dev/etherlink.cc

@@ -54,10 +54,10 @@ using namespace std;
 EtherLink::EtherLink(const Params *p)
     : EtherObject(p)
 {
-    link[0] = new Link(name() + ".link0", this, 0, params()->speed,
+    link[0] = new Link(name() + ".link0", this, 0, p->speed,
-            params()->delay, params()->delay_var, params()->dump);
+                       p->delay, p->delay_var, p->dump);
-    link[1] = new Link(name() + ".link1", this, 1, params()->speed,
+    link[1] = new Link(name() + ".link1", this, 1, p->speed,
-            params()->delay, params()->delay_var, params()->dump);
+                       p->delay, p->delay_var, p->dump);
 
     interface[0] = new Interface(name() + ".int0", link[0], link[1]);
     interface[1] = new Interface(name() + ".int1", link[1], link[0]);

src/dev/etherlink.hh

@@ -42,6 +42,7 @@
 #include "sim/eventq.hh"
 #include "sim/host.hh"
 #include "sim/sim_object.hh"
+#include "params/EtherLink.hh"
 
 class EtherDump;
 class Checkpoint;

src/dev/ide_disk.cc

@@ -45,22 +45,20 @@
 #include "dev/disk_image.hh"
 #include "dev/ide_ctrl.hh"
 #include "dev/ide_disk.hh"
-#include "params/IdeDisk.hh"
 #include "sim/core.hh"
 #include "sim/sim_object.hh"
 
 using namespace std;
 using namespace TheISA;
 
-IdeDisk::IdeDisk(const string &name, DiskImage *img,
+IdeDisk::IdeDisk(const Params *p)
-                 int id, Tick delay)
+    : SimObject(p), ctrl(NULL), image(p->image), diskDelay(p->delay),
-    : SimObject(name), ctrl(NULL), image(img), diskDelay(delay),
       dmaTransferEvent(this), dmaReadCG(NULL), dmaReadWaitEvent(this),
       dmaWriteCG(NULL), dmaWriteWaitEvent(this), dmaPrdReadEvent(this),
       dmaReadEvent(this), dmaWriteEvent(this)
 {
     // Reset the device state
-    reset(id);
+    reset(p->driveID);
 
     // fill out the drive ID structure
     memset(&driveID, 0, sizeof(struct ataparams));
@@ -1117,5 +1115,5 @@ IdeDisk::unserialize(Checkpoint *cp, const string &section)
 IdeDisk *
 IdeDiskParams::create()
 {
-    return new IdeDisk(name, image, driveID, delay);
+    return new IdeDisk(this);
 }

src/dev/ide_disk.hh

@@ -42,6 +42,8 @@
 #include "dev/ide_wdcreg.h"
 #include "dev/io_device.hh"
 #include "sim/eventq.hh"
+#include "params/IdeDisk.hh"
+
 
 class ChunkGenerator;
 
@@ -248,14 +250,8 @@ class IdeDisk : public SimObject
     Stats::Formula totBytes;
 
   public:
-    /**
+    typedef IdeDiskParams Params;
-     * Create and initialize this Disk.
+    IdeDisk(const Params *p);
-     * @param name The name of this disk.
-     * @param img The disk image of this disk.
-     * @param id The disk ID (master=0/slave=1)
-     * @param disk_delay The disk delay in milliseconds
-     */
-    IdeDisk(const std::string &name, DiskImage *img, int id, Tick disk_delay);
 
     /**
      * Delete the data buffer.

src/dev/isa_fake.hh

@@ -39,7 +39,7 @@
 
 #include "base/range.hh"
 #include "dev/io_device.hh"
-#include "dev/alpha/tsunami.hh"
+// #include "dev/alpha/tsunami.hh"
 #include "params/IsaFake.hh"
 #include "mem/packet.hh"
 

src/dev/pciconfigall.cc

@@ -44,7 +44,7 @@
 
 using namespace std;
 
-PciConfigAll::PciConfigAll(Params *p)
+PciConfigAll::PciConfigAll(const Params *p)
     : PioDevice(p)
 {
     pioAddr = p->platform->calcConfigAddr(params()->bus,0,0);
@@ -74,7 +74,7 @@ PciConfigAll::read(PacketPtr pkt)
         panic("invalid access size(?) for PCI configspace!\n");
     }
     pkt->makeAtomicResponse();
-    return params()->pio_delay;
+    return params()->pio_latency;
 }
 
 Tick
@@ -98,14 +98,7 @@ PciConfigAll::addressRanges(AddrRangeList &range_list)
 PciConfigAll *
 PciConfigAllParams::create()
 {
-    PciConfigAll::Params *p = new PciConfigAll::Params;
+    return new PciConfigAll(this);
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    p->bus = bus;
-    p->size = size;
-
-    return new PciConfigAll(p);
 }
 
 #endif // DOXYGEN_SHOULD_SKIP_THIS

src/dev/pciconfigall.hh

@@ -40,6 +40,7 @@
 #include "dev/pcireg.h"
 #include "base/range.hh"
 #include "dev/io_device.hh"
+#include "params/PciConfigAll.hh"
 
 
 /**
@@ -52,19 +53,14 @@
 class PciConfigAll : public PioDevice
 {
   public:
-    struct Params :  public PioDevice::Params
+    typedef PciConfigAllParams Params;
-    {
-        Tick pio_delay;
-        Addr size;
-        int bus;
-    };
     const Params *params() const { return (const Params *)_params; }
 
     /**
      * Constructor for PCIConfigAll
      * @param p parameters structure
      */
-    PciConfigAll(Params *p);
+    PciConfigAll(const Params *p);
 
     /**
      * Read something in PCI config space. If the device does not exist

src/dev/platform.cc

@@ -36,8 +36,8 @@
 using namespace std;
 using namespace TheISA;
 
-Platform::Platform(const string &name, IntrControl *intctrl)
+Platform::Platform(const Params *p)
-    : SimObject(name), intrctrl(intctrl)
+    : SimObject(p), intrctrl(p->intrctrl)
 {
 }
 

src/dev/platform.hh

@@ -42,6 +42,7 @@
 
 #include "sim/sim_object.hh"
 #include "arch/isa_traits.hh"
+#include "params/Platform.hh"
 
 class PciConfigAll;
 class IntrControl;
@@ -59,7 +60,8 @@ class Platform : public SimObject
     System *system;
 
   public:
-    Platform(const std::string &name, IntrControl *intctrl);
+    typedef PlatformParams Params;
+    Platform(const Params *p);
     virtual ~Platform();
     virtual void postConsoleInt() = 0;
     virtual void clearConsoleInt() = 0;

src/dev/simconsole.cc

@@ -52,7 +52,6 @@
 #include "dev/platform.hh"
 #include "dev/simconsole.hh"
 #include "dev/uart.hh"
-#include "params/SimConsole.hh"
 
 using namespace std;
 
@@ -91,18 +90,24 @@ SimConsole::DataEvent::process(int revent)
 /*
  * SimConsole code
  */
-SimConsole::SimConsole(const string &name, ostream *os, int num, int port)
+SimConsole::SimConsole(const Params *p)
-    : SimObject(name), listenEvent(NULL), dataEvent(NULL), number(num),
+    : SimObject(p), listenEvent(NULL), dataEvent(NULL), number(p->number),
-      data_fd(-1), txbuf(16384), rxbuf(16384), outfile(os)
+      data_fd(-1), txbuf(16384), rxbuf(16384), outfile(NULL)
 #if TRACING_ON == 1
       , linebuf(16384)
 #endif
 {
-    if (outfile)
+    if (!p->output.empty()) {
-        outfile->setf(ios::unitbuf);
+        if (p->append_name)
+            outfile = simout.find(p->output + "." + p->name);
+        else
+            outfile = simout.find(p->output);
 
-    if (port)
+        outfile->setf(ios::unitbuf);
-        listen(port);
+    }
+
+    if (p->port)
+        listen(p->port);
 }
 
 SimConsole::~SimConsole()
@@ -328,14 +333,5 @@ SimConsole::out(char c)
 SimConsole *
 SimConsoleParams::create()
 {
-    string filename = output;
+    return new SimConsole(this);
-    ostream *stream = NULL;
-
-    if (!filename.empty()) {
-        if (append_name)
-            filename += "." + name;
-        stream = simout.find(filename);
-    }
-
-    return new SimConsole(name, stream, number, port);
 }

src/dev/simconsole.hh

@@ -43,6 +43,7 @@
 #include "base/pollevent.hh"
 #include "base/socket.hh"
 #include "sim/sim_object.hh"
+#include "params/SimConsole.hh"
 
 class ConsoleListener;
 class Uart;
@@ -84,7 +85,8 @@ class SimConsole : public SimObject
     int data_fd;
 
   public:
-    SimConsole(const std::string &name, std::ostream *os, int num, int port);
+    typedef SimConsoleParams Params;
+    SimConsole(const Params *p);
     ~SimConsole();
 
   protected:

src/dev/simple_disk.cc

@@ -45,13 +45,12 @@
 #include "dev/disk_image.hh"
 #include "dev/simple_disk.hh"
 #include "mem/port.hh"
-#include "params/SimpleDisk.hh"
 #include "sim/system.hh"
 
 using namespace std;
 
-SimpleDisk::SimpleDisk(const string &name, System *sys, DiskImage *img)
+SimpleDisk::SimpleDisk(const Params *p)
-    : SimObject(name), system(sys), image(img)
+    : SimObject(p), system(p->system), image(p->disk)
 {}
 
 SimpleDisk::~SimpleDisk()
@@ -94,5 +93,5 @@ SimpleDisk::write(Addr addr, baddr_t block, int count)
 SimpleDisk *
 SimpleDiskParams::create()
 {
-    return new SimpleDisk(name, system, disk);
+    return new SimpleDisk(this);
 }

src/dev/simple_disk.hh

@@ -37,6 +37,7 @@
 
 #include "sim/sim_object.hh"
 #include "arch/isa_traits.hh"
+#include "params/SimpleDisk.hh"
 
 class DiskImage;
 class System;
@@ -54,7 +55,8 @@ class SimpleDisk : public SimObject
     DiskImage *image;
 
   public:
-    SimpleDisk(const std::string &name, System *sys, DiskImage *img);
+    typedef SimpleDiskParams Params;
+    SimpleDisk(const Params *p);
     ~SimpleDisk();
 
     void read(Addr addr, baddr_t block, int count) const;

src/dev/sparc/t1000.cc

@@ -39,15 +39,14 @@
 #include "cpu/intr_control.hh"
 #include "dev/simconsole.hh"
 #include "dev/sparc/t1000.hh"
-#include "params/T1000.hh"
 #include "sim/system.hh"
 
 using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-T1000::T1000(const string &name, System *s, IntrControl *ic)
+T1000::T1000(const Params *p)
-    : Platform(name, ic), system(s)
+    : Platform(p), system(p->system)
 {
     // set the back pointer from the system to myself
     system->platform = this;
@@ -104,5 +103,5 @@ T1000::calcConfigAddr(int bus, int dev, int func)
 T1000 *
 T1000Params::create()
 {
-    return new T1000(name, system, intrctrl);
+    return new T1000(this);
 }

src/dev/sparc/t1000.hh

@@ -38,6 +38,7 @@
 #define __DEV_T1000_HH__
 
 #include "dev/platform.hh"
+#include "params/T1000.hh"
 
 class IdeController;
 class System;
@@ -49,13 +50,14 @@ class T1000 : public Platform
     System *system;
 
   public:
+    typedef T1000Params Params;
     /**
      * Constructor for the Tsunami Class.
      * @param name name of the object
      * @param s system the object belongs to
      * @param intctrl pointer to the interrupt controller
      */
-    T1000(const std::string &name, System *s, IntrControl *intctrl);
+    T1000(const Params *p);
 
     /**
      * Return the interrupting frequency to AlphaAccess

src/mem/bridge.cc

@@ -55,7 +55,7 @@ Bridge::BridgePort::BridgePort(const std::string &_name,
 }
 
 Bridge::Bridge(Params *p)
-    : MemObject(p->name),
+    : MemObject(p),
       portA(p->name + "-portA", this, &portB, p->delay, p->nack_delay,
               p->req_size_a, p->resp_size_a, p->filter_ranges_a),
       portB(p->name + "-portB", this, &portA, p->delay, p->nack_delay,

src/mem/bus.cc

@@ -39,7 +39,6 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "mem/bus.hh"
-#include "params/Bus.hh"
 
 Port *
 Bus::getPort(const std::string &if_name, int idx)
@@ -632,5 +631,5 @@ Bus::startup()
 Bus *
 BusParams::create()
 {
-    return new Bus(name, bus_id, clock, width, responder_set, block_size);
+    return new Bus(this);
 }

src/mem/bus.hh

@@ -50,6 +50,7 @@
 #include "mem/port.hh"
 #include "mem/request.hh"
 #include "sim/eventq.hh"
+#include "params/Bus.hh"
 
 class Bus : public MemObject
 {
@@ -361,12 +362,11 @@ class Bus : public MemObject
 
     unsigned int drain(Event *de);
 
-    Bus(const std::string &n, int bus_id, int _clock, int _width,
+    Bus(const BusParams *p)
-        bool responder_set, int dflt_blk_size)
+        : MemObject(p), busId(p->bus_id), clock(p->clock), width(p->width),
-        : MemObject(n), busId(bus_id), clock(_clock), width(_width),
           tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false),
           maxId(0), defaultPort(NULL), funcPort(NULL), funcPortId(-4),
-          responderSet(responder_set), defaultBlockSize(dflt_blk_size),
+          responderSet(p->responder_set), defaultBlockSize(p->block_size),
           cachedBlockSize(0), cachedBlockSizeValid(false)
     {
         //Both the width and clock period must be positive

src/mem/cache/base_cache.cc

@@ -48,22 +48,21 @@ BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
 }
 
 
-BaseCache::BaseCache(const std::string &name, Params &params)
+BaseCache::BaseCache(const Params *p)
-    : MemObject(name),
+    : MemObject(p),
-      mshrQueue(params.numMSHRs, 4, MSHRQueue_MSHRs),
+      mshrQueue(p->mshrs, 4, MSHRQueue_MSHRs),
-      writeBuffer(params.numWriteBuffers, params.numMSHRs+1000,
+      writeBuffer(p->write_buffers, p->mshrs+1000,
                   MSHRQueue_WriteBuffer),
-      blkSize(params.blkSize),
+      blkSize(p->block_size),
-      hitLatency(params.hitLatency),
+      hitLatency(p->latency),
-      numTarget(params.numTargets),
+      numTarget(p->tgts_per_mshr),
       blocked(0),
       noTargetMSHR(NULL),
-      missCount(params.maxMisses),
+      missCount(p->max_miss_count),
       drainEvent(NULL)
 {
 }
 
-
 void
 BaseCache::CachePort::recvStatusChange(Port::Status status)
 {

src/mem/cache/base_cache.hh

@@ -52,6 +52,7 @@
 #include "mem/packet.hh"
 #include "mem/tport.hh"
 #include "mem/request.hh"
+#include "params/BaseCache.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_exit.hh"
 
@@ -354,54 +355,9 @@ class BaseCache : public MemObject
     virtual void regStats();
 
   public:
-
+    typedef BaseCacheParams Params;
-    class Params
+    BaseCache(const Params *p);
-    {
+    ~BaseCache() {}
-      public:
-        /** The hit latency for this cache. */
-        int hitLatency;
-        /** The block size of this cache. */
-        int blkSize;
-        int numMSHRs;
-        int numTargets;
-        int numWriteBuffers;
-        /**
-         * The maximum number of misses this cache should handle before
-         * ending the simulation.
-         */
-        Counter maxMisses;
-
-        std::vector<Range<Addr> > cpuSideFilterRanges;
-        std::vector<Range<Addr> > memSideFilterRanges;
-        /**
-         * Construct an instance of this parameter class.
-         */
-        Params(int _hitLatency, int _blkSize,
-               int _numMSHRs, int _numTargets, int _numWriteBuffers,
-               Counter _maxMisses,
-               std::vector<Range<Addr> > cpu_side_filter_ranges,
-               std::vector<Range<Addr> > mem_side_filter_ranges)
-            : hitLatency(_hitLatency), blkSize(_blkSize),
-              numMSHRs(_numMSHRs), numTargets(_numTargets),
-              numWriteBuffers(_numWriteBuffers), maxMisses(_maxMisses),
-              cpuSideFilterRanges(cpu_side_filter_ranges),
-              memSideFilterRanges(mem_side_filter_ranges)
-        {
-        }
-    };
-
-    /**
-     * Create and initialize a basic cache object.
-     * @param name The name of this cache.
-     * @param hier_params Pointer to the HierParams object for this hierarchy
-     * of this cache.
-     * @param params The parameter object for this BaseCache.
-     */
-    BaseCache(const std::string &name, Params &params);
-
-    ~BaseCache()
-    {
-    }
 
     virtual void init();
 

src/mem/cache/cache.hh

@@ -202,34 +202,8 @@ class Cache : public BaseCache
     PacketPtr writebackBlk(BlkType *blk);
 
   public:
-
-    class Params
-    {
-      public:
-        TagStore *tags;
-        BaseCache::Params baseParams;
-        BasePrefetcher*prefetcher;
-        bool prefetchAccess;
-        const bool doFastWrites;
-        const bool prefetchMiss;
-
-        Params(TagStore *_tags,
-               BaseCache::Params params,
-               BasePrefetcher *_prefetcher,
-               bool prefetch_access, int hit_latency,
-               bool do_fast_writes,
-               bool prefetch_miss)
-            : tags(_tags),
-              baseParams(params),
-              prefetcher(_prefetcher), prefetchAccess(prefetch_access),
-              doFastWrites(do_fast_writes),
-              prefetchMiss(prefetch_miss)
-        {
-        }
-    };
-
     /** Instantiates a basic cache object. */
-    Cache(const std::string &_name, Params &params);
+    Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
 
     virtual Port *getPort(const std::string &if_name, int idx = -1);
     virtual void deletePortRefs(Port *p);

src/mem/cache/cache_builder.cc

@@ -95,12 +95,8 @@ using namespace TheISA;
         else {                                                          \
             BUILD_NULL_PREFETCHER(TAGS);                                \
         }                                                               \
-        Cache<TAGS>::Params params(tags, base_params,       \
+        Cache<TAGS> *retval =                                           \
-                                   pf, prefetch_access, latency,        \
+            new Cache<TAGS>(this, tags, pf);                            \
-                                   true,                                \
-                                   prefetch_miss);                      \
-        Cache<TAGS> *retval =                                        \
-            new Cache<TAGS>(name, params);                              \
         return retval;                                                  \
     } while (0)
 
@@ -178,54 +174,28 @@ using namespace TheISA;
 
 #if defined(USE_TAGGED)
 #define BUILD_TAGGED_PREFETCHER(t)                              \
-    pf = new TaggedPrefetcher(prefetcher_size,                  \
+    pf = new TaggedPrefetcher(this)
-                              !prefetch_past_page,              \
-                              prefetch_serial_squash,           \
-                              prefetch_cache_check_push,        \
-                              prefetch_data_accesses_only,      \
-                              prefetch_latency,                 \
-                              prefetch_degree)
 #else
 #define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
 #endif
 
 #if defined(USE_STRIDED)
 #define BUILD_STRIDED_PREFETCHER(t)                             \
-    pf = new StridePrefetcher(prefetcher_size,                  \
+    pf = new StridePrefetcher(this)
-                              !prefetch_past_page,              \
-                              prefetch_serial_squash,           \
-                              prefetch_cache_check_push,        \
-                              prefetch_data_accesses_only,      \
-                              prefetch_latency,                 \
-                              prefetch_degree,                  \
-                              prefetch_use_cpu_id)
 #else
 #define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
 #endif
 
 #if defined(USE_GHB)
 #define BUILD_GHB_PREFETCHER(t)                         \
-    pf = new GHBPrefetcher(prefetcher_size,             \
+    pf = new GHBPrefetcher(this)
-                           !prefetch_past_page,         \
-                           prefetch_serial_squash,      \
-                           prefetch_cache_check_push,   \
-                           prefetch_data_accesses_only, \
-                           prefetch_latency,            \
-                           prefetch_degree,             \
-                           prefetch_use_cpu_id)
 #else
 #define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
 #endif
 
 #if defined(USE_TAGGED)
 #define BUILD_NULL_PREFETCHER(t)                                \
-    pf = new TaggedPrefetcher(prefetcher_size,                  \
+    pf = new TaggedPrefetcher(this)
-                              !prefetch_past_page,              \
-                              prefetch_serial_squash,           \
-                              prefetch_cache_check_push,        \
-                              prefetch_data_accesses_only,      \
-                              prefetch_latency,                 \
-                              prefetch_degree)
 #else
 #define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
 #endif
@@ -238,12 +208,6 @@ BaseCacheParams::create()
         subblock_size = block_size;
     }
 
-    // Build BaseCache param object
-    BaseCache::Params base_params(latency, block_size,
-                                  mshrs, tgts_per_mshr, write_buffers,
-                                  max_miss_count, cpu_side_filter_ranges,
-                                  mem_side_filter_ranges);
-
     //Warnings about prefetcher policy
     if (prefetch_policy == Enums::none) {
         if (prefetch_miss || prefetch_access)

src/mem/cache/cache_impl.hh

@@ -50,22 +50,21 @@
 
 
 template<class TagStore>
-Cache<TagStore>::Cache(const std::string &_name,
+Cache<TagStore>::Cache(const Params *p, TagStore *tags, BasePrefetcher *pf)
-                       Cache<TagStore>::Params &params)
+    : BaseCache(p),
-    : BaseCache(_name, params.baseParams),
+      prefetchAccess(p->prefetch_access),
-      prefetchAccess(params.prefetchAccess),
+      tags(tags),
-      tags(params.tags),
+      prefetcher(pf),
-      prefetcher(params.prefetcher),
+      doFastWrites(true),
-      doFastWrites(params.doFastWrites),
+      prefetchMiss(p->prefetch_miss)
-      prefetchMiss(params.prefetchMiss)
 {
     tempBlock = new BlkType();
     tempBlock->data = new uint8_t[blkSize];
 
-    cpuSidePort = new CpuSidePort(_name + "-cpu_side_port", this,
+    cpuSidePort = new CpuSidePort(p->name + "-cpu_side_port", this,
-            params.baseParams.cpuSideFilterRanges);
+            p->cpu_side_filter_ranges);
-    memSidePort = new MemSidePort(_name + "-mem_side_port", this,
+    memSidePort = new MemSidePort(p->name + "-mem_side_port", this,
-            params.baseParams.memSideFilterRanges);
+            p->mem_side_filter_ranges);
     cpuSidePort->setOtherPort(memSidePort);
     memSidePort->setOtherPort(cpuSidePort);
 

src/mem/cache/prefetch/base_prefetcher.cc

@@ -39,10 +39,11 @@
 #include "mem/request.hh"
 #include <list>
 
-BasePrefetcher::BasePrefetcher(int size, bool pageStop, bool serialSquash,
+BasePrefetcher::BasePrefetcher(const BaseCacheParams *p)
-                               bool cacheCheckPush, bool onlyData)
+    : size(p->prefetcher_size), pageStop(!p->prefetch_past_page),
-    :size(size), pageStop(pageStop), serialSquash(serialSquash),
+      serialSquash(p->prefetch_serial_squash),
-     cacheCheckPush(cacheCheckPush), only_data(onlyData)
+      cacheCheckPush(p->prefetch_cache_check_push),
+      only_data(p->prefetch_data_accesses_only)
 {
 }
 

src/mem/cache/prefetch/base_prefetcher.hh

@@ -40,6 +40,7 @@
 
 #include "base/statistics.hh"
 #include "mem/packet.hh"
+#include "params/BaseCache.hh"
 
 class BaseCache;
 
@@ -89,8 +90,7 @@ class BasePrefetcher
     void regStats(const std::string &name);
 
   public:
-    BasePrefetcher(int numMSHRS, bool pageStop, bool serialSquash,
+    BasePrefetcher(const BaseCacheParams *p);
-                   bool cacheCheckPush, bool onlyData);
 
     virtual ~BasePrefetcher() {}
 

src/mem/cache/prefetch/ghb_prefetcher.hh

@@ -51,12 +51,9 @@ class GHBPrefetcher : public BasePrefetcher
 
   public:
 
-    GHBPrefetcher(int size, bool pageStop, bool serialSquash,
+    GHBPrefetcher(const BaseCacheParams *p)
-                  bool cacheCheckPush, bool onlyData,
+        : BasePrefetcher(p), latency(p->prefetch_latency),
-                  Tick latency, int degree, bool useCPUId)
+          degree(p->prefetch_degree), useCPUId(p->prefetch_use_cpu_id)
-        : BasePrefetcher(size, pageStop, serialSquash,
-                         cacheCheckPush, onlyData),
-          latency(latency), degree(degree), useCPUId(useCPUId)
     {
     }
 

src/mem/cache/prefetch/stride_prefetcher.hh

@@ -68,12 +68,9 @@ class StridePrefetcher : public BasePrefetcher
 
   public:
 
-    StridePrefetcher(int size, bool pageStop, bool serialSquash,
+    StridePrefetcher(const BaseCacheParams *p)
-                     bool cacheCheckPush, bool onlyData,
+        : BasePrefetcher(p), latency(p->prefetch_latency),
-                     Tick latency, int degree, bool useCPUId)
+          degree(p->prefetch_degree), useCPUId(p->prefetch_use_cpu_id)
-        : BasePrefetcher(size, pageStop, serialSquash,
-                         cacheCheckPush, onlyData),
-          latency(latency), degree(degree), useCPUId(useCPUId)
     {
     }
 

src/mem/cache/prefetch/tagged_prefetcher.cc

@@ -36,13 +36,9 @@
 #include "arch/isa_traits.hh"
 #include "mem/cache/prefetch/tagged_prefetcher.hh"
 
-TaggedPrefetcher::
+TaggedPrefetcher::TaggedPrefetcher(const BaseCacheParams *p)
-TaggedPrefetcher(int size, bool pageStop, bool serialSquash,
+    : BasePrefetcher(p),
-                 bool cacheCheckPush, bool onlyData,
+      latency(p->prefetch_latency), degree(p->prefetch_degree)
-                 Tick latency, int degree)
-    : BasePrefetcher(size, pageStop, serialSquash,
-                     cacheCheckPush, onlyData),
-      latency(latency), degree(degree)
 {
 }
 

src/mem/cache/prefetch/tagged_prefetcher.hh

@@ -47,9 +47,7 @@ class TaggedPrefetcher : public BasePrefetcher
 
   public:
 
-    TaggedPrefetcher(int size, bool pageStop, bool serialSquash,
+    TaggedPrefetcher(const BaseCacheParams *p);
-                     bool cacheCheckPush, bool onlyData,
-                     Tick latency, int degree);
 
     ~TaggedPrefetcher() {}
 

src/mem/cache/tags/repl/gen.cc

@@ -44,19 +44,11 @@
 
 using namespace std;
 
-GenRepl::GenRepl(const string &_name,
+GenRepl::GenRepl(const Params *p) // fix this, should be set by cache
-                 int _num_pools,
+    : Repl(p), num_pools(p->num_pools), fresh_res(p->fresh_res),
-                 int _fresh_res,
+      pool_res(p->pool_res), num_entries(0), num_pool_entries(0), misses(0),
-                 int _pool_res) // fix this, should be set by cache
+      pools(pools = new GenPool[num_pools+1])
-    : Repl(_name)
 {
-    num_pools = _num_pools;
-    fresh_res = _fresh_res;
-    pool_res = _pool_res;
-    num_entries = 0;
-    num_pool_entries = 0;
-    misses = 0;
-    pools = new GenPool[num_pools+1];
 }
 
 GenRepl::~GenRepl()
@@ -250,5 +242,5 @@ GenRepl::findTagPtr(unsigned long index)
 GenRepl *
 GenReplParams::create()
 {
-    return new GenRepl(name, num_pools, fresh_res, pool_res);
+    return new GenRepl(this);
 }

src/mem/cache/tags/repl/gen.hh

@@ -40,6 +40,7 @@
 
 #include "base/statistics.hh"
 #include "mem/cache/tags/repl/repl.hh"
+#include "params/GenRepl.hh"
 
 /**
  * Generational Replacement entry.
@@ -139,8 +140,6 @@ class GenPool
 class GenRepl : public Repl
 {
   public:
-    /** The array of pools. */
-    GenPool *pools;
     /** The number of pools. */
     int num_pools;
     /** The amount of time to stay in the fresh pool. */
@@ -153,6 +152,8 @@ class GenRepl : public Repl
     int num_pool_entries;
     /** The number of misses. Used as the internal time. */
     Tick misses;
+    /** The array of pools. */
+    GenPool *pools;
 
     // Statistics
 
@@ -170,15 +171,8 @@ class GenRepl : public Repl
      * @}
      */
 
-    /**
+    typedef GenReplParams Params;
-     * Constructs and initializes this replacement policy.
+    GenRepl(const Params *p);
-     * @param name The name of the policy.
-     * @param num_pools The number of pools to use.
-     * @param fresh_res The amount of time to wait in the fresh pool.
-     * @param pool_res The amount of time to wait in the normal pools.
-     */
-    GenRepl(const std::string &name, int num_pools,
-            int fresh_res, int pool_res);
 
     /**
      * Destructor.

src/mem/cache/tags/repl/repl.hh

@@ -58,12 +58,8 @@ class Repl : public SimObject
     /** Pointer to the IIC using this policy. */
     IIC *iic;
 
-    /**
+    Repl (const Params *params)
-     * Construct and initialize this polixy.
+        : SimObject(params)
-     * @param name The instance name of this policy.
-     */
-    Repl (const std::string &name)
-        : SimObject(name)
     {
         iic = NULL;
     }

src/mem/mem_object.cc

@@ -35,9 +35,12 @@ MemObject::MemObject(const Params *params)
 {
 }
 
-MemObject::MemObject(const std::string &name)
+MemObjectParams *
-    : SimObject(name)
+MemObject::makeParams(const std::string &name)
 {
+    MemObjectParams *params = new MemObjectParams;
+    params->name = name;
+    return params;
 }
 
 void

src/mem/mem_object.hh

@@ -49,7 +49,6 @@ class MemObject : public SimObject
   public:
     typedef MemObjectParams Params;
     MemObject(const Params *params);
-    MemObject(const std::string &name);
 
     const Params *
     params() const
@@ -57,6 +56,10 @@ class MemObject : public SimObject
         return dynamic_cast<const Params *>(_params);
     }
 
+  protected:
+    // static: support for old-style constructors (call manually)
+    static Params *makeParams(const std::string &name);
+
   public:
     /** Additional function to return the Port of a memory object. */
     virtual Port *getPort(const std::string &if_name, int idx = -1) = 0;

src/python/swig/sim_object.i

@@ -53,7 +53,7 @@ class SimObject {
     void resume();
     void switchOut();
     void takeOverFrom(BaseCPU *cpu);
-    SimObject(const std::string &_name);
+    SimObject(const SimObjectParams *p);
 };
 
 int connectPorts(SimObject *o1, const std::string &name1, int i1,

src/sim/insttracer.hh

@@ -129,7 +129,7 @@ class InstRecord
 class InstTracer : public SimObject
 {
   public:
-    InstTracer(const std::string & name) : SimObject(name)
+    InstTracer(const Params *p) : SimObject(p)
     {}
 
     virtual ~InstTracer()

src/sim/process.cc

@@ -88,7 +88,7 @@ Process::Process(const string &nm,
                  int stdin_fd, 	// initial I/O descriptors
                  int stdout_fd,
                  int stderr_fd)
-    : SimObject(nm), system(_system)
+    : SimObject(makeParams(nm)), system(_system)
 {
     M5_pid = system->allocatePID();
     // initialize first 3 fds (stdin, stdout, stderr)

src/sim/sim_object.cc

@@ -70,25 +70,13 @@ SimObject::SimObject(const Params *p)
 }
 
 SimObjectParams *
-makeParams(const string &name)
+SimObject::makeParams(const std::string &name)
 {
     SimObjectParams *params = new SimObjectParams;
     params->name = name;
-
     return params;
 }
 
-SimObject::SimObject(const string &_name)
-    : _params(makeParams(_name))
-{
-#ifdef DEBUG
-    doDebugBreak = false;
-#endif
-
-    simObjectList.push_back(this);
-    state = Running;
-}
-
 void
 SimObject::init()
 {

src/sim/sim_object.hh

@@ -84,9 +84,14 @@ class SimObject : public Serializable, protected StartupCallback
     typedef SimObjectParams Params;
     const Params *params() const { return _params; }
     SimObject(const Params *_params);
-    SimObject(const std::string &_name);
     virtual ~SimObject() {}
 
+  protected:
+    // static: support for old-style constructors (call manually)
+    static Params *makeParams(const std::string &name);
+
+  public:
+
     virtual const std::string name() const { return params()->name; }
 
     // initialization pass of all objects.

src/sim/system.cc

@@ -57,7 +57,7 @@ vector<System *> System::systemList;
 int System::numSystemsRunning = 0;
 
 System::System(Params *p)
-    : SimObject(p->name), physmem(p->physmem), numcpus(0),
+    : SimObject(p), physmem(p->physmem), numcpus(0),
 #if FULL_SYSTEM
       init_param(p->init_param),
       functionalPort(p->name + "-fport"),

src/sim/tlb.hh

@@ -42,7 +42,7 @@ class Packet;
 class GenericTLB : public SimObject
 {
   protected:
-    GenericTLB(const std::string &name) : SimObject(name)
+    GenericTLB(const Params *p) : SimObject(p)
     {}
 
   public: