rewrote uart and renamed console.cc to simconsole to reduce confusion
base/traceflags.py: removed TsunamiUart/TlaserUart and added a plain Uart dev/alpha_console.cc: updated for new simconsole dev/platform.hh: added a uart member to platform dev/simconsole.cc: dev/simconsole.hh: removed lots of legacy code, it should all be ours now. converted tabs to 8 spaces added our copyright dev/tsunami.cc: uses simconsole.hh rather than console.hh dev/tsunami_cchip.cc: dev/tsunami_io.cc: never needed console.hh dev/tsunami_io.hh: this does need eventq.hh and it just happend to be working whenn console.hh was included everywhere dev/tsunamireg.h: added a couple more 8250/16550 uart defines dev/uart.cc: new uart code, rewritten to support both tlaser and tsunami (both a 8250 and 8530 uart). dev/uart.hh: updated for new uart, legacy code removed --HG-- rename : dev/console.cc => dev/simconsole.cc rename : dev/console.hh => dev/simconsole.hh rename : dev/tsunami_uart.cc => dev/uart.cc rename : dev/tsunami_uart.hh => dev/uart.hh extra : convert_revision : e663352d49d4c2d3c95643030cf73c0e85ba2f08
This commit is contained in:
parent
4799a7b874
commit
54b49f933a
13 changed files with 556 additions and 476 deletions
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@ -63,7 +63,6 @@ baseFlags = [
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'Console',
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'ConsolePoll',
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'ConsoleVerbose',
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'TlaserUart',
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'AlphaConsole',
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'Flow',
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'Interrupt',
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@ -114,7 +113,7 @@ baseFlags = [
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'IdeCtrl',
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'IdeDisk',
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'Tsunami',
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'TsunamiUart'
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'Uart'
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]
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#
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@ -40,7 +40,7 @@
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#include "cpu/base_cpu.hh"
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#include "cpu/exec_context.hh"
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#include "dev/alpha_console.hh"
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#include "dev/console.hh"
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#include "dev/simconsole.hh"
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#include "dev/simple_disk.hh"
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#include "dev/tlaser_clock.hh"
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#include "mem/bus/bus.hh"
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@ -226,7 +226,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
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break;
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case offsetof(AlphaAccess, outputChar):
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console->out((char)(val & 0xff), false);
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console->out((char)(val & 0xff));
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break;
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case offsetof(AlphaAccess, bootStrapImpure):
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@ -39,6 +39,7 @@
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class PciConfigAll;
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class IntrControl;
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class SimConsole;
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class Uart;
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class Platform : public SimObject
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{
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@ -50,6 +51,9 @@ class Platform : public SimObject
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/** Pointer to the PCI configuration space */
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PciConfigAll *pciconfig;
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/** Pointer to the UART, set by the uart */
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Uart *uart;
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int interrupt_frequency;
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public:
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@ -1,8 +1,33 @@
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/* $Id$ */
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/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* User Console Definitions
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* Implements the user interface to a serial console
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*/
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#include <sys/ioctl.h>
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@ -20,10 +45,11 @@
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#include "base/misc.hh"
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#include "base/socket.hh"
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#include "base/trace.hh"
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#include "dev/console.hh"
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#include "dev/simconsole.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "targetarch/ev5.hh"
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#include "dev/uart.hh"
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#include "dev/platform.hh"
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using namespace std;
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@ -48,17 +74,17 @@ SimConsole::Event::process(int revent)
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SimConsole::SimConsole(const string &name, const string &file, int num)
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: SimObject(name), event(NULL), number(num), in_fd(-1), out_fd(-1),
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listener(NULL), txbuf(16384), rxbuf(16384), outfile(NULL),
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listener(NULL), txbuf(16384), rxbuf(16384), outfile(NULL)
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#if TRACING_ON == 1
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linebuf(16384),
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, linebuf(16384)
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#endif
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_status(0), _enable(0), intr(NULL), platform(NULL)
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{
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if (!file.empty())
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outfile = new ofstream(file.c_str());
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if (outfile)
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outfile->setf(ios::unitbuf);
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}
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SimConsole::~SimConsole()
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@ -130,7 +156,8 @@ SimConsole::data()
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len = read(buf, sizeof(buf));
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if (len) {
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rxbuf.write((char *)buf, len);
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raiseInt(ReceiveInterrupt);
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// Inform the UART there is data available
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uart->dataAvailable();
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}
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}
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@ -138,7 +165,7 @@ size_t
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SimConsole::read(uint8_t *buf, size_t len)
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{
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if (in_fd < 0)
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panic("SimConsole(read): Console not properly attached.\n");
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panic("Console not properly attached.\n");
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size_t ret;
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do {
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@ -147,7 +174,7 @@ SimConsole::read(uint8_t *buf, size_t len)
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if (ret < 0)
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DPRINTFN("SimConsole(read): Read failed.\n");
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DPRINTFN("Read failed.\n");
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if (ret <= 0) {
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detach();
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@ -162,7 +189,7 @@ size_t
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SimConsole::write(const uint8_t *buf, size_t len)
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{
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if (out_fd < 0)
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panic("SimConsole(write): Console not properly attached.\n");
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panic("Console not properly attached.\n");
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size_t ret;
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for (;;) {
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@ -178,27 +205,6 @@ SimConsole::write(const uint8_t *buf, size_t len)
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return ret;
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}
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void
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SimConsole::configTerm()
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{
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struct termios ios;
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if (isatty(out_fd)) {
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if (tcgetattr(out_fd, &ios) < 0) {
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panic( "tcgetattr\n");
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}
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ios.c_iflag &= ~(ISTRIP|ICRNL|IGNCR|ICRNL|IXOFF|IXON);
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ios.c_oflag &= ~(OPOST);
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ios.c_oflag &= (ONLCR);
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ios.c_lflag &= ~(ISIG|ICANON|ECHO);
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ios.c_cc[VMIN] = 1;
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ios.c_cc[VTIME] = 0;
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if (tcsetattr(out_fd, TCSANOW, &ios) < 0) {
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panic( "tcsetattr\n");
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}
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}
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}
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#define MORE_PENDING (ULL(1) << 61)
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#define RECEIVE_SUCCESS (ULL(0) << 62)
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#define RECEIVE_NONE (ULL(2) << 62)
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empty = rxbuf.empty();
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}
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if (empty)
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clearInt(ReceiveInterrupt);
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DPRINTF(ConsoleVerbose, "in: \'%c\' %#02x more: %d, return: %d\n",
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isprint(c) ? c : ' ', c, !empty, ret);
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@ -245,7 +248,7 @@ SimConsole::console_in()
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}
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void
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SimConsole::out(char c, bool raise_int)
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SimConsole::out(char c)
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{
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#if TRACING_ON == 1
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if (DTRACE(Console)) {
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@ -277,90 +280,20 @@ SimConsole::out(char c, bool raise_int)
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if (outfile)
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outfile->write(&c, 1);
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if (raise_int)
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raiseInt(TransmitInterrupt);
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DPRINTF(ConsoleVerbose, "out: \'%c\' %#02x",
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DPRINTF(ConsoleVerbose, "out: \'%c\' %#02x\n",
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isprint(c) ? c : ' ', (int)c);
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if (raise_int)
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DPRINTF(ConsoleVerbose, "status: %#x\n", _status);
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else
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DPRINTF(ConsoleVerbose, "\n");
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}
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inline bool
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MaskStatus(int status, int mask)
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{ return (status & mask) != 0; }
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int
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SimConsole::clearInt(int i)
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{
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int old = _status;
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_status &= ~i;
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//if (MaskStatus(old, _enable) != MaskStatus(_status, _enable) && intr)
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platform->clearConsoleInt();
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return old;
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}
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void
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SimConsole::raiseInt(int i)
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{
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//int old = _status;
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_status |= i;
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//if (MaskStatus(old, _enable) != MaskStatus(_status, _enable) && intr)
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platform->postConsoleInt();
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}
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void
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SimConsole::initInt(IntrControl *i)
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{
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if (intr)
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panic("Console has already been initialized.");
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intr = i;
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}
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void
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SimConsole::setInt(int bits)
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{
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int old;
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if (bits & ~(TransmitInterrupt | ReceiveInterrupt))
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panic("An interrupt was not set!");
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old = _enable;
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_enable |= bits;
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//if (MaskStatus(_status, old) != MaskStatus(_status, _enable) && intr) {
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if (intr) {
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if (MaskStatus(_status, _enable))
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platform->postConsoleInt();
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else
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platform->clearConsoleInt();
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}
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}
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void
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SimConsole::setPlatform(Platform *p)
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{
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platform = p;
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platform->cons = this;
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}
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void
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SimConsole::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(_status);
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SERIALIZE_SCALAR(_enable);
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}
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void
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SimConsole::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(_status);
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UNSERIALIZE_SCALAR(_enable);
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}
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@ -368,7 +301,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
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SimObjectParam<ConsoleListener *> listener;
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SimObjectParam<IntrControl *> intr_control;
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SimObjectParam<Platform *> platform;
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Param<string> output;
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Param<bool> append_name;
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Param<int> number;
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@ -379,7 +311,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimConsole)
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INIT_PARAM(listener, "console listener"),
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INIT_PARAM(intr_control, "interrupt controller"),
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INIT_PARAM(platform, "platform"),
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INIT_PARAM_DFLT(output, "file to dump output to", ""),
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INIT_PARAM_DFLT(append_name, "append name() to filename", true),
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INIT_PARAM_DFLT(number, "console number", 0)
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@ -401,10 +332,6 @@ CREATE_SIM_OBJECT(SimConsole)
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SimConsole *console = new SimConsole(getInstanceName(), filename, number);
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((ConsoleListener *)listener)->add(console);
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((SimConsole *)console)->initInt(intr_control);
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((SimConsole *)console)->setPlatform(platform);
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//((SimConsole *)console)->setInt(SimConsole::TransmitInterrupt |
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// SimConsole::ReceiveInterrupt);
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return console;
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}
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@ -1,4 +1,30 @@
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/* $Id$ */
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/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* @file
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||||
* User Console Interface
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@ -16,8 +42,13 @@
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#include "sim/sim_object.hh"
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class ConsoleListener;
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class Uart;
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class SimConsole : public SimObject
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{
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public:
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Uart *uart;
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protected:
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class Event : public PollEvent
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{
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@ -36,8 +67,6 @@ class SimConsole : public SimObject
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int number;
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int in_fd;
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int out_fd;
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protected:
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ConsoleListener *listener;
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public:
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|
@ -68,18 +97,6 @@ class SimConsole : public SimObject
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void write(uint8_t c) { write(&c, 1); }
|
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size_t write(const uint8_t *buf, size_t len);
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|
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void configTerm();
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||||
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protected:
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// interrupt status/enable
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int _status;
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int _enable;
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|
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// interrupt handle
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||||
IntrControl *intr;
|
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// Platform so we can post interrupts
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Platform *platform;
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public:
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/////////////////
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// OS interface
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||||
|
@ -102,24 +119,10 @@ class SimConsole : public SimObject
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uint64_t console_in();
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||||
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||||
// Send a character to the console
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||||
void out(char c, bool raise_int = true);
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void out(char c);
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||||
|
||||
enum {
|
||||
TransmitInterrupt = 1,
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||||
ReceiveInterrupt = 2
|
||||
};
|
||||
|
||||
// Read the current interrupt status of this console.
|
||||
int intStatus() { return _status; }
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||||
|
||||
// Set the interrupt enable bits.
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||||
int clearInt(int i);
|
||||
void raiseInt(int i);
|
||||
|
||||
void initInt(IntrControl *i);
|
||||
void setInt(int bits);
|
||||
|
||||
void setPlatform(Platform *p);
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||||
//Ask the console if data is available
|
||||
bool dataAvailable() { return !rxbuf.empty(); }
|
||||
|
||||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
|
@ -31,7 +31,7 @@
|
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#include <vector>
|
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|
||||
#include "cpu/intr_control.hh"
|
||||
#include "dev/console.hh"
|
||||
#include "dev/simconsole.hh"
|
||||
#include "dev/etherdev.hh"
|
||||
#include "dev/ide_ctrl.hh"
|
||||
#include "dev/tlaser_clock.hh"
|
||||
|
|
|
@ -35,7 +35,6 @@
|
|||
#include <vector>
|
||||
|
||||
#include "base/trace.hh"
|
||||
#include "dev/console.hh"
|
||||
#include "dev/tsunami_cchip.hh"
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||||
#include "dev/tsunamireg.h"
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||||
#include "dev/tsunami.hh"
|
||||
|
|
|
@ -37,7 +37,6 @@
|
|||
#include <vector>
|
||||
|
||||
#include "base/trace.hh"
|
||||
#include "dev/console.hh"
|
||||
#include "dev/tsunami_io.hh"
|
||||
#include "dev/tsunami.hh"
|
||||
#include "mem/bus/bus.hh"
|
||||
|
|
|
@ -36,6 +36,7 @@
|
|||
#include "dev/io_device.hh"
|
||||
#include "base/range.hh"
|
||||
#include "dev/tsunami.hh"
|
||||
#include "sim/eventq.hh"
|
||||
|
||||
/** How often the RTC interrupts */
|
||||
static const int RTC_RATE = 1024;
|
||||
|
|
|
@ -1,308 +0,0 @@
|
|||
/* $Id$ */
|
||||
|
||||
/* @file
|
||||
* Tsunami UART
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 1998 by the Board of Trustees
|
||||
* of Leland Stanford Junior University.
|
||||
* Copyright (C) 1998 Digital Equipment Corporation
|
||||
*
|
||||
* This file is part of the SimOS distribution.
|
||||
* See LICENSE file for terms of the license.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
#include "base/inifile.hh"
|
||||
#include "base/str.hh" // for to_number
|
||||
#include "base/trace.hh"
|
||||
#include "dev/console.hh"
|
||||
#include "dev/tsunami_uart.hh"
|
||||
#include "mem/bus/bus.hh"
|
||||
#include "mem/bus/pio_interface.hh"
|
||||
#include "mem/bus/pio_interface_impl.hh"
|
||||
#include "mem/functional_mem/memory_control.hh"
|
||||
#include "sim/builder.hh"
|
||||
#include "targetarch/ev5.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
#define CONS_INT_TX 0x01 // interrupt enable / state bits
|
||||
#define CONS_INT_RX 0x02
|
||||
|
||||
|
||||
TsunamiUart::IntrEvent::IntrEvent(TsunamiUart *u)
|
||||
: Event(&mainEventQueue), uart(u)
|
||||
{
|
||||
DPRINTF(TsunamiUart, "UART Interrupt Event Initilizing\n");
|
||||
}
|
||||
|
||||
const char *
|
||||
TsunamiUart::IntrEvent::description()
|
||||
{
|
||||
return "tsunami uart interrupt delay event";
|
||||
}
|
||||
|
||||
void
|
||||
TsunamiUart::IntrEvent::process()
|
||||
{
|
||||
if (UART_IER_THRI & uart->IER) {
|
||||
DPRINTF(TsunamiUart, "UART InterEvent, interrupting\n");
|
||||
uart->cons->raiseInt(CONS_INT_TX);
|
||||
}
|
||||
else
|
||||
DPRINTF(TsunamiUart, "UART InterEvent, not interrupting\n");
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
TsunamiUart::IntrEvent::scheduleIntr()
|
||||
{
|
||||
DPRINTF(TsunamiUart, "Scheduling IER interrupt\n");
|
||||
if (!scheduled())
|
||||
schedule(curTick + 300);
|
||||
else
|
||||
reschedule(curTick + 300);
|
||||
}
|
||||
|
||||
|
||||
|
||||
TsunamiUart::TsunamiUart(const string &name, SimConsole *c,
|
||||
MemoryController *mmu, Addr a,
|
||||
HierParams *hier, Bus *bus)
|
||||
: PioDevice(name), addr(a), cons(c), status_store(0), valid_char(false),
|
||||
intrEvent(this)
|
||||
{
|
||||
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
||||
|
||||
if (bus) {
|
||||
pioInterface = newPioInterface(name, hier, bus, this,
|
||||
&TsunamiUart::cacheAccess);
|
||||
pioInterface->addAddrRange(addr, addr + size - 1);
|
||||
}
|
||||
|
||||
IER = 0;
|
||||
}
|
||||
|
||||
Fault
|
||||
TsunamiUart::read(MemReqPtr &req, uint8_t *data)
|
||||
{
|
||||
Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
|
||||
DPRINTF(TsunamiUart, " read register %#x\n", daddr);
|
||||
|
||||
switch (req->size) {
|
||||
case sizeof(uint64_t):
|
||||
*(uint64_t *)data = 0;
|
||||
break;
|
||||
case sizeof(uint32_t):
|
||||
*(uint32_t *)data = 0;
|
||||
break;
|
||||
case sizeof(uint16_t):
|
||||
*(uint16_t *)data = 0;
|
||||
break;
|
||||
case sizeof(uint8_t):
|
||||
*(uint8_t *)data = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
switch(daddr) {
|
||||
case 0x5: // Status Register
|
||||
{
|
||||
int status = cons->intStatus();
|
||||
if (!valid_char) {
|
||||
valid_char = cons->in(next_char);
|
||||
if (!valid_char)
|
||||
status &= ~CONS_INT_RX;
|
||||
} else {
|
||||
status |= CONS_INT_RX;
|
||||
}
|
||||
|
||||
if (status_store == 3) {
|
||||
// RR3 stuff? Don't really understand it, btw
|
||||
status_store = 0;
|
||||
if (status & CONS_INT_TX) {
|
||||
*data = (1 << 4);
|
||||
return No_Fault;
|
||||
} else if (status & CONS_INT_RX) {
|
||||
*data = (1 << 5);
|
||||
return No_Fault;
|
||||
} else {
|
||||
DPRINTF(TsunamiUart, "spurious read\n");
|
||||
return No_Fault;
|
||||
}
|
||||
} else {
|
||||
int reg = (1 << 2) | (1 << 5) | (1 << 6);
|
||||
if (status & CONS_INT_RX)
|
||||
reg |= (1 << 0);
|
||||
*data = reg;
|
||||
return No_Fault;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x0: // Data register (RX)
|
||||
DPRINTF(TsunamiUart, "read data register \'%c\' %#02x\n",
|
||||
isprint(next_char) ? next_char : ' ', next_char);
|
||||
|
||||
*data = next_char;
|
||||
valid_char = false;
|
||||
return No_Fault;
|
||||
|
||||
case 0x1: // Interrupt Enable Register
|
||||
// This is the lovely way linux checks there is actually a serial
|
||||
// port at the desired address
|
||||
if (IER == 0)
|
||||
*data = 0;
|
||||
else if (IER == 0x0F)
|
||||
*data = 0x0F;
|
||||
else
|
||||
*data = 0;
|
||||
return No_Fault;
|
||||
case 0x2:
|
||||
// High two bits need to be clear for an 8250 (simple) serial port
|
||||
// Low bit of IIR is 0 for a pending interrupt, 1 otherwise.
|
||||
int status = cons->intStatus();
|
||||
status = (status & 0x1) | (status >> 1);
|
||||
*data = (~status) & 0x1 ;
|
||||
return No_Fault;
|
||||
}
|
||||
*data = 0;
|
||||
// panic("%s: read daddr=%#x type=read *data=%#x\n", name(), daddr, *data);
|
||||
|
||||
return No_Fault;
|
||||
}
|
||||
|
||||
Fault
|
||||
TsunamiUart::write(MemReqPtr &req, const uint8_t *data)
|
||||
{
|
||||
Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
|
||||
|
||||
DPRINTF(TsunamiUart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
|
||||
|
||||
switch (daddr) {
|
||||
case 0x3:
|
||||
status_store = *data;
|
||||
switch (*data) {
|
||||
case 0x03: // going to read RR3
|
||||
return No_Fault;
|
||||
|
||||
case 0x28: // Ack of TX
|
||||
{
|
||||
if ((cons->intStatus() & CONS_INT_TX) == 0)
|
||||
panic("Ack of transmit, though there was no interrupt");
|
||||
|
||||
cons->clearInt(CONS_INT_TX);
|
||||
return No_Fault;
|
||||
}
|
||||
|
||||
case 0x00:
|
||||
case 0x01:
|
||||
case 0x12:
|
||||
// going to write data???
|
||||
return No_Fault;
|
||||
|
||||
default:
|
||||
DPRINTF(TsunamiUart, "writing status register %#x \n",
|
||||
*(uint8_t *)data);
|
||||
return No_Fault;
|
||||
}
|
||||
|
||||
case 0x0: // Data register (TX)
|
||||
char ourchar;
|
||||
ourchar = *(uint8_t *)data;
|
||||
if ((isprint(ourchar) || iscntrl(ourchar)) && (ourchar != 0x0C))
|
||||
cons->out(ourchar);
|
||||
cons->clearInt(CONS_INT_TX);
|
||||
intrEvent.scheduleIntr();
|
||||
return No_Fault;
|
||||
break;
|
||||
case 0x1: // IER
|
||||
IER = *(uint8_t*)data;
|
||||
DPRINTF(TsunamiUart, "writing to IER [%#x]\n", IER);
|
||||
if (UART_IER_THRI & IER)
|
||||
cons->raiseInt(CONS_INT_TX);
|
||||
else {
|
||||
cons->clearInt(CONS_INT_TX);
|
||||
if (intrEvent.scheduled())
|
||||
intrEvent.deschedule();
|
||||
}
|
||||
return No_Fault;
|
||||
break;
|
||||
case 0x4: // MCR
|
||||
DPRINTF(TsunamiUart, "writing to MCR %#x\n", *(uint8_t*)data);
|
||||
return No_Fault;
|
||||
|
||||
}
|
||||
|
||||
return No_Fault;
|
||||
}
|
||||
|
||||
Tick
|
||||
TsunamiUart::cacheAccess(MemReqPtr &req)
|
||||
{
|
||||
return curTick + 1000;
|
||||
}
|
||||
|
||||
void
|
||||
TsunamiUart::serialize(ostream &os)
|
||||
{
|
||||
SERIALIZE_SCALAR(status_store);
|
||||
SERIALIZE_SCALAR(next_char);
|
||||
SERIALIZE_SCALAR(valid_char);
|
||||
SERIALIZE_SCALAR(IER);
|
||||
Tick intrwhen;
|
||||
if (intrEvent.scheduled())
|
||||
intrwhen = intrEvent.when();
|
||||
else
|
||||
intrwhen = 0;
|
||||
SERIALIZE_SCALAR(intrwhen);
|
||||
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
TsunamiUart::unserialize(Checkpoint *cp, const std::string §ion)
|
||||
{
|
||||
UNSERIALIZE_SCALAR(status_store);
|
||||
UNSERIALIZE_SCALAR(next_char);
|
||||
UNSERIALIZE_SCALAR(valid_char);
|
||||
UNSERIALIZE_SCALAR(IER);
|
||||
Tick intrwhen;
|
||||
UNSERIALIZE_SCALAR(intrwhen);
|
||||
if (intrwhen != 0)
|
||||
intrEvent.schedule(intrwhen);
|
||||
|
||||
}
|
||||
|
||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiUart)
|
||||
|
||||
SimObjectParam<SimConsole *> console;
|
||||
SimObjectParam<MemoryController *> mmu;
|
||||
Param<Addr> addr;
|
||||
SimObjectParam<Bus*> io_bus;
|
||||
SimObjectParam<HierParams *> hier;
|
||||
|
||||
|
||||
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiUart)
|
||||
|
||||
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiUart)
|
||||
|
||||
INIT_PARAM(console, "The console"),
|
||||
INIT_PARAM(mmu, "Memory Controller"),
|
||||
INIT_PARAM(addr, "Device Address"),
|
||||
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
||||
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
||||
|
||||
END_INIT_SIM_OBJECT_PARAMS(TsunamiUart)
|
||||
|
||||
CREATE_SIM_OBJECT(TsunamiUart)
|
||||
{
|
||||
return new TsunamiUart(getInstanceName(), console, mmu, addr, hier, io_bus);
|
||||
}
|
||||
|
||||
REGISTER_SIM_OBJECT("TsunamiUart", TsunamiUart)
|
|
@ -140,7 +140,15 @@
|
|||
|
||||
|
||||
// UART Defines
|
||||
#define UART_IER_RDI 0x01
|
||||
#define UART_IER_THRI 0x02
|
||||
#define UART_IER_RLSI 0x04
|
||||
|
||||
|
||||
#define UART_LSR_TEMT 0x40
|
||||
#define UART_LSR_THRE 0x20
|
||||
#define UART_LSR_DR 0x01
|
||||
|
||||
#define UART_MCR_LOOP 0x10
|
||||
|
||||
#endif // __TSUNAMIREG_H__
|
||||
|
|
433
dev/uart.cc
Normal file
433
dev/uart.cc
Normal file
|
@ -0,0 +1,433 @@
|
|||
/*
|
||||
* Copyright (c) 2004 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* @file
|
||||
* Implements a 8250 UART
|
||||
*/
|
||||
|
||||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
#include "base/inifile.hh"
|
||||
#include "base/str.hh" // for to_number
|
||||
#include "base/trace.hh"
|
||||
#include "dev/simconsole.hh"
|
||||
#include "dev/uart.hh"
|
||||
#include "dev/platform.hh"
|
||||
#include "mem/bus/bus.hh"
|
||||
#include "mem/bus/pio_interface.hh"
|
||||
#include "mem/bus/pio_interface_impl.hh"
|
||||
#include "mem/functional_mem/memory_control.hh"
|
||||
#include "sim/builder.hh"
|
||||
#include "targetarch/ev5.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
Uart::IntrEvent::IntrEvent(Uart *u)
|
||||
: Event(&mainEventQueue), uart(u)
|
||||
{
|
||||
DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
|
||||
}
|
||||
|
||||
const char *
|
||||
Uart::IntrEvent::description()
|
||||
{
|
||||
return "uart interrupt delay event";
|
||||
}
|
||||
|
||||
void
|
||||
Uart::IntrEvent::process()
|
||||
{
|
||||
if (UART_IER_THRI & uart->IER) {
|
||||
DPRINTF(Uart, "UART InterEvent, interrupting\n");
|
||||
uart->platform->postConsoleInt();
|
||||
uart->status |= TX_INT;
|
||||
}
|
||||
else
|
||||
DPRINTF(Uart, "UART InterEvent, not interrupting\n");
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
Uart::IntrEvent::scheduleIntr()
|
||||
{
|
||||
DPRINTF(Uart, "Scheduling IER interrupt\n");
|
||||
if (!scheduled())
|
||||
schedule(curTick + 300);
|
||||
else
|
||||
reschedule(curTick + 300);
|
||||
}
|
||||
|
||||
Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
|
||||
Addr s, HierParams *hier, Bus *bus, Platform *p)
|
||||
: PioDevice(name), addr(a), size(s), cons(c), intrEvent(this), platform(p)
|
||||
{
|
||||
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
||||
|
||||
|
||||
if (bus) {
|
||||
pioInterface = newPioInterface(name, hier, bus, this,
|
||||
&Uart::cacheAccess);
|
||||
pioInterface->addAddrRange(addr, addr + size - 1);
|
||||
}
|
||||
|
||||
readAddr = 0;
|
||||
IER = 0;
|
||||
DLAB = 0;
|
||||
LCR = 0;
|
||||
MCR = 0;
|
||||
status = 0;
|
||||
|
||||
// set back pointers
|
||||
cons->uart = this;
|
||||
platform->uart = this;
|
||||
|
||||
}
|
||||
|
||||
Fault
|
||||
Uart::read(MemReqPtr &req, uint8_t *data)
|
||||
{
|
||||
Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
|
||||
DPRINTF(Uart, " read register %#x\n", daddr);
|
||||
|
||||
|
||||
|
||||
#ifdef ALPHA_TLASER
|
||||
|
||||
switch (req->size) {
|
||||
case sizeof(uint64_t):
|
||||
*(uint64_t *)data = 0;
|
||||
break;
|
||||
case sizeof(uint32_t):
|
||||
*(uint32_t *)data = 0;
|
||||
break;
|
||||
case sizeof(uint16_t):
|
||||
*(uint16_t *)data = 0;
|
||||
break;
|
||||
case sizeof(uint8_t):
|
||||
*(uint8_t *)data = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (daddr) {
|
||||
case 0x80: // Status Register
|
||||
if (readAddr == 3) {
|
||||
readAddr = 0;
|
||||
if (status & TX_INT)
|
||||
*data = (1 << 4);
|
||||
else if (status & RX_INT)
|
||||
*data = (1 << 5);
|
||||
else
|
||||
DPRINTF(Uart, "spurious read\n");
|
||||
|
||||
} else {
|
||||
*data = (1 << 2);
|
||||
if (status & RX_INT)
|
||||
*data |= (1 << 0);
|
||||
}
|
||||
break;
|
||||
|
||||
case 0xc0: // Data register (RX)
|
||||
if (!cons->dataAvailable())
|
||||
panic("No data to read");
|
||||
|
||||
cons->in(*data);
|
||||
|
||||
if (!cons->dataAvailable()) {
|
||||
platform->clearConsoleInt();
|
||||
status &= ~RX_INT;
|
||||
}
|
||||
|
||||
DPRINTF(Uart, "read data register \'%c\' %2x\n",
|
||||
isprint(*data) ? *data : ' ', *data);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
|
||||
|
||||
assert(req->size == 1);
|
||||
|
||||
switch (daddr) {
|
||||
case 0x0:
|
||||
if (!(LCR & 0x80)) { // read byte
|
||||
//assert(cons->dataAvailable());
|
||||
if (cons->dataAvailable())
|
||||
cons->in(*data);
|
||||
else {
|
||||
*(uint8_t*)data = 0;
|
||||
// A limited amount of these are ok.
|
||||
DPRINTF(Uart, "empty read of RX register\n");
|
||||
}
|
||||
|
||||
if (cons->dataAvailable())
|
||||
platform->postConsoleInt();
|
||||
else
|
||||
{
|
||||
status &= ~RX_INT;
|
||||
platform->clearConsoleInt();
|
||||
}
|
||||
} else { // dll divisor latch
|
||||
;
|
||||
}
|
||||
break;
|
||||
case 0x1:
|
||||
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
|
||||
*(uint8_t*)data = IER;
|
||||
} else { // DLM divisor latch MSB
|
||||
;
|
||||
}
|
||||
break;
|
||||
case 0x2: // Intr Identification Register (IIR)
|
||||
if (status)
|
||||
*(uint8_t*)data = 1;
|
||||
else
|
||||
*(uint8_t*)data = 0;
|
||||
break;
|
||||
case 0x3: // Line Control Register (LCR)
|
||||
*(uint8_t*)data = LCR;
|
||||
break;
|
||||
case 0x4: // Modem Control Register (MCR)
|
||||
break;
|
||||
case 0x5: // Line Status Register (LSR)
|
||||
uint8_t lsr;
|
||||
lsr = 0;
|
||||
// check if there are any bytes to be read
|
||||
if (cons->dataAvailable())
|
||||
lsr = UART_LSR_DR;
|
||||
lsr |= UART_LSR_TEMT | UART_LSR_THRE;
|
||||
*(uint8_t*)data = lsr;
|
||||
break;
|
||||
case 0x6: // Modem Status Register (MSR)
|
||||
*(uint8_t*)data = 0;
|
||||
break;
|
||||
case 0x7: // Scratch Register (SCR)
|
||||
*(uint8_t*)data = 0; // doesn't exist with at 8250.
|
||||
break;
|
||||
default:
|
||||
panic("Tried to access a UART port that doesn't exist\n");
|
||||
break;
|
||||
}
|
||||
|
||||
#endif
|
||||
return No_Fault;
|
||||
|
||||
}
|
||||
|
||||
Fault
|
||||
Uart::write(MemReqPtr &req, const uint8_t *data)
|
||||
{
|
||||
Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
|
||||
|
||||
DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
|
||||
|
||||
#ifdef ALPHA_TLASER
|
||||
|
||||
switch (daddr) {
|
||||
case 0x80:
|
||||
readAddr = *data;
|
||||
switch (*data) {
|
||||
case 0x28: // Ack of TX
|
||||
if ((status & TX_INT) == 0)
|
||||
panic("Ack of transmit, though there was no interrupt");
|
||||
|
||||
status &= ~TX_INT;
|
||||
platform->clearConsoleInt();
|
||||
break;
|
||||
case 0x00:
|
||||
case 0x01:
|
||||
case 0x03: // going to read RR3
|
||||
case 0x12:
|
||||
break;
|
||||
default:
|
||||
DPRINTF(Uart, "writing status register %#x \n",
|
||||
*(uint64_t *)data);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0xc0: // Data register (TX)
|
||||
cons->out(*(uint64_t *)data);
|
||||
platform->postConsoleInt();
|
||||
status |= TX_INT;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
switch (daddr) {
|
||||
case 0x0:
|
||||
if (!(LCR & 0x80)) { // write byte
|
||||
cons->out(*(uint64_t *)data);
|
||||
platform->clearConsoleInt();
|
||||
status &= ~TX_INT;
|
||||
if (UART_IER_THRI & IER)
|
||||
intrEvent.scheduleIntr();
|
||||
} else { // dll divisor latch
|
||||
;
|
||||
}
|
||||
break;
|
||||
case 0x1:
|
||||
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
|
||||
IER = *(uint8_t*)data;
|
||||
if ((UART_IER_THRI & IER) || ((UART_IER_RDI & IER) && cons->dataAvailable()))
|
||||
platform->postConsoleInt();
|
||||
else
|
||||
{
|
||||
platform->clearConsoleInt();
|
||||
if (intrEvent.scheduled())
|
||||
intrEvent.deschedule();
|
||||
|
||||
}
|
||||
if (!(UART_IER_THRI & IER))
|
||||
status &= ~TX_INT;
|
||||
if (!((UART_IER_RDI & IER) && cons->dataAvailable()))
|
||||
status &= ~RX_INT;
|
||||
} else { // DLM divisor latch MSB
|
||||
;
|
||||
}
|
||||
break;
|
||||
case 0x2: // FIFO Control Register (FCR)
|
||||
break;
|
||||
case 0x3: // Line Control Register (LCR)
|
||||
LCR = *(uint8_t*)data;
|
||||
break;
|
||||
case 0x4: // Modem Control Register (MCR)
|
||||
if (*(uint8_t*)data == (UART_MCR_LOOP | 0x0A))
|
||||
MCR = 0x9A;
|
||||
break;
|
||||
case 0x7: // Scratch Register (SCR)
|
||||
// We are emulating a 8250 so we don't have a scratch reg
|
||||
break;
|
||||
default:
|
||||
panic("Tried to access a UART port that doesn't exist\n");
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
return No_Fault;
|
||||
}
|
||||
|
||||
void
|
||||
Uart::dataAvailable()
|
||||
{
|
||||
#ifdef ALPHA_TLASER
|
||||
platform->postConsoleInt();
|
||||
status |= RX_INT;
|
||||
#else
|
||||
|
||||
// if the kernel wants an interrupt when we have data
|
||||
if (IER & UART_IER_RDI)
|
||||
{
|
||||
platform->postConsoleInt();
|
||||
status |= RX_INT;
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
Tick
|
||||
Uart::cacheAccess(MemReqPtr &req)
|
||||
{
|
||||
return curTick + 1000;
|
||||
}
|
||||
|
||||
void
|
||||
Uart::serialize(ostream &os)
|
||||
{
|
||||
#ifdef ALPHA_TLASER
|
||||
SERIALIZE_SCALAR(readAddr);
|
||||
SERIALIZE_SCALAR(status);
|
||||
#else
|
||||
SERIALIZE_SCALAR(status);
|
||||
SERIALIZE_SCALAR(IER);
|
||||
SERIALIZE_SCALAR(DLAB);
|
||||
SERIALIZE_SCALAR(LCR);
|
||||
SERIALIZE_SCALAR(MCR);
|
||||
Tick intrwhen;
|
||||
if (intrEvent.scheduled())
|
||||
intrwhen = intrEvent.when();
|
||||
else
|
||||
intrwhen = 0;
|
||||
SERIALIZE_SCALAR(intrwhen);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
Uart::unserialize(Checkpoint *cp, const std::string §ion)
|
||||
{
|
||||
#ifdef ALPHA_TLASER
|
||||
UNSERIALIZE_SCALAR(readAddr);
|
||||
UNSERIALIZE_SCALAR(status);
|
||||
#else
|
||||
UNSERIALIZE_SCALAR(status);
|
||||
UNSERIALIZE_SCALAR(IER);
|
||||
UNSERIALIZE_SCALAR(DLAB);
|
||||
UNSERIALIZE_SCALAR(LCR);
|
||||
UNSERIALIZE_SCALAR(MCR);
|
||||
Tick intrwhen;
|
||||
UNSERIALIZE_SCALAR(intrwhen);
|
||||
if (intrwhen != 0)
|
||||
intrEvent.schedule(intrwhen);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart)
|
||||
|
||||
SimObjectParam<SimConsole *> console;
|
||||
SimObjectParam<MemoryController *> mmu;
|
||||
SimObjectParam<Platform *> platform;
|
||||
Param<Addr> addr;
|
||||
Param<Addr> size;
|
||||
SimObjectParam<Bus*> io_bus;
|
||||
SimObjectParam<HierParams *> hier;
|
||||
|
||||
|
||||
END_DECLARE_SIM_OBJECT_PARAMS(Uart)
|
||||
|
||||
BEGIN_INIT_SIM_OBJECT_PARAMS(Uart)
|
||||
|
||||
INIT_PARAM(console, "The console"),
|
||||
INIT_PARAM(mmu, "Memory Controller"),
|
||||
INIT_PARAM(platform, "Pointer to platfrom"),
|
||||
INIT_PARAM(addr, "Device Address"),
|
||||
INIT_PARAM_DFLT(size, "Device size", 0x8),
|
||||
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
||||
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
||||
|
||||
END_INIT_SIM_OBJECT_PARAMS(Uart)
|
||||
|
||||
CREATE_SIM_OBJECT(Uart)
|
||||
{
|
||||
return new Uart(getInstanceName(), console, mmu, addr, size, hier, io_bus,
|
||||
platform);
|
||||
}
|
||||
|
||||
REGISTER_SIM_OBJECT("Uart", Uart)
|
|
@ -27,7 +27,7 @@
|
|||
*/
|
||||
|
||||
/* @file
|
||||
* Tsunami UART
|
||||
* Defines a 8250 UART
|
||||
*/
|
||||
|
||||
#ifndef __TSUNAMI_UART_HH__
|
||||
|
@ -38,45 +38,60 @@
|
|||
#include "dev/io_device.hh"
|
||||
|
||||
class SimConsole;
|
||||
class Platform;
|
||||
|
||||
/*
|
||||
* Tsunami UART
|
||||
*/
|
||||
class TsunamiUart : public PioDevice
|
||||
const int RX_INT = 0x1;
|
||||
const int TX_INT = 0x2;
|
||||
|
||||
|
||||
class Uart : public PioDevice
|
||||
{
|
||||
|
||||
private:
|
||||
Addr addr;
|
||||
static const Addr size = 0x8;
|
||||
Addr size;
|
||||
SimConsole *cons;
|
||||
|
||||
|
||||
protected:
|
||||
SimConsole *cons;
|
||||
int status_store;
|
||||
uint8_t next_char;
|
||||
bool valid_char;
|
||||
uint8_t IER;
|
||||
int readAddr; // tlaser only
|
||||
uint8_t IER, DLAB, LCR, MCR;
|
||||
int status;
|
||||
|
||||
class IntrEvent : public Event
|
||||
{
|
||||
protected:
|
||||
TsunamiUart *uart;
|
||||
Uart *uart;
|
||||
public:
|
||||
IntrEvent(TsunamiUart *u);
|
||||
IntrEvent(Uart *u);
|
||||
virtual void process();
|
||||
virtual const char *description();
|
||||
void scheduleIntr();
|
||||
};
|
||||
|
||||
IntrEvent intrEvent;
|
||||
Platform *platform;
|
||||
|
||||
public:
|
||||
TsunamiUart(const string &name, SimConsole *c, MemoryController *mmu,
|
||||
Addr a, HierParams *hier, Bus *bus);
|
||||
Uart(const string &name, SimConsole *c, MemoryController *mmu,
|
||||
Addr a, Addr s, HierParams *hier, Bus *bus, Platform *p);
|
||||
|
||||
Fault read(MemReqPtr &req, uint8_t *data);
|
||||
Fault write(MemReqPtr &req, const uint8_t *data);
|
||||
|
||||
|
||||
/**
|
||||
* Inform the uart that there is data available.
|
||||
*/
|
||||
void dataAvailable();
|
||||
|
||||
|
||||
/**
|
||||
* Return if we have an interrupt pending
|
||||
* @return interrupt status
|
||||
*/
|
||||
bool intStatus() { return status ? true : false; }
|
||||
|
||||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
|
Loading…
Reference in a new issue