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This commit is contained in:
Steve Reinhardt 2016-06-12 20:02:49 -04:00
parent 3724fb15fa
commit 54aeb1a187
20 changed files with 1424 additions and 686 deletions
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20
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
View file

@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a boot_osflags=a
cache_line_size=64 cache_line_size=64
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
exit_on_work_items=false exit_on_work_items=false
init_param=0 init_param=0
@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false mmap_using_noreserve=false
multi_thread=false multi_thread=false
num_work_ids=16 num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile= readfile=
symbolfile= symbolfile=
thermal_components= thermal_components=
@ -55,6 +60,7 @@ branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=0 cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -71,6 +77,10 @@ max_insts_any_thread=500000
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0 profile=0
progress_interval=0 progress_interval=0
simpoint_start_insts= simpoint_start_insts=
@ -140,10 +150,15 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
forward_latency=4 forward_latency=4
frontend_latency=3 frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=Null
snoop_response_latency=4 snoop_response_latency=4
@ -158,11 +173,16 @@ type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727 range=0:134217727
port=system.membus.master[0] port=system.membus.master[0]

68
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
View file

@ -6,6 +6,24 @@
"mmap_using_noreserve": false, "mmap_using_noreserve": false,
"kernel_addr_check": true, "kernel_addr_check": true,
"membus": { "membus": {
"point_of_coherency": true,
"system": "system",
"response_latency": 2,
"cxx_class": "CoherentXBar",
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"width": 16,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 3,
"slave": { "slave": {
"peer": [ "peer": [
"system.system_port", "system.system_port",
@ -14,35 +32,23 @@
], ],
"role": "SLAVE" "role": "SLAVE"
}, },
"name": "membus", "p_state_clk_gate_min": 1000,
"point_of_coherency": true,
"snoop_filter": null, "snoop_filter": null,
"forward_latency": 4, "power_model": null,
"clk_domain": "system.clk_domain",
"system": "system",
"width": 16,
"eventq_index": 0,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"response_latency": 2,
"cxx_class": "CoherentXBar",
"path": "system.membus", "path": "system.membus",
"snoop_response_latency": 4, "snoop_response_latency": 4,
"type": "CoherentXBar", "name": "membus",
"use_default_range": false, "p_state_clk_gate_bins": 20,
"frontend_latency": 3 "use_default_range": false
}, },
"symbolfile": "", "symbolfile": "",
"readfile": "", "readfile": "",
"thermal_model": null, "thermal_model": null,
"cxx_class": "System", "cxx_class": "System",
"work_begin_cpu_id_exit": -1,
"load_offset": 0, "load_offset": 0,
"work_begin_exit_count": 0, "work_begin_exit_count": 0,
"work_end_ckpt_count": 0, "p_state_clk_gate_min": 1000,
"memories": [ "memories": [
"system.physmem" "system.physmem"
], ],
@ -62,7 +68,8 @@
}, },
"mem_ranges": [], "mem_ranges": [],
"eventq_index": 0, "eventq_index": 0,
"work_begin_cpu_id_exit": -1, "default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"dvfs_handler": { "dvfs_handler": {
"enable": false, "enable": false,
"name": "dvfs_handler", "name": "dvfs_handler",
@ -88,16 +95,25 @@
}, },
"cache_line_size": 64, "cache_line_size": 64,
"boot_osflags": "a", "boot_osflags": "a",
"system_port": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"physmem": { "physmem": {
"range": "0:134217727", "range": "0:134217727",
"latency": 30000, "latency": 30000,
"name": "physmem", "name": "physmem",
"p_state_clk_gate_min": 1000,
"eventq_index": 0, "eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.clk_domain", "clk_domain": "system.clk_domain",
"power_model": null,
"latency_var": 0, "latency_var": 0,
"bandwidth": "73.000000", "bandwidth": "73.000000",
"conf_table_reported": true, "conf_table_reported": true,
"cxx_class": "SimpleMemory", "cxx_class": "SimpleMemory",
"p_state_clk_gate_max": 1000000000000,
"path": "system.physmem", "path": "system.physmem",
"null": false, "null": false,
"type": "SimpleMemory", "type": "SimpleMemory",
@ -107,6 +123,7 @@
}, },
"in_addr_map": true "in_addr_map": true
}, },
"power_model": null,
"work_cpus_ckpt_count": 0, "work_cpus_ckpt_count": 0,
"thermal_components": [], "thermal_components": [],
"path": "system", "path": "system",
@ -123,13 +140,11 @@
"type": "SrcClockDomain", "type": "SrcClockDomain",
"domain_id": -1 "domain_id": -1
}, },
"work_end_ckpt_count": 0,
"mem_mode": "atomic", "mem_mode": "atomic",
"name": "system", "name": "system",
"init_param": 0, "init_param": 0,
"system_port": { "p_state_clk_gate_bins": 20,
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"load_addr_mask": 1099511627775, "load_addr_mask": 1099511627775,
"cpu": [ "cpu": [
{ {
@ -155,6 +170,8 @@
"width": 1, "width": 1,
"checker": null, "checker": null,
"eventq_index": 0, "eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"do_quiesce": true, "do_quiesce": true,
"type": "AtomicSimpleCPU", "type": "AtomicSimpleCPU",
"fastmem": false, "fastmem": false,
@ -163,6 +180,8 @@
"peer": "system.membus.slave[1]", "peer": "system.membus.slave[1]",
"role": "MASTER" "role": "MASTER"
}, },
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"interrupts": [ "interrupts": [
{ {
"eventq_index": 0, "eventq_index": 0,
@ -177,6 +196,7 @@
"role": "MASTER" "role": "MASTER"
}, },
"socket_id": 0, "socket_id": 0,
"power_model": null,
"max_insts_all_threads": 0, "max_insts_all_threads": 0,
"path": "system.cpu", "path": "system.cpu",
"max_loads_any_thread": 0, "max_loads_any_thread": 0,

1
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
View file

@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything

6
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simp
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 5 2016 19:50:43 gem5 compiled Jun 12 2016 19:14:13
gem5 started Jun 5 2016 20:05:34 gem5 started Jun 12 2016 19:14:37
gem5 executing on zizzer, pid 54386 gem5 executing on zizzer, pid 29746
command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/20.eio-short/alpha/eio/simple-atomic command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second

14
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
View file

@ -4,15 +4,16 @@ sim_seconds 0.000250 # Nu
sim_ticks 250015500 # Number of ticks simulated sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1086021 # Simulator instruction rate (inst/s) host_inst_rate 1177687 # Simulator instruction rate (inst/s)
host_op_rate 1085950 # Simulator op (including micro ops) rate (op/s) host_op_rate 1177628 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 542974724 # Simulator tick rate (ticks/s) host_tick_rate 588821738 # Simulator tick rate (ticks/s)
host_mem_usage 223156 # Number of bytes of host memory used host_mem_usage 224108 # Number of bytes of host memory used
host_seconds 0.46 # Real time elapsed on the host host_seconds 0.42 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated sim_ops 500001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 2000076 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 2000076 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 872600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 872600 # Number of bytes read from this memory
system.physmem.bytes_read::total 2872676 # Number of bytes read from this memory system.physmem.bytes_read::total 2872676 # Number of bytes read from this memory
@ -35,6 +36,7 @@ system.physmem.bw_write::total 1670144451 # Wr
system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 250015500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 500032 # number of cpu cycles simulated system.cpu.numCycles 500032 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 500019 # Class of executed instruction system.cpu.op_class::total 500019 # Class of executed instruction
system.membus.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 624454 # Transaction distribution system.membus.trans_dist::ReadReq 624454 # Transaction distribution
system.membus.trans_dist::ReadResp 624454 # Transaction distribution system.membus.trans_dist::ReadResp 624454 # Transaction distribution
system.membus.trans_dist::WriteReq 56340 # Transaction distribution system.membus.trans_dist::WriteReq 56340 # Transaction distribution

55
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
View file

@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a boot_osflags=a
cache_line_size=64 cache_line_size=64
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
exit_on_work_items=false exit_on_work_items=false
init_param=0 init_param=0
@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false mmap_using_noreserve=false
multi_thread=false multi_thread=false
num_work_ids=16 num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile= readfile=
symbolfile= symbolfile=
thermal_components= thermal_components=
@ -55,6 +60,7 @@ branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=0 cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -70,6 +76,10 @@ max_insts_any_thread=500000
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0 profile=0
progress_interval=0 progress_interval=0
simpoint_start_insts= simpoint_start_insts=
@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -112,8 +127,13 @@ type=LRU
assoc=2 assoc=2
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=262144 size=262144
@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
assoc=2 assoc=2
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -153,8 +178,13 @@ type=LRU
assoc=2 assoc=2
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=131072 size=131072
@ -179,12 +209,17 @@ addr_ranges=0:18446744073709551615
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=20 hit_latency=20
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
mshrs=20 mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=20 response_latency=20
@ -203,8 +238,13 @@ type=LRU
assoc=8 assoc=8
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=20 hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=2097152 size=2097152
@ -212,10 +252,15 @@ size=2097152
type=CoherentXBar type=CoherentXBar
children=snoop_filter children=snoop_filter
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
forward_latency=0 forward_latency=0
frontend_latency=1 frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false point_of_coherency=false
power_model=Null
response_latency=1 response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1 snoop_response_latency=1
@ -268,10 +313,15 @@ transition_latency=100000000
[system.membus] [system.membus]
type=CoherentXBar type=CoherentXBar
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
forward_latency=4 forward_latency=4
frontend_latency=3 frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=Null
snoop_response_latency=4 snoop_response_latency=4
@ -286,11 +336,16 @@ type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727 range=0:134217727
port=system.membus.master[0] port=system.membus.master[0]

255
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json
View file

@ -6,6 +6,24 @@
"mmap_using_noreserve": false, "mmap_using_noreserve": false,
"kernel_addr_check": true, "kernel_addr_check": true,
"membus": { "membus": {
"point_of_coherency": true,
"system": "system",
"response_latency": 2,
"cxx_class": "CoherentXBar",
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"width": 16,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 3,
"slave": { "slave": {
"peer": [ "peer": [
"system.system_port", "system.system_port",
@ -13,35 +31,23 @@
], ],
"role": "SLAVE" "role": "SLAVE"
}, },
"name": "membus", "p_state_clk_gate_min": 1000,
"point_of_coherency": true,
"snoop_filter": null, "snoop_filter": null,
"forward_latency": 4, "power_model": null,
"clk_domain": "system.clk_domain",
"system": "system",
"width": 16,
"eventq_index": 0,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"response_latency": 2,
"cxx_class": "CoherentXBar",
"path": "system.membus", "path": "system.membus",
"snoop_response_latency": 4, "snoop_response_latency": 4,
"type": "CoherentXBar", "name": "membus",
"use_default_range": false, "p_state_clk_gate_bins": 20,
"frontend_latency": 3 "use_default_range": false
}, },
"symbolfile": "", "symbolfile": "",
"readfile": "", "readfile": "",
"thermal_model": null, "thermal_model": null,
"cxx_class": "System", "cxx_class": "System",
"work_begin_cpu_id_exit": -1,
"load_offset": 0, "load_offset": 0,
"work_begin_exit_count": 0, "work_begin_exit_count": 0,
"work_end_ckpt_count": 0, "p_state_clk_gate_min": 1000,
"memories": [ "memories": [
"system.physmem" "system.physmem"
], ],
@ -61,7 +67,8 @@
}, },
"mem_ranges": [], "mem_ranges": [],
"eventq_index": 0, "eventq_index": 0,
"work_begin_cpu_id_exit": -1, "default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"dvfs_handler": { "dvfs_handler": {
"enable": false, "enable": false,
"name": "dvfs_handler", "name": "dvfs_handler",
@ -87,16 +94,25 @@
}, },
"cache_line_size": 64, "cache_line_size": 64,
"boot_osflags": "a", "boot_osflags": "a",
"system_port": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"physmem": { "physmem": {
"range": "0:134217727", "range": "0:134217727",
"latency": 30000, "latency": 30000,
"name": "physmem", "name": "physmem",
"p_state_clk_gate_min": 1000,
"eventq_index": 0, "eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.clk_domain", "clk_domain": "system.clk_domain",
"power_model": null,
"latency_var": 0, "latency_var": 0,
"bandwidth": "73.000000", "bandwidth": "73.000000",
"conf_table_reported": true, "conf_table_reported": true,
"cxx_class": "SimpleMemory", "cxx_class": "SimpleMemory",
"p_state_clk_gate_max": 1000000000000,
"path": "system.physmem", "path": "system.physmem",
"null": false, "null": false,
"type": "SimpleMemory", "type": "SimpleMemory",
@ -106,6 +122,7 @@
}, },
"in_addr_map": true "in_addr_map": true
}, },
"power_model": null,
"work_cpus_ckpt_count": 0, "work_cpus_ckpt_count": 0,
"thermal_components": [], "thermal_components": [],
"path": "system", "path": "system",
@ -122,13 +139,11 @@
"type": "SrcClockDomain", "type": "SrcClockDomain",
"domain_id": -1 "domain_id": -1
}, },
"work_end_ckpt_count": 0,
"mem_mode": "timing", "mem_mode": "timing",
"name": "system", "name": "system",
"init_param": 0, "init_param": 0,
"system_port": { "p_state_clk_gate_bins": 20,
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"load_addr_mask": 1099511627775, "load_addr_mask": 1099511627775,
"cpu": [ "cpu": [
{ {
@ -143,6 +158,64 @@
"size": 48 "size": 48
}, },
"system": "system", "system": "system",
"icache": {
"cpu_side": {
"peer": "system.cpu.icache_port",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 2,
"cxx_class": "Cache",
"size": 131072,
"tags": {
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 2,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.icache.tags",
"hit_latency": 2,
"block_size": 64,
"type": "LRU",
"size": 131072
},
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.cpu.toL2Bus.slave[0]",
"role": "MASTER"
},
"type": "Cache",
"writeback_clean": true,
"p_state_clk_gate_min": 1000,
"hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615"
],
"is_read_only": true,
"prefetch_on_access": false,
"path": "system.cpu.icache",
"mshrs": 4,
"name": "icache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 2
},
"function_trace": false, "function_trace": false,
"do_checkpoint_insts": true, "do_checkpoint_insts": true,
"cxx_class": "TimingSimpleCPU", "cxx_class": "TimingSimpleCPU",
@ -152,7 +225,27 @@
"cpu_id": 0, "cpu_id": 0,
"checker": null, "checker": null,
"eventq_index": 0, "eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"toL2Bus": { "toL2Bus": {
"point_of_coherency": false,
"system": "system",
"response_latency": 1,
"cxx_class": "CoherentXBar",
"forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
"width": 32,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.cpu.l2cache.cpu_side"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 1,
"slave": { "slave": {
"peer": [ "peer": [
"system.cpu.icache.mem_side", "system.cpu.icache.mem_side",
@ -160,8 +253,7 @@
], ],
"role": "SLAVE" "role": "SLAVE"
}, },
"name": "toL2Bus", "p_state_clk_gate_min": 1000,
"point_of_coherency": false,
"snoop_filter": { "snoop_filter": {
"name": "snoop_filter", "name": "snoop_filter",
"system": "system", "system": "system",
@ -172,24 +264,12 @@
"type": "SnoopFilter", "type": "SnoopFilter",
"lookup_latency": 0 "lookup_latency": 0
}, },
"forward_latency": 0, "power_model": null,
"clk_domain": "system.cpu_clk_domain",
"system": "system",
"width": 32,
"eventq_index": 0,
"master": {
"peer": [
"system.cpu.l2cache.cpu_side"
],
"role": "MASTER"
},
"response_latency": 1,
"cxx_class": "CoherentXBar",
"path": "system.cpu.toL2Bus", "path": "system.cpu.toL2Bus",
"snoop_response_latency": 1, "snoop_response_latency": 1,
"type": "CoherentXBar", "name": "toL2Bus",
"use_default_range": false, "p_state_clk_gate_bins": 20,
"frontend_latency": 1 "use_default_range": false
}, },
"do_quiesce": true, "do_quiesce": true,
"type": "TimingSimpleCPU", "type": "TimingSimpleCPU",
@ -198,54 +278,8 @@
"peer": "system.cpu.icache.cpu_side", "peer": "system.cpu.icache.cpu_side",
"role": "MASTER" "role": "MASTER"
}, },
"icache": { "p_state_clk_gate_bins": 20,
"cpu_side": { "p_state_clk_gate_min": 1000,
"peer": "system.cpu.icache_port",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"clk_domain": "system.cpu_clk_domain",
"write_buffers": 8,
"response_latency": 2,
"cxx_class": "Cache",
"size": 131072,
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 2,
"clk_domain": "system.cpu_clk_domain",
"sequential_access": false,
"assoc": 2,
"cxx_class": "LRU",
"path": "system.cpu.icache.tags",
"block_size": 64,
"type": "LRU",
"size": 131072
},
"system": "system",
"max_miss_count": 0,
"eventq_index": 0,
"mem_side": {
"peer": "system.cpu.toL2Bus.slave[0]",
"role": "MASTER"
},
"type": "Cache",
"writeback_clean": true,
"hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
],
"is_read_only": true,
"prefetch_on_access": false,
"path": "system.cpu.icache",
"name": "icache",
"mshrs": 4,
"sequential_access": false,
"assoc": 2
},
"interrupts": [ "interrupts": [
{ {
"eventq_index": 0, "eventq_index": 0,
@ -260,6 +294,7 @@
"role": "MASTER" "role": "MASTER"
}, },
"socket_id": 0, "socket_id": 0,
"power_model": null,
"max_insts_all_threads": 0, "max_insts_all_threads": 0,
"l2cache": { "l2cache": {
"cpu_side": { "cpu_side": {
@ -268,44 +303,54 @@
}, },
"clusivity": "mostly_incl", "clusivity": "mostly_incl",
"prefetcher": null, "prefetcher": null,
"clk_domain": "system.cpu_clk_domain", "system": "system",
"write_buffers": 8, "write_buffers": 8,
"response_latency": 20, "response_latency": 20,
"cxx_class": "Cache", "cxx_class": "Cache",
"size": 2097152, "size": 2097152,
"tags": { "tags": {
"name": "tags", "name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0, "eventq_index": 0,
"hit_latency": 20, "p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain", "clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false, "sequential_access": false,
"assoc": 8, "assoc": 8,
"cxx_class": "LRU", "cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.l2cache.tags", "path": "system.cpu.l2cache.tags",
"hit_latency": 20,
"block_size": 64, "block_size": 64,
"type": "LRU", "type": "LRU",
"size": 2097152 "size": 2097152
}, },
"system": "system", "clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0, "max_miss_count": 0,
"eventq_index": 0, "eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": { "mem_side": {
"peer": "system.membus.slave[1]", "peer": "system.membus.slave[1]",
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"writeback_clean": false, "writeback_clean": false,
"p_state_clk_gate_min": 1000,
"hit_latency": 20, "hit_latency": 20,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 12, "tgts_per_mshr": 12,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
"is_read_only": false, "is_read_only": false,
"prefetch_on_access": false, "prefetch_on_access": false,
"path": "system.cpu.l2cache", "path": "system.cpu.l2cache",
"name": "l2cache",
"mshrs": 20, "mshrs": 20,
"name": "l2cache",
"p_state_clk_gate_bins": 20,
"sequential_access": false, "sequential_access": false,
"assoc": 8 "assoc": 8
}, },
@ -350,44 +395,54 @@
}, },
"clusivity": "mostly_incl", "clusivity": "mostly_incl",
"prefetcher": null, "prefetcher": null,
"clk_domain": "system.cpu_clk_domain", "system": "system",
"write_buffers": 8, "write_buffers": 8,
"response_latency": 2, "response_latency": 2,
"cxx_class": "Cache", "cxx_class": "Cache",
"size": 262144, "size": 262144,
"tags": { "tags": {
"name": "tags", "name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0, "eventq_index": 0,
"hit_latency": 2, "p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain", "clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false, "sequential_access": false,
"assoc": 2, "assoc": 2,
"cxx_class": "LRU", "cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.dcache.tags", "path": "system.cpu.dcache.tags",
"hit_latency": 2,
"block_size": 64, "block_size": 64,
"type": "LRU", "type": "LRU",
"size": 262144 "size": 262144
}, },
"system": "system", "clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0, "max_miss_count": 0,
"eventq_index": 0, "eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": { "mem_side": {
"peer": "system.cpu.toL2Bus.slave[1]", "peer": "system.cpu.toL2Bus.slave[1]",
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"writeback_clean": false, "writeback_clean": false,
"p_state_clk_gate_min": 1000,
"hit_latency": 2, "hit_latency": 2,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20, "tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
"is_read_only": false, "is_read_only": false,
"prefetch_on_access": false, "prefetch_on_access": false,
"path": "system.cpu.dcache", "path": "system.cpu.dcache",
"name": "dcache",
"mshrs": 4, "mshrs": 4,
"name": "dcache",
"p_state_clk_gate_bins": 20,
"sequential_access": false, "sequential_access": false,
"assoc": 2 "assoc": 2
}, },

1
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
View file

@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything

6
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simp
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 5 2016 19:50:43 gem5 compiled Jun 12 2016 19:14:13
gem5 started Jun 5 2016 20:04:44 gem5 started Jun 12 2016 19:14:35
gem5 executing on zizzer, pid 54380 gem5 executing on zizzer, pid 29706
command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/20.eio-short/alpha/eio/simple-timing command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second

21
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
View file

@ -4,15 +4,16 @@ sim_seconds 0.000733 # Nu
sim_ticks 733071500 # Number of ticks simulated sim_ticks 733071500 # Number of ticks simulated
final_tick 733071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 733071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 528622 # Simulator instruction rate (inst/s) host_inst_rate 714823 # Simulator instruction rate (inst/s)
host_op_rate 528606 # Simulator op (including micro ops) rate (op/s) host_op_rate 714800 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 774988448 # Simulator tick rate (ticks/s) host_tick_rate 1047966347 # Simulator tick rate (ticks/s)
host_mem_usage 232700 # Number of bytes of host memory used host_mem_usage 233664 # Number of bytes of host memory used
host_seconds 0.95 # Real time elapsed on the host host_seconds 0.70 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated sim_ops 500001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 29056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 29056 # Number of bytes read from this memory
system.physmem.bytes_read::total 54848 # Number of bytes read from this memory system.physmem.bytes_read::total 54848 # Number of bytes read from this memory
@ -29,6 +30,7 @@ system.physmem.bw_inst_read::total 35183471 # In
system.physmem.bw_total::cpu.inst 35183471 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 35183471 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 39635970 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 39635970 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 74819441 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 74819441 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
@ -63,6 +65,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 733071500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1466143 # number of cpu cycles simulated system.cpu.numCycles 1466143 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@ -121,6 +124,7 @@ system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 500019 # Class of executed instruction system.cpu.op_class::total 500019 # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 286.668758 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 286.668758 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
@ -137,6 +141,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 426
system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
@ -223,6 +228,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 264.585152 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 264.585152 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
@ -237,6 +243,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 403
system.cpu.icache.tags.occ_task_id_percent::1024 0.196777 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.196777 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1000443 # Number of tag accesses system.cpu.icache.tags.tag_accesses 1000443 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1000443 # Number of data accesses system.cpu.icache.tags.data_accesses 1000443 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
@ -303,6 +310,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61001.240695
system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 480.680597 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 480.680597 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
@ -321,6 +329,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 714
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021912 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021912 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 7713 # Number of tag accesses system.cpu.l2cache.tags.tag_accesses 7713 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 7713 # Number of data accesses system.cpu.l2cache.tags.data_accesses 7713 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 403 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 403 # number of ReadCleanReq misses
@ -441,6 +450,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution
@ -470,6 +480,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 604500 # La
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 718 # Transaction distribution system.membus.trans_dist::ReadResp 718 # Transaction distribution
system.membus.trans_dist::ReadExReq 139 # Transaction distribution system.membus.trans_dist::ReadExReq 139 # Transaction distribution
system.membus.trans_dist::ReadExResp 139 # Transaction distribution system.membus.trans_dist::ReadExResp 139 # Transaction distribution

130
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
View file

@ -14,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus p
boot_osflags=a boot_osflags=a
cache_line_size=64 cache_line_size=64
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
exit_on_work_items=false exit_on_work_items=false
init_param=0 init_param=0
@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false mmap_using_noreserve=false
multi_thread=false multi_thread=false
num_work_ids=16 num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile= readfile=
symbolfile= symbolfile=
thermal_components= thermal_components=
@ -55,6 +60,7 @@ branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=0 cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -71,6 +77,10 @@ max_insts_any_thread=500000
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0 profile=0
progress_interval=0 progress_interval=0
simpoint_start_insts= simpoint_start_insts=
@ -92,12 +102,17 @@ addr_ranges=0:18446744073709551615
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -116,8 +131,13 @@ type=LRU
assoc=4 assoc=4
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -133,12 +153,17 @@ addr_ranges=0:18446744073709551615
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -157,8 +182,13 @@ type=LRU
assoc=1 assoc=1
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -200,6 +230,7 @@ branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=1 cpu_id=1
default_p_state=UNDEFINED
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -216,6 +247,10 @@ max_insts_any_thread=500000
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0 profile=0
progress_interval=0 progress_interval=0
simpoint_start_insts= simpoint_start_insts=
@ -237,12 +272,17 @@ addr_ranges=0:18446744073709551615
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -261,8 +301,13 @@ type=LRU
assoc=4 assoc=4
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -278,12 +323,17 @@ addr_ranges=0:18446744073709551615
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -302,8 +352,13 @@ type=LRU
assoc=1 assoc=1
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -345,6 +400,7 @@ branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=2 cpu_id=2
default_p_state=UNDEFINED
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -361,6 +417,10 @@ max_insts_any_thread=500000
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0 profile=0
progress_interval=0 progress_interval=0
simpoint_start_insts= simpoint_start_insts=
@ -382,12 +442,17 @@ addr_ranges=0:18446744073709551615
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -406,8 +471,13 @@ type=LRU
assoc=4 assoc=4
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -423,12 +493,17 @@ addr_ranges=0:18446744073709551615
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -447,8 +522,13 @@ type=LRU
assoc=1 assoc=1
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -490,6 +570,7 @@ branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=3 cpu_id=3
default_p_state=UNDEFINED
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -506,6 +587,10 @@ max_insts_any_thread=500000
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0 profile=0
progress_interval=0 progress_interval=0
simpoint_start_insts= simpoint_start_insts=
@ -527,12 +612,17 @@ addr_ranges=0:18446744073709551615
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -551,8 +641,13 @@ type=LRU
assoc=4 assoc=4
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -568,12 +663,17 @@ addr_ranges=0:18446744073709551615
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -592,8 +692,13 @@ type=LRU
assoc=1 assoc=1
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -651,12 +756,17 @@ addr_ranges=0:18446744073709551615
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=20 hit_latency=20
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
mshrs=20 mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=20 response_latency=20
@ -675,8 +785,13 @@ type=LRU
assoc=8 assoc=8
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=20 hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=4194304 size=4194304
@ -684,10 +799,15 @@ size=4194304
type=CoherentXBar type=CoherentXBar
children=snoop_filter children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
forward_latency=4 forward_latency=4
frontend_latency=3 frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null
response_latency=2 response_latency=2
snoop_filter=system.membus.snoop_filter snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
@ -709,11 +829,16 @@ type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727 range=0:134217727
port=system.membus.master[0] port=system.membus.master[0]
@ -721,10 +846,15 @@ port=system.membus.master[0]
type=CoherentXBar type=CoherentXBar
children=snoop_filter children=snoop_filter
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
forward_latency=0 forward_latency=0
frontend_latency=1 frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false point_of_coherency=false
power_model=Null
response_latency=1 response_latency=1
snoop_filter=system.toL2Bus.snoop_filter snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1 snoop_response_latency=1

648
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json
View file

File diff suppressed because it is too large Load diff

11
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
View file

@ -1,11 +1,10 @@
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything
gzip: stdout: Broken pipe gzip: stdout: Broken pipe
stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe

6
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 5 2016 19:50:43 gem5 compiled Jun 12 2016 19:14:13
gem5 started Jun 5 2016 19:51:07 gem5 started Jun 12 2016 19:14:35
gem5 executing on zizzer, pid 54308 gem5 executing on zizzer, pid 29714
command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/30.eio-mp/alpha/eio/simple-atomic-mp command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second

36
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
View file

@ -4,15 +4,16 @@ sim_seconds 0.000250 # Nu
sim_ticks 250015500 # Number of ticks simulated sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1005954 # Simulator instruction rate (inst/s) host_inst_rate 1104001 # Simulator instruction rate (inst/s)
host_op_rate 1005938 # Simulator op (including micro ops) rate (op/s) host_op_rate 1103987 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 125747952 # Simulator tick rate (ticks/s) host_tick_rate 138004981 # Simulator tick rate (ticks/s)
host_mem_usage 245580 # Number of bytes of host memory used host_mem_usage 246580 # Number of bytes of host memory used
host_seconds 1.99 # Real time elapsed on the host host_seconds 1.81 # Real time elapsed on the host
sim_insts 2000004 # Number of instructions simulated sim_insts 2000004 # Number of instructions simulated
sim_ops 2000004 # Number of ops (including micro ops) simulated sim_ops 2000004 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
@ -59,6 +60,7 @@ system.physmem.bw_total::cpu2.data 116216795 # To
system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_misses 0 # ITB misses
@ -93,6 +95,7 @@ system.cpu0.itb.data_misses 0 # DT
system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.workload.num_syscalls 18 # Number of system calls system.cpu0.workload.num_syscalls 18 # Number of system calls
system.cpu0.pwrStateResidencyTicks::ON 250015500 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 500032 # number of cpu cycles simulated system.cpu0.numCycles 500032 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
@ -151,6 +154,7 @@ system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 500019 # Class of executed instruction system.cpu0.op_class::total 500019 # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 61 # number of replacements system.cpu0.dcache.tags.replacements 61 # number of replacements
system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
@ -167,6 +171,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 248
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
@ -207,6 +212,7 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu0.dcache.writebacks::total 29 # number of writebacks system.cpu0.dcache.writebacks::total 29 # number of writebacks
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 152 # number of replacements system.cpu0.icache.tags.replacements 152 # number of replacements
system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks. system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks.
@ -222,6 +228,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 121
system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 500482 # Number of tag accesses system.cpu0.icache.tags.tag_accesses 500482 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 500482 # Number of data accesses system.cpu0.icache.tags.data_accesses 500482 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits
@ -287,6 +294,7 @@ system.cpu1.itb.data_misses 0 # DT
system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.workload.num_syscalls 18 # Number of system calls system.cpu1.workload.num_syscalls 18 # Number of system calls
system.cpu1.pwrStateResidencyTicks::ON 250015500 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 500032 # number of cpu cycles simulated system.cpu1.numCycles 500032 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
@ -345,6 +353,7 @@ system.cpu1.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 500019 # Class of executed instruction system.cpu1.op_class::total 500019 # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 61 # number of replacements system.cpu1.dcache.tags.replacements 61 # number of replacements
system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks. system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
@ -361,6 +370,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::2 248
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 723563 # Number of tag accesses system.cpu1.dcache.tags.tag_accesses 723563 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 723563 # Number of data accesses system.cpu1.dcache.tags.data_accesses 723563 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 56201 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 56201 # number of WriteReq hits
@ -401,6 +411,7 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu1.dcache.writebacks::total 29 # number of writebacks system.cpu1.dcache.writebacks::total 29 # number of writebacks
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 152 # number of replacements system.cpu1.icache.tags.replacements 152 # number of replacements
system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks. system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks.
@ -416,6 +427,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 121
system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 500482 # Number of tag accesses system.cpu1.icache.tags.tag_accesses 500482 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 500482 # Number of data accesses system.cpu1.icache.tags.data_accesses 500482 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits
@ -481,6 +493,7 @@ system.cpu2.itb.data_misses 0 # DT
system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.workload.num_syscalls 18 # Number of system calls system.cpu2.workload.num_syscalls 18 # Number of system calls
system.cpu2.pwrStateResidencyTicks::ON 250015500 # Cumulative time (in ticks) in various power states
system.cpu2.numCycles 500032 # number of cpu cycles simulated system.cpu2.numCycles 500032 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
@ -539,6 +552,7 @@ system.cpu2.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::total 500019 # Class of executed instruction system.cpu2.op_class::total 500019 # Class of executed instruction
system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu2.dcache.tags.replacements 61 # number of replacements system.cpu2.dcache.tags.replacements 61 # number of replacements
system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks. system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
@ -555,6 +569,7 @@ system.cpu2.dcache.tags.age_task_id_blocks_1024::2 248
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses 723563 # Number of tag accesses system.cpu2.dcache.tags.tag_accesses 723563 # Number of tag accesses
system.cpu2.dcache.tags.data_accesses 723563 # Number of data accesses system.cpu2.dcache.tags.data_accesses 723563 # Number of data accesses
system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 56201 # number of WriteReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 56201 # number of WriteReq hits
@ -595,6 +610,7 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu2.dcache.writebacks::total 29 # number of writebacks system.cpu2.dcache.writebacks::total 29 # number of writebacks
system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu2.icache.tags.replacements 152 # number of replacements system.cpu2.icache.tags.replacements 152 # number of replacements
system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks. system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks.
@ -610,6 +626,7 @@ system.cpu2.icache.tags.age_task_id_blocks_1024::2 121
system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses 500482 # Number of tag accesses system.cpu2.icache.tags.tag_accesses 500482 # Number of tag accesses
system.cpu2.icache.tags.data_accesses 500482 # Number of data accesses system.cpu2.icache.tags.data_accesses 500482 # Number of data accesses
system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits
@ -675,6 +692,7 @@ system.cpu3.itb.data_misses 0 # DT
system.cpu3.itb.data_acv 0 # DTB access violations system.cpu3.itb.data_acv 0 # DTB access violations
system.cpu3.itb.data_accesses 0 # DTB accesses system.cpu3.itb.data_accesses 0 # DTB accesses
system.cpu3.workload.num_syscalls 18 # Number of system calls system.cpu3.workload.num_syscalls 18 # Number of system calls
system.cpu3.pwrStateResidencyTicks::ON 250015500 # Cumulative time (in ticks) in various power states
system.cpu3.numCycles 500032 # number of cpu cycles simulated system.cpu3.numCycles 500032 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
@ -733,6 +751,7 @@ system.cpu3.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::total 500019 # Class of executed instruction system.cpu3.op_class::total 500019 # Class of executed instruction
system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu3.dcache.tags.replacements 61 # number of replacements system.cpu3.dcache.tags.replacements 61 # number of replacements
system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks. system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
@ -749,6 +768,7 @@ system.cpu3.dcache.tags.age_task_id_blocks_1024::2 248
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses 723563 # Number of tag accesses system.cpu3.dcache.tags.tag_accesses 723563 # Number of tag accesses
system.cpu3.dcache.tags.data_accesses 723563 # Number of data accesses system.cpu3.dcache.tags.data_accesses 723563 # Number of data accesses
system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu3.dcache.ReadReq_hits::cpu3.data 124111 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::cpu3.data 124111 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 56201 # number of WriteReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 56201 # number of WriteReq hits
@ -789,6 +809,7 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu3.dcache.writebacks::total 29 # number of writebacks system.cpu3.dcache.writebacks::total 29 # number of writebacks
system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu3.icache.tags.replacements 152 # number of replacements system.cpu3.icache.tags.replacements 152 # number of replacements
system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks. system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks.
@ -804,6 +825,7 @@ system.cpu3.icache.tags.age_task_id_blocks_1024::2 121
system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses 500482 # Number of tag accesses system.cpu3.icache.tags.tag_accesses 500482 # Number of tag accesses
system.cpu3.icache.tags.data_accesses 500482 # Number of data accesses system.cpu3.icache.tags.data_accesses 500482 # Number of data accesses
system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits
@ -836,6 +858,7 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.writebacks::writebacks 152 # number of writebacks system.cpu3.icache.writebacks::writebacks 152 # number of writebacks
system.cpu3.icache.writebacks::total 152 # number of writebacks system.cpu3.icache.writebacks::total 152 # number of writebacks
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use
system.l2c.tags.total_refs 1068 # Total number of references to valid blocks. system.l2c.tags.total_refs 1068 # Total number of references to valid blocks.
@ -868,6 +891,7 @@ system.l2c.tags.age_task_id_blocks_1024::2 1836 #
system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 39936 # Number of tag accesses system.l2c.tags.tag_accesses 39936 # Number of tag accesses
system.l2c.tags.data_accesses 39936 # Number of data accesses system.l2c.tags.data_accesses 39936 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits
@ -1015,6 +1039,7 @@ system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 2872 # Transaction distribution system.membus.trans_dist::ReadResp 2872 # Transaction distribution
system.membus.trans_dist::ReadExReq 556 # Transaction distribution system.membus.trans_dist::ReadExReq 556 # Transaction distribution
system.membus.trans_dist::ReadExResp 556 # Transaction distribution system.membus.trans_dist::ReadExResp 556 # Transaction distribution
@ -1040,6 +1065,7 @@ system.toL2Bus.snoop_filter.hit_multi_requests 0
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution

130
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
View file

@ -14,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus p
boot_osflags=a boot_osflags=a
cache_line_size=64 cache_line_size=64
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
exit_on_work_items=false exit_on_work_items=false
init_param=0 init_param=0
@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false mmap_using_noreserve=false
multi_thread=false multi_thread=false
num_work_ids=16 num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile= readfile=
symbolfile= symbolfile=
thermal_components= thermal_components=
@ -55,6 +60,7 @@ branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=0 cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -70,6 +76,10 @@ max_insts_any_thread=500000
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0 profile=0
progress_interval=0 progress_interval=0
simpoint_start_insts= simpoint_start_insts=
@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -112,8 +127,13 @@ type=LRU
assoc=4 assoc=4
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -153,8 +178,13 @@ type=LRU
assoc=1 assoc=1
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -196,6 +226,7 @@ branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=1 cpu_id=1
default_p_state=UNDEFINED
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -211,6 +242,10 @@ max_insts_any_thread=500000
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0 profile=0
progress_interval=0 progress_interval=0
simpoint_start_insts= simpoint_start_insts=
@ -229,12 +264,17 @@ addr_ranges=0:18446744073709551615
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -253,8 +293,13 @@ type=LRU
assoc=4 assoc=4
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -270,12 +315,17 @@ addr_ranges=0:18446744073709551615
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -294,8 +344,13 @@ type=LRU
assoc=1 assoc=1
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -337,6 +392,7 @@ branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=2 cpu_id=2
default_p_state=UNDEFINED
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -352,6 +408,10 @@ max_insts_any_thread=500000
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0 profile=0
progress_interval=0 progress_interval=0
simpoint_start_insts= simpoint_start_insts=
@ -370,12 +430,17 @@ addr_ranges=0:18446744073709551615
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -394,8 +459,13 @@ type=LRU
assoc=4 assoc=4
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -411,12 +481,17 @@ addr_ranges=0:18446744073709551615
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -435,8 +510,13 @@ type=LRU
assoc=1 assoc=1
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -478,6 +558,7 @@ branchPred=Null
checker=Null checker=Null
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
cpu_id=3 cpu_id=3
default_p_state=UNDEFINED
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -493,6 +574,10 @@ max_insts_any_thread=500000
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0 profile=0
progress_interval=0 progress_interval=0
simpoint_start_insts= simpoint_start_insts=
@ -511,12 +596,17 @@ addr_ranges=0:18446744073709551615
assoc=4 assoc=4
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -535,8 +625,13 @@ type=LRU
assoc=4 assoc=4
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -552,12 +647,17 @@ addr_ranges=0:18446744073709551615
assoc=1 assoc=1
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=2 response_latency=2
@ -576,8 +676,13 @@ type=LRU
assoc=1 assoc=1
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=2 hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=32768 size=32768
@ -635,12 +740,17 @@ addr_ranges=0:18446744073709551615
assoc=8 assoc=8
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
hit_latency=20 hit_latency=20
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
mshrs=20 mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
response_latency=20 response_latency=20
@ -659,8 +769,13 @@ type=LRU
assoc=8 assoc=8
block_size=64 block_size=64
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
hit_latency=20 hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false sequential_access=false
size=4194304 size=4194304
@ -668,10 +783,15 @@ size=4194304
type=CoherentXBar type=CoherentXBar
children=snoop_filter children=snoop_filter
clk_domain=system.clk_domain clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
forward_latency=4 forward_latency=4
frontend_latency=3 frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true point_of_coherency=true
power_model=Null
response_latency=2 response_latency=2
snoop_filter=system.membus.snoop_filter snoop_filter=system.membus.snoop_filter
snoop_response_latency=4 snoop_response_latency=4
@ -693,11 +813,16 @@ type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clk_domain=system.clk_domain clk_domain=system.clk_domain
conf_table_reported=true conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
in_addr_map=true in_addr_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0
null=false null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727 range=0:134217727
port=system.membus.master[0] port=system.membus.master[0]
@ -705,10 +830,15 @@ port=system.membus.master[0]
type=CoherentXBar type=CoherentXBar
children=snoop_filter children=snoop_filter
clk_domain=system.cpu_clk_domain clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0 eventq_index=0
forward_latency=0 forward_latency=0
frontend_latency=1 frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false point_of_coherency=false
power_model=Null
response_latency=1 response_latency=1
snoop_filter=system.toL2Bus.snoop_filter snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1 snoop_response_latency=1

648
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json
View file

File diff suppressed because it is too large Load diff

12
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
View file

@ -1,11 +1,11 @@
warn: Sockets disabled, not accepting gdb connections warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything
gzip: stdout:
gzip: stdout: Broken pipe gzip: stdout: Broken pipe
stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe

6
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 5 2016 19:50:43 gem5 compiled Jun 12 2016 19:14:13
gem5 started Jun 5 2016 20:00:38 gem5 started Jun 12 2016 19:14:35
gem5 executing on zizzer, pid 54353 gem5 executing on zizzer, pid 29705
command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/30.eio-mp/alpha/eio/simple-timing-mp command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second

36
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
View file

@ -4,15 +4,16 @@ sim_seconds 0.000735 # Nu
sim_ticks 734771500 # Number of ticks simulated sim_ticks 734771500 # Number of ticks simulated
final_tick 734771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 734771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 460544 # Simulator instruction rate (inst/s) host_inst_rate 583455 # Simulator instruction rate (inst/s)
host_op_rate 460541 # Simulator op (including micro ops) rate (op/s) host_op_rate 583451 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 169197253 # Simulator tick rate (ticks/s) host_tick_rate 214352932 # Simulator tick rate (ticks/s)
host_mem_usage 245584 # Number of bytes of host memory used host_mem_usage 246584 # Number of bytes of host memory used
host_seconds 4.34 # Real time elapsed on the host host_seconds 3.43 # Real time elapsed on the host
sim_insts 1999973 # Number of instructions simulated sim_insts 1999973 # Number of instructions simulated
sim_ops 1999973 # Number of ops (including micro ops) simulated sim_ops 1999973 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
@ -59,6 +60,7 @@ system.physmem.bw_total::cpu2.data 39544266 # To
system.physmem.bw_total::cpu3.inst 35102069 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.inst 35102069 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 39544266 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 39544266 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 298585343 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 298585343 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_misses 0 # ITB misses
@ -93,6 +95,7 @@ system.cpu0.itb.data_misses 0 # DT
system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.workload.num_syscalls 18 # Number of system calls system.cpu0.workload.num_syscalls 18 # Number of system calls
system.cpu0.pwrStateResidencyTicks::ON 734771500 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 1469543 # number of cpu cycles simulated system.cpu0.numCycles 1469543 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
@ -151,6 +154,7 @@ system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 500019 # Class of executed instruction system.cpu0.op_class::total 500019 # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 61 # number of replacements system.cpu0.dcache.tags.replacements 61 # number of replacements
system.cpu0.dcache.tags.tagsinuse 272.993368 # Cycle average of tags in use system.cpu0.dcache.tags.tagsinuse 272.993368 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
@ -167,6 +171,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 367
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
@ -255,6 +260,7 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 61038.876890
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 61038.876890 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 61038.876890 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 152 # number of replacements system.cpu0.icache.tags.replacements 152 # number of replacements
system.cpu0.icache.tags.tagsinuse 216.071308 # Cycle average of tags in use system.cpu0.icache.tags.tagsinuse 216.071308 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks. system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks.
@ -269,6 +275,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 311
system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 500483 # Number of tag accesses system.cpu0.icache.tags.tag_accesses 500483 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 500483 # Number of data accesses system.cpu0.icache.tags.data_accesses 500483 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
@ -370,6 +377,7 @@ system.cpu1.itb.data_misses 0 # DT
system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.workload.num_syscalls 18 # Number of system calls system.cpu1.workload.num_syscalls 18 # Number of system calls
system.cpu1.pwrStateResidencyTicks::ON 734771500 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 1469543 # number of cpu cycles simulated system.cpu1.numCycles 1469543 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
@ -428,6 +436,7 @@ system.cpu1.op_class::MemWrite 56349 11.27% 100.00% # Cl
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 500013 # Class of executed instruction system.cpu1.op_class::total 500013 # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 61 # number of replacements system.cpu1.dcache.tags.replacements 61 # number of replacements
system.cpu1.dcache.tags.tagsinuse 272.990534 # Cycle average of tags in use system.cpu1.dcache.tags.tagsinuse 272.990534 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks. system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
@ -444,6 +453,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::2 367
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 723559 # Number of tag accesses system.cpu1.dcache.tags.tag_accesses 723559 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 723559 # Number of data accesses system.cpu1.dcache.tags.data_accesses 723559 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits
@ -532,6 +542,7 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 61039.956803
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 61039.956803 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 61039.956803 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 152 # number of replacements system.cpu1.icache.tags.replacements 152 # number of replacements
system.cpu1.icache.tags.tagsinuse 216.069189 # Cycle average of tags in use system.cpu1.icache.tags.tagsinuse 216.069189 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 499551 # Total number of references to valid blocks. system.cpu1.icache.tags.total_refs 499551 # Total number of references to valid blocks.
@ -546,6 +557,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 311
system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 500477 # Number of tag accesses system.cpu1.icache.tags.tag_accesses 500477 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 500477 # Number of data accesses system.cpu1.icache.tags.data_accesses 500477 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 499551 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::cpu1.inst 499551 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 499551 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 499551 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 499551 # number of demand (read+write) hits system.cpu1.icache.demand_hits::cpu1.inst 499551 # number of demand (read+write) hits
@ -647,6 +659,7 @@ system.cpu2.itb.data_misses 0 # DT
system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.workload.num_syscalls 18 # Number of system calls system.cpu2.workload.num_syscalls 18 # Number of system calls
system.cpu2.pwrStateResidencyTicks::ON 734771500 # Cumulative time (in ticks) in various power states
system.cpu2.numCycles 1469543 # number of cpu cycles simulated system.cpu2.numCycles 1469543 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
@ -705,6 +718,7 @@ system.cpu2.op_class::MemWrite 56349 11.27% 100.00% # Cl
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::total 500008 # Class of executed instruction system.cpu2.op_class::total 500008 # Class of executed instruction
system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu2.dcache.tags.replacements 61 # number of replacements system.cpu2.dcache.tags.replacements 61 # number of replacements
system.cpu2.dcache.tags.tagsinuse 272.987788 # Cycle average of tags in use system.cpu2.dcache.tags.tagsinuse 272.987788 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 180311 # Total number of references to valid blocks. system.cpu2.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
@ -721,6 +735,7 @@ system.cpu2.dcache.tags.age_task_id_blocks_1024::2 367
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses 723559 # Number of tag accesses system.cpu2.dcache.tags.tag_accesses 723559 # Number of tag accesses
system.cpu2.dcache.tags.data_accesses 723559 # Number of data accesses system.cpu2.dcache.tags.data_accesses 723559 # Number of data accesses
system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits
@ -809,6 +824,7 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 61038.876890
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency system.cpu2.dcache.demand_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 61038.876890 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 61038.876890 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency
system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu2.icache.tags.replacements 152 # number of replacements system.cpu2.icache.tags.replacements 152 # number of replacements
system.cpu2.icache.tags.tagsinuse 216.067062 # Cycle average of tags in use system.cpu2.icache.tags.tagsinuse 216.067062 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 499546 # Total number of references to valid blocks. system.cpu2.icache.tags.total_refs 499546 # Total number of references to valid blocks.
@ -823,6 +839,7 @@ system.cpu2.icache.tags.age_task_id_blocks_1024::2 311
system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses 500472 # Number of tag accesses system.cpu2.icache.tags.tag_accesses 500472 # Number of tag accesses
system.cpu2.icache.tags.data_accesses 500472 # Number of data accesses system.cpu2.icache.tags.data_accesses 500472 # Number of data accesses
system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu2.icache.ReadReq_hits::cpu2.inst 499546 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::cpu2.inst 499546 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 499546 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 499546 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 499546 # number of demand (read+write) hits system.cpu2.icache.demand_hits::cpu2.inst 499546 # number of demand (read+write) hits
@ -924,6 +941,7 @@ system.cpu3.itb.data_misses 0 # DT
system.cpu3.itb.data_acv 0 # DTB access violations system.cpu3.itb.data_acv 0 # DTB access violations
system.cpu3.itb.data_accesses 0 # DTB accesses system.cpu3.itb.data_accesses 0 # DTB accesses
system.cpu3.workload.num_syscalls 18 # Number of system calls system.cpu3.workload.num_syscalls 18 # Number of system calls
system.cpu3.pwrStateResidencyTicks::ON 734771500 # Cumulative time (in ticks) in various power states
system.cpu3.numCycles 1469543 # number of cpu cycles simulated system.cpu3.numCycles 1469543 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
@ -982,6 +1000,7 @@ system.cpu3.op_class::MemWrite 56349 11.27% 100.00% # Cl
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::total 500005 # Class of executed instruction system.cpu3.op_class::total 500005 # Class of executed instruction
system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu3.dcache.tags.replacements 61 # number of replacements system.cpu3.dcache.tags.replacements 61 # number of replacements
system.cpu3.dcache.tags.tagsinuse 272.985038 # Cycle average of tags in use system.cpu3.dcache.tags.tagsinuse 272.985038 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 180309 # Total number of references to valid blocks. system.cpu3.dcache.tags.total_refs 180309 # Total number of references to valid blocks.
@ -998,6 +1017,7 @@ system.cpu3.dcache.tags.age_task_id_blocks_1024::2 367
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses 723551 # Number of tag accesses system.cpu3.dcache.tags.tag_accesses 723551 # Number of tag accesses
system.cpu3.dcache.tags.data_accesses 723551 # Number of data accesses system.cpu3.dcache.tags.data_accesses 723551 # Number of data accesses
system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu3.dcache.ReadReq_hits::cpu3.data 124109 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::cpu3.data 124109 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 124109 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 124109 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits
@ -1086,6 +1106,7 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 61039.956803
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency system.cpu3.dcache.demand_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 61039.956803 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 61039.956803 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency
system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu3.icache.tags.replacements 152 # number of replacements system.cpu3.icache.tags.replacements 152 # number of replacements
system.cpu3.icache.tags.tagsinuse 216.064909 # Cycle average of tags in use system.cpu3.icache.tags.tagsinuse 216.064909 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 499543 # Total number of references to valid blocks. system.cpu3.icache.tags.total_refs 499543 # Total number of references to valid blocks.
@ -1100,6 +1121,7 @@ system.cpu3.icache.tags.age_task_id_blocks_1024::2 311
system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses 500469 # Number of tag accesses system.cpu3.icache.tags.tag_accesses 500469 # Number of tag accesses
system.cpu3.icache.tags.data_accesses 500469 # Number of data accesses system.cpu3.icache.tags.data_accesses 500469 # Number of data accesses
system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.cpu3.icache.ReadReq_hits::cpu3.inst 499543 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::cpu3.inst 499543 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 499543 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 499543 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 499543 # number of demand (read+write) hits system.cpu3.icache.demand_hits::cpu3.inst 499543 # number of demand (read+write) hits
@ -1168,6 +1190,7 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 55578.833693
system.cpu3.icache.demand_avg_mshr_miss_latency::total 55578.833693 # average overall mshr miss latency system.cpu3.icache.demand_avg_mshr_miss_latency::total 55578.833693 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 55578.833693 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 55578.833693 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 55578.833693 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 55578.833693 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 1939.822021 # Cycle average of tags in use system.l2c.tags.tagsinuse 1939.822021 # Cycle average of tags in use
system.l2c.tags.total_refs 1068 # Total number of references to valid blocks. system.l2c.tags.total_refs 1068 # Total number of references to valid blocks.
@ -1200,6 +1223,7 @@ system.l2c.tags.age_task_id_blocks_1024::2 2904 #
system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 39936 # Number of tag accesses system.l2c.tags.tag_accesses 39936 # Number of tag accesses
system.l2c.tags.data_accesses 39936 # Number of data accesses system.l2c.tags.data_accesses 39936 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits
@ -1545,6 +1569,7 @@ system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 2872 # Transaction distribution system.membus.trans_dist::ReadResp 2872 # Transaction distribution
system.membus.trans_dist::ReadExReq 556 # Transaction distribution system.membus.trans_dist::ReadExReq 556 # Transaction distribution
system.membus.trans_dist::ReadExResp 556 # Transaction distribution system.membus.trans_dist::ReadExResp 556 # Transaction distribution
@ -1574,6 +1599,7 @@ system.toL2Bus.snoop_filter.hit_multi_requests 0
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution