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ARM: Decode the ssub instructions.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:06 -05:00
parent fd6e9f304e
commit 5495ebd68d
1 changed files with 6 additions and 4 deletions
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10
src/arch/arm/isa/formats/data.isa
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@ -240,11 +240,11 @@ def format ArmParallelAddSubtract() {{
case 0x2: case 0x2:
return new WarnUnimplemented("ssax", machInst); return new WarnUnimplemented("ssax", machInst);
case 0x3: case 0x3:
return new WarnUnimplemented("ssub16", machInst); return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL);
case 0x4: case 0x4:
return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL);
case 0x7: case 0x7:
return new WarnUnimplemented("ssub8", machInst); return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL);
} }
break; break;
case 0x2: case 0x2:
@ -557,12 +557,14 @@ def format Thumb32DataProcReg() {{
case 0x6: case 0x6:
return new WarnUnimplemented("ssax", machInst); return new WarnUnimplemented("ssax", machInst);
case 0x5: case 0x5:
return new WarnUnimplemented("ssub16", machInst); return new Ssub16RegCc(machInst, rd,
rn, rm, 0, LSL);
case 0x0: case 0x0:
return new Sadd8RegCc(machInst, rd, return new Sadd8RegCc(machInst, rd,
rn, rm, 0, LSL); rn, rm, 0, LSL);
case 0x4: case 0x4:
return new WarnUnimplemented("ssub8", machInst); return new Ssub8RegCc(machInst, rd,
rn, rm, 0, LSL);
} }
break; break;
case 0x1: case 0x1: