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get rid of defined and just access the env dict directly

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get rid of the alias for true to True and false to False to keep
consistent python syntax.

util/stats/info.py:
    Fix typo

--HG--
extra : convert_revision : e69588a8de52424e043315e70008ca3a3ede7d5b
This commit is contained in:
Nathan Binkert 2005-02-03 17:04:54 -05:00
parent 936ad58402
commit 52403a5ddf
10 changed files with 23 additions and 35 deletions
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2
objects/BaseCPU.mpy
View file

@ -19,7 +19,7 @@ simobj BaseCPU(SimObject):
max_loads_any_thread = Param.Counter(0,
"terminate when any thread reaches this load count")
defer_registration = Param.Bool(false,
defer_registration = Param.Bool(False,
"defer registration with system (for sampling)")
def check(self):

16
objects/BaseCache.mpy
View file

@ -2,37 +2,37 @@ from BaseMem import BaseMem
simobj BaseCache(BaseMem):
type = 'BaseCache'
adaptive_compression = Param.Bool(false,
adaptive_compression = Param.Bool(False,
"Use an adaptive compression scheme")
assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes")
compressed_bus = Param.Bool(false,
compressed_bus = Param.Bool(False,
"This cache connects to a compressed memory")
compression_latency = Param.Int(0,
"Latency in cycles of compression algorithm")
do_copy = Param.Bool(false, "perform fast copies in the cache")
do_copy = Param.Bool(False, "perform fast copies in the cache")
hash_delay = Param.Int(1, "time in cycles of hash access")
in_bus = Param.Bus(NULL, "incoming bus object")
lifo = Param.Bool(false,
lifo = Param.Bool(False,
"whether this NIC partition should use LIFO repl. policy")
max_miss_count = Param.Counter(0,
"number of misses to handle before calling exit")
mshrs = Param.Int("number of MSHRs (max outstanding requests)")
out_bus = Param.Bus("outgoing bus object")
prioritizeRequests = Param.Bool(false,
prioritizeRequests = Param.Bool(False,
"always service demand misses first")
protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
repl = Param.Repl(NULL, "replacement policy")
size = Param.Int("capacity in bytes")
split = Param.Bool(false, "whether or not this cache is split")
split = Param.Bool(False, "whether or not this cache is split")
split_size = Param.Int(0,
"How many ways of the cache belong to CPU/LRU partition")
store_compressed = Param.Bool(false,
store_compressed = Param.Bool(False,
"Store compressed data in the cache")
subblock_size = Param.Int(0,
"Size of subblock in IIC used for compression")
tgts_per_mshr = Param.Int("max number of accesses per MSHR")
trace_addr = Param.Addr(0, "address to trace")
two_queue = Param.Bool(false,
two_queue = Param.Bool(False,
"whether the lifo should have two queue replacement")
write_buffers = Param.Int(8, "number of write buffers")

2
objects/BaseSystem.mpy
View file

@ -11,5 +11,5 @@ simobj BaseSystem(SimObject):
boot_osflags = Param.String("a", "boot flags to pass to the kernel")
system_type = Param.UInt64("Type of system we are emulating")
system_rev = Param.UInt64("Revision of system we are emulating")
bin = Param.Bool(false, "is this system binned")
bin = Param.Bool(False, "is this system binned")
binned_fns = VectorParam.String([], "functions broken down and binned")

2
objects/CoherenceProtocol.mpy
View file

@ -2,5 +2,5 @@ Coherence = Enum('uni', 'msi', 'mesi', 'mosi', 'moesi')
simobj CoherenceProtocol(SimObject):
type = 'CoherenceProtocol'
do_upgrades = Param.Bool(true, "use upgrade transactions?")
do_upgrades = Param.Bool(True, "use upgrade transactions?")
protocol = Param.Coherence("name of coherence protocol")

2
objects/DiskImage.mpy
View file

@ -2,7 +2,7 @@ simobj DiskImage(SimObject):
type = 'DiskImage'
abstract = True
image_file = Param.String("disk image file")
read_only = Param.Bool(false, "read only image")
read_only = Param.Bool(False, "read only image")
simobj RawDiskImage(DiskImage):
type = 'RawDiskImage'

14
objects/Ethernet.mpy
View file

@ -16,7 +16,7 @@ simobj EtherLink(SimObject):
simobj EtherBus(SimObject):
type = 'EtherBus'
loopback = Param.Bool(true,
loopback = Param.Bool(True,
"send packet back to the interface from which it came")
dump = Param.EtherDump(NULL, "dump object")
speed = Param.UInt64(100000000, "bus speed in bits per second")
@ -36,14 +36,14 @@ simobj EtherDev(DmaDevice):
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
dma_data_free = Param.Bool(false, "DMA of Data is free")
dma_desc_free = Param.Bool(false, "DMA of Descriptors is free")
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_read_delay = Param.Tick(0, "fixed delay for dma reads")
dma_read_factor = Param.Tick(0, "multiplier for dma reads")
dma_write_delay = Param.Tick(0, "fixed delay for dma writes")
dma_write_factor = Param.Tick(0, "multiplier for dma writes")
rx_filter = Param.Bool(true, "Enable Receive Filter")
rx_filter = Param.Bool(True, "Enable Receive Filter")
rx_delay = Param.Tick(1000, "Receive Delay")
tx_delay = Param.Tick(1000, "Transmit Delay")
@ -57,14 +57,14 @@ simobj NSGigE(PciDevice):
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
dma_data_free = Param.Bool(false, "DMA of Data is free")
dma_desc_free = Param.Bool(false, "DMA of Descriptors is free")
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_read_delay = Param.Tick(0, "fixed delay for dma reads")
dma_read_factor = Param.Tick(0, "multiplier for dma reads")
dma_write_delay = Param.Tick(0, "fixed delay for dma writes")
dma_write_factor = Param.Tick(0, "multiplier for dma writes")
rx_filter = Param.Bool(true, "Enable Receive Filter")
rx_filter = Param.Bool(True, "Enable Receive Filter")
rx_delay = Param.Tick(1000, "Receive Delay")
tx_delay = Param.Tick(1000, "Transmit Delay")

2
objects/Root.mpy
View file

@ -7,5 +7,5 @@ simobj Root(SimObject):
config_output_file = Param.String('m5config.out',
"file to dump simulator config to")
full_system = Param.Bool("Full system simulation?")
hier = HierParams(do_data = false, do_events = true)
hier = HierParams(do_data = False, do_events = True)
checkpoint = Param.String('', "Checkpoint file")

2
objects/SimConsole.mpy
View file

@ -4,7 +4,7 @@ simobj ConsoleListener(SimObject):
simobj SimConsole(SimObject):
type = 'SimConsole'
append_name = Param.Bool(true, "append name() to filename")
append_name = Param.Bool(True, "append name() to filename")
intr_control = Param.IntrControl(Super, "interrupt controller")
listener = Param.ConsoleListener("console listener")
number = Param.Int(0, "console number")

14
sim/pyconfig/m5config.py
View file

@ -34,11 +34,6 @@ except:
env = {}
env.update(os.environ)
def defined(key):
return env.has_key(key)
def define(key, value = True):
env[key] = value
def panic(*args, **kwargs):
sys.exit(*args, **kwargs)
@ -64,9 +59,6 @@ class Singleton(type):
cls._instance = super(Singleton, cls).__call__(*args, **kwargs)
return cls._instance
if os.environ.has_key('FULL_SYSTEM'):
FULL_SYSTEM = True
#####################################################################
#
# M5 Python Configuration Utility
@ -670,7 +662,7 @@ class Node(object):
% (self.name, ptype, value._path)
found, done = obj.find(ptype, value._path)
if isinstance(found, Proxy):
done = false
done = False
obj = obj.parent
return found
@ -1267,10 +1259,6 @@ class Enum(type):
# "Constants"... handy aliases for various values.
#
# For compatibility with C++ bool constants.
false = False
true = True
# Some memory range specifications use this as a default upper bound.
MAX_ADDR = Addr._max
MaxTick = Tick._max

2
util/stats/info.py
View file

@ -324,7 +324,7 @@ class Vector(Statistic,FormulaStat):
def __eq__(self, other):
if issequence(self.value) != issequence(other.value):
return false
return False
if issequence(self.value):
if len(self.value) != len(other.value):