Split out basic types from isa_traits.hh into a new file, types.hh

arch/alpha/isa_traits.hh:
    Pulled out basic type definitions into types.hh
arch/alpha/types.hh:
    New BitKeeper file ``arch/alpha/types.hh''
    For relatively basic types associated with an architecture. This does not include, for instance, register files.

--HG--
extra : convert_revision : ee6c4afc115271ad237208274c863a7dee97c5d7

arch/alpha/isa_traits.hh

@@ -32,7 +32,7 @@
 namespace LittleEndianGuest {}
 using namespace LittleEndianGuest;
 
-//#include "arch/alpha/faults.hh"
+#include "arch/alpha/types.hh"
 #include "base/misc.hh"
 #include "config/full_system.hh"
 #include "sim/host.hh"
@@ -92,10 +92,6 @@ class SyscallReturn {
 namespace AlphaISA
 {
 
-    typedef uint32_t MachInst;
-    typedef uint64_t ExtMachInst;
-    typedef uint8_t  RegIndex;
-
     const int NumIntArchRegs = 32;
     const int NumPALShadowRegs = 8;
     const int NumFloatArchRegs = 32;
@@ -141,28 +137,8 @@ namespace AlphaISA
     const int NumFloatRegs = NumFloatArchRegs;
     const int NumMiscRegs = NumMiscArchRegs;
 
-    // These enumerate all the registers for dependence tracking.
-    enum DependenceTags {
-        // 0..31 are the integer regs 0..31
-        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
-        FP_Base_DepTag = 40,
-        Ctrl_Base_DepTag = 72,
-        Fpcr_DepTag = 72,		// floating point control register
-        Uniq_DepTag = 73,
-        Lock_Flag_DepTag = 74,
-        Lock_Addr_DepTag = 75,
-        IPR_Base_DepTag = 76
-    };
-
-    typedef uint64_t IntReg;
     typedef IntReg IntRegFile[NumIntRegs];
 
-    // floating point register file entry type
-    typedef union {
-        uint64_t q;
-        double d;
-    } FloatReg;
-
     typedef union {
         uint64_t q[NumFloatRegs];	// integer qword view
         double d[NumFloatRegs];		// double-precision floating point view
@@ -178,16 +154,11 @@ extern const int reg_redir[NumIntRegs];
 
 #if FULL_SYSTEM
 
-    typedef uint64_t InternalProcReg;
-
 #include "arch/alpha/isa_fullsys_traits.hh"
 
 #else
     const int NumInternalProcRegs = 0;
 #endif
-
-    // control register file contents
-    typedef uint64_t MiscReg;
     class MiscRegFile {
       protected:
         uint64_t	fpcr;		// floating point condition codes
@@ -231,12 +202,6 @@ extern const int reg_redir[NumIntRegs];
 
     const int TotalDataRegs = NumIntRegs + NumFloatRegs;
 
-    typedef union {
-        IntReg  intreg;
-        FloatReg   fpreg;
-        MiscReg ctrlreg;
-    } AnyReg;
-
     struct RegFile {
         IntRegFile intRegFile;		// (signed) integer register file
         FloatRegFile floatRegFile;	// floating point register file
@@ -264,12 +229,6 @@ extern const int reg_redir[NumIntRegs];
     // return a no-op instruction... used for instruction fetch faults
     extern const ExtMachInst NoopMachInst;
 
-    enum annotes {
-        ANNOTE_NONE = 0,
-        // An impossible number for instruction annotations
-        ITOUCH_ANNOTE = 0xffffffff,
-    };
-
     static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
         panic("register classification not implemented");
         return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);

arch/alpha/types.hh

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_ALPHA_TYPES_HH__
+#define __ARCH_ALPHA_TYPES_HH__
+
+#include "config/full_system.hh"
+#include "sim/host.hh"
+
+namespace AlphaISA
+{
+
+    typedef uint32_t MachInst;
+    typedef uint64_t ExtMachInst;
+    typedef uint8_t  RegIndex;
+
+    // These enumerate all the registers for dependence tracking.
+    enum DependenceTags {
+        // 0..31 are the integer regs 0..31
+        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
+        FP_Base_DepTag = 40,
+        Ctrl_Base_DepTag = 72,
+        Fpcr_DepTag = 72,		// floating point control register
+        Uniq_DepTag = 73,
+        Lock_Flag_DepTag = 74,
+        Lock_Addr_DepTag = 75,
+        IPR_Base_DepTag = 76
+    };
+
+    typedef uint64_t IntReg;
+
+    // floating point register file entry type
+    typedef union {
+        uint64_t q;
+        double d;
+    } FloatReg;
+
+#if FULL_SYSTEM
+    typedef uint64_t InternalProcReg;
+#endif
+
+    // control register file contents
+    typedef uint64_t MiscReg;
+
+    typedef union {
+        IntReg  intreg;
+        FloatReg   fpreg;
+        MiscReg ctrlreg;
+    } AnyReg;
+
+    enum annotes {
+        ANNOTE_NONE = 0,
+        // An impossible number for instruction annotations
+        ITOUCH_ANNOTE = 0xffffffff,
+    };
+
+} // namespace AlphaISA
+
+#endif