ARM: Reimplement load/store multiple external to the decoder.
--HG-- rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa
This commit is contained in:
parent
93a3714816
commit
51bde086d5
7 changed files with 369 additions and 257 deletions
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@ -82,39 +82,17 @@ class MicroIntOp : public PredOp
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class MicroMemOp : public MicroIntOp
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class MicroMemOp : public MicroIntOp
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{
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{
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protected:
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protected:
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bool up;
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unsigned memAccessFlags;
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unsigned memAccessFlags;
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MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _ura, RegIndex _urb, uint8_t _imm)
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RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
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: MicroIntOp(mnem, machInst, __opClass, _ura, _urb, _imm),
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: MicroIntOp(mnem, machInst, __opClass, _ura, _urb, _imm),
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memAccessFlags(0)
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up(_up), memAccessFlags(0)
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{
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{
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}
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}
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};
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};
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/**
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* Arm Macro Memory operations like LDM/STM
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*/
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class ArmMacroMemoryOp : public PredMacroOp
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{
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protected:
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/// Memory request flags. See mem_req_base.hh.
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unsigned memAccessFlags;
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uint32_t reglist;
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uint32_t ones;
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ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass)
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: PredMacroOp(mnem, _machInst, __opClass), memAccessFlags(0),
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reglist(machInst.regList), ones(0)
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{
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ones = number_of_ones(reglist);
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numMicroops = ones + machInst.puswl.writeback + 1;
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// Remember that writeback adds a uop
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microOps = new StaticInstPtr[numMicroops];
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}
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};
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}
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}
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#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
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#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
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@ -304,10 +304,7 @@ format DataOp {
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}
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}
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}
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}
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}
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}
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0x4: decode PUSWL {
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0x4: ArmMacroMem::armMacroMem();
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// Right now we only handle cases when S (PSRUSER) is not set
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default: ArmMacroStore::ldmstm({{ }});
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}
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0x5: decode OPCODE_24 {
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0x5: decode OPCODE_24 {
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// Branch (and Link) Instructions
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// Branch (and Link) Instructions
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0: Branch::b({{ }});
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0: Branch::b({{ }});
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@ -1,7 +1,16 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2007-2008 The Florida State University
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// Copyright (c) 2010 ARM Limited
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// All rights reserved.
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// modification, are permitted provided that the following conditions are
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@ -26,232 +35,11 @@
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Authors: Stephen Hines
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// Authors: Gabe Black
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// Gabe Black
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////////////////////////////////////////////////////////////////////
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def format ArmMacroMem() {{
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//
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decode_block = '''
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// Common microop templates
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return new LdmStm(machInst, (IntRegIndex)(uint32_t)RN, !PREPOST, UP,
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//
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PSRUSER, WRITEBACK, LOADOP, machInst.regList);
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def template MicroConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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RegIndex _ura,
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RegIndex _urb,
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uint8_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_ura, _urb, _imm)
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{
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%(constructor)s;
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}
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Load/store microops
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//
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def template MicroMemDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst,
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RegIndex _ura, RegIndex _urb,
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uint8_t _imm);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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let {{
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microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
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'MicroMemOp',
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{'memacc_code': 'Ra = Mem;',
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'ea_code': 'EA = Rb + (UP ? imm : -imm);',
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'predicate_test': predicateTest},
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['IsMicroop'])
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microLdrRetUopCode = '''
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Ra = Mem;
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Cpsr = cpsrWriteByInstr(Cpsr, Spsr, 0xF, true);
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'''
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'''
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microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
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'MicroMemOp',
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{'memacc_code': microLdrRetUopCode,
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'ea_code':
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'EA = Rb + (UP ? imm : -imm);',
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'predicate_test': predicateTest},
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['IsMicroop'])
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microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
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'MicroMemOp',
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{'memacc_code': 'Mem = Ra;',
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'ea_code': 'EA = Rb + (UP ? imm : -imm);',
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'predicate_test': predicateTest},
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['IsMicroop'])
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header_output = MicroMemDeclare.subst(microLdrUopIop) + \
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MicroMemDeclare.subst(microLdrRetUopIop) + \
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MicroMemDeclare.subst(microStrUopIop)
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decoder_output = MicroConstructor.subst(microLdrUopIop) + \
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MicroConstructor.subst(microLdrRetUopIop) + \
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MicroConstructor.subst(microStrUopIop)
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exec_output = LoadExecute.subst(microLdrUopIop) + \
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LoadExecute.subst(microLdrRetUopIop) + \
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StoreExecute.subst(microStrUopIop) + \
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LoadInitiateAcc.subst(microLdrUopIop) + \
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LoadInitiateAcc.subst(microLdrRetUopIop) + \
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StoreInitiateAcc.subst(microStrUopIop) + \
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LoadCompleteAcc.subst(microLdrUopIop) + \
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LoadCompleteAcc.subst(microLdrRetUopIop) + \
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StoreCompleteAcc.subst(microStrUopIop)
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Integer = Integer op Immediate microops
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//
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def template MicroIntDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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%(class_name)s(ExtMachInst machInst,
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RegIndex _ura, RegIndex _urb,
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uint8_t _imm);
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%(BasicExecDeclare)s
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};
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}};
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let {{
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microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
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'MicroIntOp',
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{'code': 'Ra = Rb + imm;',
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'predicate_test': predicateTest},
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['IsMicroop'])
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microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
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'MicroIntOp',
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{'code': 'Ra = Rb - imm;',
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'predicate_test': predicateTest},
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['IsMicroop'])
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header_output = MicroIntDeclare.subst(microAddiUopIop) + \
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MicroIntDeclare.subst(microSubiUopIop)
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decoder_output = MicroConstructor.subst(microAddiUopIop) + \
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MicroConstructor.subst(microSubiUopIop)
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exec_output = PredOpExecute.subst(microAddiUopIop) + \
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PredOpExecute.subst(microSubiUopIop)
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Macro Memory-format instructions
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//
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def template MacroStoreDeclare {{
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/**
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* Static instructions class for a store multiple instruction
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*/
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst);
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%(BasicExecDeclare)s
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};
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}};
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def template MacroStoreConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
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{
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%(constructor)s;
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uint32_t regs = reglist;
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uint32_t addr = 0;
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bool up = machInst.puswl.up;
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if (!up)
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addr = (ones << 2) - 4;
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if (machInst.puswl.prepost)
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addr += 4;
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// Add 0 to Rn and stick it in ureg0.
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// This is equivalent to a move.
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microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0);
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unsigned reg = 0;
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bool force_user = machInst.puswl.psruser & !OPCODE_15;
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bool exception_ret = machInst.puswl.psruser & OPCODE_15;
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for (int i = 1; i < ones + 1; i++) {
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// Find the next register.
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while (!bits(regs, reg))
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reg++;
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replaceBits(regs, reg, 0);
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unsigned regIdx = reg;
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if (force_user) {
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regIdx = intRegForceUser(regIdx);
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}
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if (machInst.puswl.loadOp) {
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if (reg == INTREG_PC && exception_ret) {
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// This must be the exception return form of ldm.
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microOps[i] =
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new MicroLdrRetUop(machInst, regIdx, INTREG_UREG0, addr);
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} else {
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microOps[i] =
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new MicroLdrUop(machInst, regIdx, INTREG_UREG0, addr);
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}
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} else {
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microOps[i] =
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new MicroStrUop(machInst, regIdx, INTREG_UREG0, addr);
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}
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if (up)
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addr += 4;
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else
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addr -= 4;
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}
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StaticInstPtr &lastUop = microOps[numMicroops - 1];
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if (machInst.puswl.writeback) {
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if (up) {
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lastUop = new MicroAddiUop(machInst, RN, RN, ones * 4);
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} else {
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lastUop = new MicroSubiUop(machInst, RN, RN, ones * 4);
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}
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}
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lastUop->setLastMicroop();
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}
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}};
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def template MacroStoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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if (fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{
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iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags)
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header_output = MacroStoreDeclare.subst(iop)
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decoder_output = MacroStoreConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = MacroStoreExecute.subst(iop)
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}};
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}};
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@ -48,3 +48,6 @@
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//Stores of a single item
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//Stores of a single item
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##include "str.isa"
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##include "str.isa"
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//Load/store multiple
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##include "macromem.isa"
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131
src/arch/arm/isa/insts/macromem.isa
Normal file
131
src/arch/arm/isa/insts/macromem.isa
Normal file
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@ -0,0 +1,131 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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||||||
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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||||||
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// licensed hereunder. You may use the software subject to the license
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||||||
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
|
||||||
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// modified or unmodified, in source code or in binary form.
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//
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||||||
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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// Gabe Black
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////////////////////////////////////////////////////////////////////
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//
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// Load/store microops
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//
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let {{
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predicateTest = 'testPredicate(CondCodes, condCode)'
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}};
|
||||||
|
|
||||||
|
let {{
|
||||||
|
microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
|
||||||
|
'MicroMemOp',
|
||||||
|
{'memacc_code': 'Ra = Mem;',
|
||||||
|
'ea_code': 'EA = Rb + (up ? imm : -imm);',
|
||||||
|
'predicate_test': predicateTest},
|
||||||
|
['IsMicroop'])
|
||||||
|
|
||||||
|
microLdrRetUopCode = '''
|
||||||
|
Ra = Mem;
|
||||||
|
uint32_t newCpsr =
|
||||||
|
cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
|
||||||
|
Cpsr = ~CondCodesMask & newCpsr;
|
||||||
|
CondCodes = CondCodesMask & newCpsr;
|
||||||
|
'''
|
||||||
|
microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
|
||||||
|
'MicroMemOp',
|
||||||
|
{'memacc_code': microLdrRetUopCode,
|
||||||
|
'ea_code':
|
||||||
|
'EA = Rb + (up ? imm : -imm);',
|
||||||
|
'predicate_test': predicateTest},
|
||||||
|
['IsMicroop'])
|
||||||
|
|
||||||
|
microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
|
||||||
|
'MicroMemOp',
|
||||||
|
{'memacc_code': 'Mem = Ra;',
|
||||||
|
'ea_code': 'EA = Rb + (up ? imm : -imm);',
|
||||||
|
'predicate_test': predicateTest},
|
||||||
|
['IsMicroop'])
|
||||||
|
|
||||||
|
header_output = MicroMemDeclare.subst(microLdrUopIop) + \
|
||||||
|
MicroMemDeclare.subst(microLdrRetUopIop) + \
|
||||||
|
MicroMemDeclare.subst(microStrUopIop)
|
||||||
|
decoder_output = MicroMemConstructor.subst(microLdrUopIop) + \
|
||||||
|
MicroMemConstructor.subst(microLdrRetUopIop) + \
|
||||||
|
MicroMemConstructor.subst(microStrUopIop)
|
||||||
|
exec_output = LoadExecute.subst(microLdrUopIop) + \
|
||||||
|
LoadExecute.subst(microLdrRetUopIop) + \
|
||||||
|
StoreExecute.subst(microStrUopIop) + \
|
||||||
|
LoadInitiateAcc.subst(microLdrUopIop) + \
|
||||||
|
LoadInitiateAcc.subst(microLdrRetUopIop) + \
|
||||||
|
StoreInitiateAcc.subst(microStrUopIop) + \
|
||||||
|
LoadCompleteAcc.subst(microLdrUopIop) + \
|
||||||
|
LoadCompleteAcc.subst(microLdrRetUopIop) + \
|
||||||
|
StoreCompleteAcc.subst(microStrUopIop)
|
||||||
|
}};
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// Integer = Integer op Immediate microops
|
||||||
|
//
|
||||||
|
|
||||||
|
let {{
|
||||||
|
microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
|
||||||
|
'MicroIntOp',
|
||||||
|
{'code': 'Ra = Rb + imm;',
|
||||||
|
'predicate_test': predicateTest},
|
||||||
|
['IsMicroop'])
|
||||||
|
|
||||||
|
microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
|
||||||
|
'MicroIntOp',
|
||||||
|
{'code': 'Ra = Rb - imm;',
|
||||||
|
'predicate_test': predicateTest},
|
||||||
|
['IsMicroop'])
|
||||||
|
|
||||||
|
header_output = MicroIntDeclare.subst(microAddiUopIop) + \
|
||||||
|
MicroIntDeclare.subst(microSubiUopIop)
|
||||||
|
decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \
|
||||||
|
MicroIntConstructor.subst(microSubiUopIop)
|
||||||
|
exec_output = PredOpExecute.subst(microAddiUopIop) + \
|
||||||
|
PredOpExecute.subst(microSubiUopIop)
|
||||||
|
}};
|
||||||
|
|
||||||
|
let {{
|
||||||
|
iop = InstObjParams("ldmstm", "LdmStm", 'PredMacroOp', "", [])
|
||||||
|
header_output = MacroMemDeclare.subst(iop)
|
||||||
|
decoder_output = MacroMemConstructor.subst(iop)
|
||||||
|
exec_output = MacroMemExecute.subst(iop)
|
||||||
|
}};
|
212
src/arch/arm/isa/templates/macromem.isa
Normal file
212
src/arch/arm/isa/templates/macromem.isa
Normal file
|
@ -0,0 +1,212 @@
|
||||||
|
// -*- mode:c++ -*-
|
||||||
|
|
||||||
|
// Copyright (c) 2010 ARM Limited
|
||||||
|
// All rights reserved
|
||||||
|
//
|
||||||
|
// The license below extends only to copyright in the software and shall
|
||||||
|
// not be construed as granting a license to any other intellectual
|
||||||
|
// property including but not limited to intellectual property relating
|
||||||
|
// to a hardware implementation of the functionality of the software
|
||||||
|
// licensed hereunder. You may use the software subject to the license
|
||||||
|
// terms below provided that you ensure that this notice is replicated
|
||||||
|
// unmodified and in its entirety in all distributions of the software,
|
||||||
|
// modified or unmodified, in source code or in binary form.
|
||||||
|
//
|
||||||
|
// Copyright (c) 2007-2008 The Florida State University
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without
|
||||||
|
// modification, are permitted provided that the following conditions are
|
||||||
|
// met: redistributions of source code must retain the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer;
|
||||||
|
// redistributions in binary form must reproduce the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer in the
|
||||||
|
// documentation and/or other materials provided with the distribution;
|
||||||
|
// neither the name of the copyright holders nor the names of its
|
||||||
|
// contributors may be used to endorse or promote products derived from
|
||||||
|
// this software without specific prior written permission.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
//
|
||||||
|
// Authors: Stephen Hines
|
||||||
|
// Gabe Black
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// Load/store microops
|
||||||
|
//
|
||||||
|
|
||||||
|
def template MicroMemDeclare {{
|
||||||
|
class %(class_name)s : public %(base_class)s
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
%(class_name)s(ExtMachInst machInst,
|
||||||
|
RegIndex _ura, RegIndex _urb, bool _up,
|
||||||
|
uint8_t _imm);
|
||||||
|
%(BasicExecDeclare)s
|
||||||
|
%(InitiateAccDeclare)s
|
||||||
|
%(CompleteAccDeclare)s
|
||||||
|
};
|
||||||
|
}};
|
||||||
|
|
||||||
|
def template MicroMemConstructor {{
|
||||||
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
||||||
|
RegIndex _ura,
|
||||||
|
RegIndex _urb,
|
||||||
|
bool _up,
|
||||||
|
uint8_t _imm)
|
||||||
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
||||||
|
_ura, _urb, _up, _imm)
|
||||||
|
{
|
||||||
|
%(constructor)s;
|
||||||
|
}
|
||||||
|
}};
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// Integer = Integer op Immediate microops
|
||||||
|
//
|
||||||
|
|
||||||
|
def template MicroIntDeclare {{
|
||||||
|
class %(class_name)s : public %(base_class)s
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
%(class_name)s(ExtMachInst machInst,
|
||||||
|
RegIndex _ura, RegIndex _urb,
|
||||||
|
uint8_t _imm);
|
||||||
|
%(BasicExecDeclare)s
|
||||||
|
};
|
||||||
|
}};
|
||||||
|
|
||||||
|
def template MicroIntConstructor {{
|
||||||
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
||||||
|
RegIndex _ura,
|
||||||
|
RegIndex _urb,
|
||||||
|
uint8_t _imm)
|
||||||
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
||||||
|
_ura, _urb, _imm)
|
||||||
|
{
|
||||||
|
%(constructor)s;
|
||||||
|
}
|
||||||
|
}};
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// Macro Memory-format instructions
|
||||||
|
//
|
||||||
|
|
||||||
|
def template MacroMemDeclare {{
|
||||||
|
/**
|
||||||
|
* Static instructions class for a store multiple instruction
|
||||||
|
*/
|
||||||
|
class %(class_name)s : public %(base_class)s
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
// Constructor
|
||||||
|
%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
|
||||||
|
bool index, bool up, bool user, bool writeback, bool load,
|
||||||
|
uint32_t reglist);
|
||||||
|
%(BasicExecDeclare)s
|
||||||
|
};
|
||||||
|
}};
|
||||||
|
|
||||||
|
def template MacroMemConstructor {{
|
||||||
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
|
||||||
|
bool index, bool up, bool user, bool writeback, bool load,
|
||||||
|
uint32_t reglist)
|
||||||
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
|
||||||
|
{
|
||||||
|
%(constructor)s;
|
||||||
|
uint32_t regs = reglist;
|
||||||
|
uint32_t ones = number_of_ones(reglist);
|
||||||
|
// Remember that writeback adds a uop
|
||||||
|
numMicroops = ones + (writeback ? 1 : 0) + 1;
|
||||||
|
microOps = new StaticInstPtr[numMicroops];
|
||||||
|
uint32_t addr = 0;
|
||||||
|
|
||||||
|
if (!up)
|
||||||
|
addr = (ones << 2) - 4;
|
||||||
|
|
||||||
|
if (!index)
|
||||||
|
addr += 4;
|
||||||
|
|
||||||
|
// Add 0 to Rn and stick it in ureg0.
|
||||||
|
// This is equivalent to a move.
|
||||||
|
microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
|
||||||
|
|
||||||
|
unsigned reg = 0;
|
||||||
|
bool force_user = user & !bits(reglist, 15);
|
||||||
|
bool exception_ret = user & bits(reglist, 15);
|
||||||
|
|
||||||
|
for (int i = 1; i < ones + 1; i++) {
|
||||||
|
// Find the next register.
|
||||||
|
while (!bits(regs, reg))
|
||||||
|
reg++;
|
||||||
|
replaceBits(regs, reg, 0);
|
||||||
|
|
||||||
|
unsigned regIdx = reg;
|
||||||
|
if (force_user) {
|
||||||
|
regIdx = intRegForceUser(regIdx);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (load) {
|
||||||
|
if (reg == INTREG_PC && exception_ret) {
|
||||||
|
// This must be the exception return form of ldm.
|
||||||
|
microOps[i] =
|
||||||
|
new MicroLdrRetUop(machInst, regIdx,
|
||||||
|
INTREG_UREG0, up, addr);
|
||||||
|
} else {
|
||||||
|
microOps[i] =
|
||||||
|
new MicroLdrUop(machInst, regIdx, INTREG_UREG0, up, addr);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
microOps[i] =
|
||||||
|
new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (up)
|
||||||
|
addr += 4;
|
||||||
|
else
|
||||||
|
addr -= 4;
|
||||||
|
}
|
||||||
|
|
||||||
|
StaticInstPtr &lastUop = microOps[numMicroops - 1];
|
||||||
|
if (writeback) {
|
||||||
|
if (up) {
|
||||||
|
lastUop = new MicroAddiUop(machInst, rn, rn, ones * 4);
|
||||||
|
} else {
|
||||||
|
lastUop = new MicroSubiUop(machInst, rn, rn, ones * 4);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
lastUop->setLastMicroop();
|
||||||
|
}
|
||||||
|
|
||||||
|
}};
|
||||||
|
|
||||||
|
def template MacroMemExecute {{
|
||||||
|
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||||
|
{
|
||||||
|
Fault fault = NoFault;
|
||||||
|
|
||||||
|
%(fp_enable_check)s;
|
||||||
|
%(op_decl)s;
|
||||||
|
%(op_rd)s;
|
||||||
|
%(code)s;
|
||||||
|
if (fault == NoFault)
|
||||||
|
{
|
||||||
|
%(op_wb)s;
|
||||||
|
}
|
||||||
|
|
||||||
|
return fault;
|
||||||
|
}
|
||||||
|
}};
|
|
@ -42,3 +42,6 @@
|
||||||
|
|
||||||
//Templates for memory instructions
|
//Templates for memory instructions
|
||||||
##include "mem.isa"
|
##include "mem.isa"
|
||||||
|
|
||||||
|
//Templates for microcoded memory instructions
|
||||||
|
##include "macromem.isa"
|
||||||
|
|
Loading…
Reference in a new issue