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Two fixes to try and get TLB miss cost more in line with real platform:

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1) Add fault_handler_delay param to FullCPU to wait N cycles after
committing faulting instruction before fetching fault handler.
2) Make hw_rei a serializing instruction (flushes pipe, basically).

arch/alpha/isa_desc:
    Make hw_rei a serializing instruction (guarantees previous insts
    complete before hw_rei will issue).

--HG--
extra : convert_revision : 704cef65b3869be9eee724055cedb22114a78359
This commit is contained in:
Steve Reinhardt 2005-03-01 22:32:14 -05:00
parent d9de7c5783
commit 50a4ed87d0
1 changed files with 1 additions and 1 deletions
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2
arch/alpha/isa_desc
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@ -2566,7 +2566,7 @@ decode OPCODE default Unknown::unknown() {
} }
format BasicOperate { format BasicOperate {
0x1e: hw_rei({{ xc->hwrei(); }}); 0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing);
// M5 special opcodes use the reserved 0x01 opcode space // M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC { 0x01: decode M5FUNC {