X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging.
--HG-- extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af
This commit is contained in:
parent
f4a932a6b3
commit
504f90f763
9 changed files with 471 additions and 136 deletions
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@ -88,6 +88,7 @@ Import('*')
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if env['TARGET_ISA'] == 'x86':
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if env['TARGET_ISA'] == 'x86':
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Source('emulenv.cc')
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Source('emulenv.cc')
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Source('floatregfile.cc')
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Source('floatregfile.cc')
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Source('faults.cc')
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Source('insts/microfpop.cc')
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Source('insts/microfpop.cc')
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Source('insts/microldstop.cc')
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Source('insts/microldstop.cc')
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Source('insts/microop.cc')
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Source('insts/microop.cc')
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@ -95,6 +96,7 @@ if env['TARGET_ISA'] == 'x86':
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Source('insts/static_inst.cc')
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Source('insts/static_inst.cc')
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Source('intregfile.cc')
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Source('intregfile.cc')
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Source('miscregfile.cc')
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Source('miscregfile.cc')
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Source('pagetable.cc')
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Source('predecoder.cc')
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Source('predecoder.cc')
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Source('predecoder_tables.cc')
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Source('predecoder_tables.cc')
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Source('regfile.cc')
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Source('regfile.cc')
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@ -58,18 +58,18 @@ from m5.params import *
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class X86TLB(SimObject):
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class X86TLB(SimObject):
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type = 'X86TLB'
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type = 'X86TLB'
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abstract = True
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abstract = True
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#size = Param.Int("TLB size")
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size = Param.Int("TLB size")
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class X86DTB(X86TLB):
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class X86DTB(X86TLB):
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type = 'X86DTB'
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type = 'X86DTB'
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cxx_namespace = 'X86ISA'
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cxx_namespace = 'X86ISA'
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cxx_class = 'DTB'
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cxx_class = 'DTB'
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#size = 64
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size = 64
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class X86ITB(X86TLB):
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class X86ITB(X86TLB):
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type = 'X86ITB'
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type = 'X86ITB'
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cxx_namespace = 'X86ISA'
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cxx_namespace = 'X86ISA'
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cxx_class = 'ITB'
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cxx_class = 'ITB'
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#size = 64
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size = 64
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171
src/arch/x86/faults.cc
Normal file
171
src/arch/x86/faults.cc
Normal file
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@ -0,0 +1,171 @@
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/*
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* Copyright (c) 2003-2007 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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|
* modification, are permitted provided that the following conditions are
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|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
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||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
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||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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|
*
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* Authors: Gabe Black
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*/
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/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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|
*
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|
* Redistribution and use of this software in source and binary forms,
|
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|
* with or without modification, are permitted provided that the
|
||||||
|
* following conditions are met:
|
||||||
|
*
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||||||
|
* The software must be used only for Non-Commercial Use which means any
|
||||||
|
* use which is NOT directed to receiving any direct monetary
|
||||||
|
* compensation for, or commercial advantage from such use. Illustrative
|
||||||
|
* examples of non-commercial use are academic research, personal study,
|
||||||
|
* teaching, education and corporate research & development.
|
||||||
|
* Illustrative examples of commercial use are distributing products for
|
||||||
|
* commercial advantage and providing services using the software for
|
||||||
|
* commercial advantage.
|
||||||
|
*
|
||||||
|
* If you wish to use this software or functionality therein that may be
|
||||||
|
* covered by patents for commercial use, please contact:
|
||||||
|
* Director of Intellectual Property Licensing
|
||||||
|
* Office of Strategy and Technology
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||||||
|
* Hewlett-Packard Company
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||||||
|
* 1501 Page Mill Road
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|
* Palo Alto, California 94304
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|
*
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||||||
|
* Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer. Redistributions
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||||||
|
* in binary form must reproduce the above copyright notice, this list of
|
||||||
|
* conditions and the following disclaimer in the documentation and/or
|
||||||
|
* other materials provided with the distribution. Neither the name of
|
||||||
|
* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission. No right of
|
||||||
|
* sublicense is granted herewith. Derivatives of the software and
|
||||||
|
* output created using the software may be prepared, but only for
|
||||||
|
* Non-Commercial Uses. Derivatives of the software may be shared with
|
||||||
|
* others provided: (i) the others agree to abide by the list of
|
||||||
|
* conditions herein which includes the Non-Commercial Use restrictions;
|
||||||
|
* and (ii) such Derivatives of the software include the above copyright
|
||||||
|
* notice to acknowledge the contribution from this software where
|
||||||
|
* applicable, this list of conditions and the disclaimer below.
|
||||||
|
*
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||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/x86/faults.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#if !FULL_SYSTEM
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#include "arch/x86/isa_traits.hh"
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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#endif
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namespace X86ISA
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{
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#if FULL_SYSTEM
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void X86Trap::invoke(TheeadContext * tc)
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{
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panic("X86 faults are not implemented!");
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}
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void X86Abort::invoke(TheeadContext * tc)
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{
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panic("X86 faults are not implemented!");
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}
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void X86Interrupt::invoke(TheeadContext * tc)
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{
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panic("X86 faults are not implemented!");
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}
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#else // !FULL_SYSTEM
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void FakeITLBFault::invoke(ThreadContext * tc)
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{
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DPRINTF(TLB, "Invoking an ITLB fault for address %#x at pc %#x.\n",
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vaddr, tc->readPC());
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Process *p = tc->getProcessPtr();
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Addr paddr;
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bool success = p->pTable->translate(vaddr, paddr);
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if(!success) {
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panic("Tried to execute unmapped address %#x.\n", vaddr);
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} else {
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TlbEntry entry;
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entry.pageStart = p->pTable->pageAlign(paddr);
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entry.writeable = false;
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entry.user = true;
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entry.uncacheable = false;
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entry.global = false;
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entry.patBit = 0;
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entry.noExec = false;
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entry.size = PageBytes;
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Addr alignedVaddr = p->pTable->pageAlign(vaddr);
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DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
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tc->getITBPtr()->insert(alignedVaddr, entry);
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}
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}
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void FakeDTLBFault::invoke(ThreadContext * tc)
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{
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DPRINTF(TLB, "Invoking an DTLB fault for address %#x at pc %#x.\n",
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vaddr, tc->readPC());
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Process *p = tc->getProcessPtr();
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Addr paddr;
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bool success = p->pTable->translate(vaddr, paddr);
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if(!success) {
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p->checkAndAllocNextPage(vaddr);
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success = p->pTable->translate(vaddr, paddr);
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}
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if(!success) {
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panic("Tried to access unmapped address %#x.\n", vaddr);
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} else {
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TlbEntry entry;
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entry.pageStart = p->pTable->pageAlign(paddr);
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entry.writeable = true;
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entry.user = true;
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entry.uncacheable = false;
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entry.global = false;
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entry.patBit = 0;
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entry.noExec = true;
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entry.size = PageBytes;
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Addr alignedVaddr = p->pTable->pageAlign(vaddr);
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DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
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tc->getDTBPtr()->insert(alignedVaddr, entry);
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}
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}
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#endif
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} // namespace X86ISA
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@ -111,10 +111,7 @@ namespace X86ISA
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{}
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{}
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc)
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void invoke(ThreadContext * tc);
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{
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panic("X86 faults are not implemented!");
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}
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#endif
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#endif
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};
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};
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@ -127,10 +124,7 @@ namespace X86ISA
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{}
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{}
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc)
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void invoke(ThreadContext * tc);
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{
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panic("X86 faults are not implemented!");
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}
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#endif
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#endif
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};
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};
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@ -143,10 +137,7 @@ namespace X86ISA
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{}
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{}
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc)
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void invoke(ThreadContext * tc);
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{
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panic("X86 faults are not implemented!");
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}
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#endif
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#endif
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};
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};
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@ -372,18 +363,44 @@ namespace X86ISA
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// the tlb on a miss and are to take the place of a hardware table walker.
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// the tlb on a miss and are to take the place of a hardware table walker.
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class FakeITLBFault : public X86Fault
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class FakeITLBFault : public X86Fault
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{
|
{
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|
#if !FULL_SYSTEM
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protected:
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Addr vaddr;
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public:
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FakeITLBFault(Addr _vaddr) :
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X86Fault("fake instruction tlb fault", "itlb"),
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vaddr(_vaddr)
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#else
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public:
|
public:
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FakeITLBFault() :
|
FakeITLBFault() :
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X86Fault("fake instruction tlb fault", "itlb")
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X86Fault("fake instruction tlb fault", "itlb")
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#endif
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{}
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{}
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#if !FULL_SYSTEM
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void invoke(ThreadContext * tc);
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|
#endif
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};
|
};
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|
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class FakeDTLBFault : public X86Fault
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class FakeDTLBFault : public X86Fault
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{
|
{
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|
#if !FULL_SYSTEM
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|
protected:
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Addr vaddr;
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public:
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FakeDTLBFault(Addr _vaddr) :
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X86Fault("fake data tlb fault", "dtlb"),
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|
vaddr(_vaddr)
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|
#else
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public:
|
public:
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FakeDTLBFault() :
|
FakeDTLBFault() :
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X86Fault("fake data tlb fault", "dtlb")
|
X86Fault("fake data tlb fault", "dtlb")
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|
#endif
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{}
|
{}
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|
|
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|
#if !FULL_SYSTEM
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|
void invoke(ThreadContext * tc);
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|
#endif
|
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};
|
};
|
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};
|
};
|
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|
|
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|
|
74
src/arch/x86/pagetable.cc
Normal file
74
src/arch/x86/pagetable.cc
Normal file
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@ -0,0 +1,74 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2007 The Hewlett-Packard Development Company
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use of this software in source and binary forms,
|
||||||
|
* with or without modification, are permitted provided that the
|
||||||
|
* following conditions are met:
|
||||||
|
*
|
||||||
|
* The software must be used only for Non-Commercial Use which means any
|
||||||
|
* use which is NOT directed to receiving any direct monetary
|
||||||
|
* compensation for, or commercial advantage from such use. Illustrative
|
||||||
|
* examples of non-commercial use are academic research, personal study,
|
||||||
|
* teaching, education and corporate research & development.
|
||||||
|
* Illustrative examples of commercial use are distributing products for
|
||||||
|
* commercial advantage and providing services using the software for
|
||||||
|
* commercial advantage.
|
||||||
|
*
|
||||||
|
* If you wish to use this software or functionality therein that may be
|
||||||
|
* covered by patents for commercial use, please contact:
|
||||||
|
* Director of Intellectual Property Licensing
|
||||||
|
* Office of Strategy and Technology
|
||||||
|
* Hewlett-Packard Company
|
||||||
|
* 1501 Page Mill Road
|
||||||
|
* Palo Alto, California 94304
|
||||||
|
*
|
||||||
|
* Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer. Redistributions
|
||||||
|
* in binary form must reproduce the above copyright notice, this list of
|
||||||
|
* conditions and the following disclaimer in the documentation and/or
|
||||||
|
* other materials provided with the distribution. Neither the name of
|
||||||
|
* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission. No right of
|
||||||
|
* sublicense is granted herewith. Derivatives of the software and
|
||||||
|
* output created using the software may be prepared, but only for
|
||||||
|
* Non-Commercial Uses. Derivatives of the software may be shared with
|
||||||
|
* others provided: (i) the others agree to abide by the list of
|
||||||
|
* conditions herein which includes the Non-Commercial Use restrictions;
|
||||||
|
* and (ii) such Derivatives of the software include the above copyright
|
||||||
|
* notice to acknowledge the contribution from this software where
|
||||||
|
* applicable, this list of conditions and the disclaimer below.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Gabe Black
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "arch/x86/pagetable.hh"
|
||||||
|
#include "sim/serialize.hh"
|
||||||
|
|
||||||
|
namespace X86ISA
|
||||||
|
{
|
||||||
|
|
||||||
|
void
|
||||||
|
TlbEntry::serialize(std::ostream &os)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
TlbEntry::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
|
@ -58,9 +58,14 @@
|
||||||
#ifndef __ARCH_X86_PAGETABLE_HH__
|
#ifndef __ARCH_X86_PAGETABLE_HH__
|
||||||
#define __ARCH_X86_PAGETABLE_HH__
|
#define __ARCH_X86_PAGETABLE_HH__
|
||||||
|
|
||||||
|
#include <iostream>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
#include "sim/host.hh"
|
#include "sim/host.hh"
|
||||||
#include "base/misc.hh"
|
#include "base/misc.hh"
|
||||||
|
|
||||||
|
class Checkpoint;
|
||||||
|
|
||||||
namespace X86ISA
|
namespace X86ISA
|
||||||
{
|
{
|
||||||
struct VAddr
|
struct VAddr
|
||||||
|
@ -68,8 +73,37 @@ namespace X86ISA
|
||||||
VAddr(Addr a) { panic("not implemented yet."); }
|
VAddr(Addr a) { panic("not implemented yet."); }
|
||||||
};
|
};
|
||||||
|
|
||||||
class PageTableEntry
|
struct TlbEntry
|
||||||
{
|
{
|
||||||
|
// The base of the physical page.
|
||||||
|
Addr pageStart;
|
||||||
|
// Read permission is always available, assuming it isn't blocked by
|
||||||
|
// other mechanisms.
|
||||||
|
bool writeable;
|
||||||
|
// Whether this page is accesible without being in supervisor mode.
|
||||||
|
bool user;
|
||||||
|
// Whether to use write through or write back. M5 ignores this and
|
||||||
|
// lets the caches handle the writeback policy.
|
||||||
|
//bool pwt;
|
||||||
|
// Whether the page is cacheable or not.
|
||||||
|
bool uncacheable;
|
||||||
|
// Whether or not to kick this page out on a write to CR3.
|
||||||
|
bool global;
|
||||||
|
// A bit used to form an index into the PAT table.
|
||||||
|
bool patBit;
|
||||||
|
// Whether or not memory on this page can be executed.
|
||||||
|
bool noExec;
|
||||||
|
|
||||||
|
// The beginning of the virtual page this entry maps.
|
||||||
|
Addr vaddr;
|
||||||
|
// The size of the page this entry represents.
|
||||||
|
Addr size;
|
||||||
|
|
||||||
|
TlbEntry() {}
|
||||||
|
TlbEntry(Addr paddr) : pageStart(paddr) {}
|
||||||
|
|
||||||
|
void serialize(std::ostream &os);
|
||||||
|
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -59,8 +59,7 @@
|
||||||
|
|
||||||
#include "config/full_system.hh"
|
#include "config/full_system.hh"
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#include "arch/x86/pagetable.hh"
|
||||||
|
|
||||||
#include "arch/x86/tlb.hh"
|
#include "arch/x86/tlb.hh"
|
||||||
#include "base/bitfield.hh"
|
#include "base/bitfield.hh"
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
|
@ -72,21 +71,114 @@
|
||||||
|
|
||||||
namespace X86ISA {
|
namespace X86ISA {
|
||||||
|
|
||||||
TLB::TLB(const Params *p) : SimObject(p)
|
TLB::TLB(const Params *p) : SimObject(p), size(p->size)
|
||||||
|
{
|
||||||
|
tlb = new TlbEntry[size];
|
||||||
|
std::memset(tlb, 0, sizeof(TlbEntry) * size);
|
||||||
|
|
||||||
|
for (int x = 0; x < size; x++)
|
||||||
|
freeList.push_back(&tlb[x]);
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
TLB::insert(Addr vpn, TlbEntry &entry)
|
||||||
|
{
|
||||||
|
//TODO Deal with conflicting entries
|
||||||
|
|
||||||
|
TlbEntry *newEntry = NULL;
|
||||||
|
if (!freeList.empty()) {
|
||||||
|
newEntry = freeList.front();
|
||||||
|
freeList.pop_front();
|
||||||
|
} else {
|
||||||
|
newEntry = entryList.back();
|
||||||
|
entryList.pop_back();
|
||||||
|
}
|
||||||
|
*newEntry = entry;
|
||||||
|
newEntry->vaddr = vpn;
|
||||||
|
entryList.push_front(newEntry);
|
||||||
|
}
|
||||||
|
|
||||||
|
TlbEntry *
|
||||||
|
TLB::lookup(Addr va, bool update_lru)
|
||||||
|
{
|
||||||
|
//TODO make this smarter at some point
|
||||||
|
EntryList::iterator entry;
|
||||||
|
for (entry = entryList.begin(); entry != entryList.end(); entry++) {
|
||||||
|
if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
|
||||||
|
DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
|
||||||
|
"with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
|
||||||
|
TlbEntry *e = *entry;
|
||||||
|
if (update_lru) {
|
||||||
|
entryList.erase(entry);
|
||||||
|
entryList.push_front(e);
|
||||||
|
}
|
||||||
|
return e;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
TLB::invalidateAll()
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
TLB::invalidateNonGlobal()
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
TLB::demapPage(Addr va)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
Fault
|
Fault
|
||||||
ITB::translate(RequestPtr &req, ThreadContext *tc)
|
ITB::translate(RequestPtr &req, ThreadContext *tc)
|
||||||
{
|
{
|
||||||
|
Addr vaddr = req->getVaddr();
|
||||||
|
// Check against the limit of the CS segment, and permissions.
|
||||||
|
// The vaddr already has the segment base applied.
|
||||||
|
TlbEntry *entry = lookup(vaddr);
|
||||||
|
if (!entry) {
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
return new FakeITLBFault();
|
||||||
|
#else
|
||||||
|
return new FakeITLBFault(vaddr);
|
||||||
|
#endif
|
||||||
|
} else {
|
||||||
|
Addr paddr = entry->pageStart | (vaddr & mask(12));
|
||||||
|
DPRINTF(TLB, "Translated %#x to %#x\n", vaddr, paddr);
|
||||||
|
req->setPaddr(paddr);
|
||||||
|
}
|
||||||
|
|
||||||
return NoFault;
|
return NoFault;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Fault
|
Fault
|
||||||
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
|
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
|
||||||
{
|
{
|
||||||
|
Addr vaddr = req->getVaddr();
|
||||||
|
uint32_t flags = req->getFlags();
|
||||||
|
bool storeCheck = flags & StoreCheck;
|
||||||
|
int seg = flags & (mask(NUM_SEGMENTREGS));
|
||||||
|
|
||||||
|
//XXX Junk code to surpress the warning
|
||||||
|
if (storeCheck) seg = seg;
|
||||||
|
|
||||||
|
// Check the limit of the segment "seg", and permissions.
|
||||||
|
// The vaddr already has the segment base applied.
|
||||||
|
TlbEntry *entry = lookup(vaddr);
|
||||||
|
if (!entry) {
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
return new FakeDTLBFault();
|
||||||
|
#else
|
||||||
|
return new FakeDTLBFault(vaddr);
|
||||||
|
#endif
|
||||||
|
} else {
|
||||||
|
Addr paddr = entry->pageStart | (vaddr & mask(12));
|
||||||
|
req->setPaddr(paddr);
|
||||||
|
}
|
||||||
return NoFault;
|
return NoFault;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -130,31 +222,6 @@ DTB::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
|
|
||||||
/* end namespace X86ISA */ }
|
/* end namespace X86ISA */ }
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
#include <cstring>
|
|
||||||
|
|
||||||
#include "arch/x86/tlb.hh"
|
|
||||||
#include "params/X86DTB.hh"
|
|
||||||
#include "params/X86ITB.hh"
|
|
||||||
#include "sim/serialize.hh"
|
|
||||||
|
|
||||||
namespace X86ISA {
|
|
||||||
void
|
|
||||||
TlbEntry::serialize(std::ostream &os)
|
|
||||||
{
|
|
||||||
SERIALIZE_SCALAR(pageStart);
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
|
||||||
TlbEntry::unserialize(Checkpoint *cp, const std::string §ion)
|
|
||||||
{
|
|
||||||
UNSERIALIZE_SCALAR(pageStart);
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
X86ISA::ITB *
|
X86ISA::ITB *
|
||||||
X86ITBParams::create()
|
X86ITBParams::create()
|
||||||
{
|
{
|
||||||
|
|
|
@ -58,11 +58,11 @@
|
||||||
#ifndef __ARCH_X86_TLB_HH__
|
#ifndef __ARCH_X86_TLB_HH__
|
||||||
#define __ARCH_X86_TLB_HH__
|
#define __ARCH_X86_TLB_HH__
|
||||||
|
|
||||||
|
#include <list>
|
||||||
|
|
||||||
|
#include "arch/x86/pagetable.hh"
|
||||||
|
#include "arch/x86/segmentregs.hh"
|
||||||
#include "config/full_system.hh"
|
#include "config/full_system.hh"
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
|
|
||||||
#include "arch/segmentregs.hh"
|
|
||||||
#include "mem/request.hh"
|
#include "mem/request.hh"
|
||||||
#include "params/X86DTB.hh"
|
#include "params/X86DTB.hh"
|
||||||
#include "params/X86ITB.hh"
|
#include "params/X86ITB.hh"
|
||||||
|
@ -76,102 +76,75 @@ namespace X86ISA
|
||||||
{
|
{
|
||||||
static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
|
static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
|
||||||
|
|
||||||
struct TlbEntry
|
class TLB : public SimObject
|
||||||
{
|
{
|
||||||
Addr pageStart;
|
#if !FULL_SYSTEM
|
||||||
TlbEntry() {}
|
protected:
|
||||||
TlbEntry(Addr paddr) : pageStart(paddr) {}
|
friend class FakeITLBFault;
|
||||||
|
friend class FakeDTLBFault;
|
||||||
|
#endif
|
||||||
|
public:
|
||||||
|
typedef X86TLBParams Params;
|
||||||
|
TLB(const Params *p);
|
||||||
|
|
||||||
void serialize(std::ostream &os);
|
void dumpAll();
|
||||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
|
||||||
|
TlbEntry *lookup(Addr va, bool update_lru = true);
|
||||||
|
|
||||||
|
protected:
|
||||||
|
int size;
|
||||||
|
|
||||||
|
TlbEntry * tlb;
|
||||||
|
|
||||||
|
typedef std::list<TlbEntry *> EntryList;
|
||||||
|
EntryList freeList;
|
||||||
|
EntryList entryList;
|
||||||
|
|
||||||
|
void insert(Addr vpn, TlbEntry &entry);
|
||||||
|
|
||||||
|
void invalidateAll();
|
||||||
|
|
||||||
|
void invalidateNonGlobal();
|
||||||
|
|
||||||
|
void demapPage(Addr va);
|
||||||
|
|
||||||
|
public:
|
||||||
|
// Checkpointing
|
||||||
|
virtual void serialize(std::ostream &os);
|
||||||
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
};
|
};
|
||||||
|
|
||||||
class TLB : public SimObject
|
class ITB : public TLB
|
||||||
{
|
|
||||||
public:
|
|
||||||
typedef X86TLBParams Params;
|
|
||||||
TLB(const Params *p);
|
|
||||||
|
|
||||||
void dumpAll();
|
|
||||||
|
|
||||||
// Checkpointing
|
|
||||||
virtual void serialize(std::ostream &os);
|
|
||||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
|
||||||
};
|
|
||||||
|
|
||||||
class ITB : public TLB
|
|
||||||
{
|
|
||||||
public:
|
|
||||||
typedef X86ITBParams Params;
|
|
||||||
ITB(const Params *p) : TLB(p)
|
|
||||||
{
|
{
|
||||||
}
|
public:
|
||||||
|
typedef X86ITBParams Params;
|
||||||
|
ITB(const Params *p) : TLB(p)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
Fault translate(RequestPtr &req, ThreadContext *tc);
|
Fault translate(RequestPtr &req, ThreadContext *tc);
|
||||||
|
|
||||||
friend class DTB;
|
friend class DTB;
|
||||||
};
|
};
|
||||||
|
|
||||||
class DTB : public TLB
|
class DTB : public TLB
|
||||||
{
|
|
||||||
public:
|
|
||||||
typedef X86DTBParams Params;
|
|
||||||
DTB(const Params *p) : TLB(p)
|
|
||||||
{
|
{
|
||||||
}
|
public:
|
||||||
|
typedef X86DTBParams Params;
|
||||||
|
DTB(const Params *p) : TLB(p)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
|
Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
|
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
|
||||||
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
|
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// Checkpointing
|
// Checkpointing
|
||||||
virtual void serialize(std::ostream &os);
|
virtual void serialize(std::ostream &os);
|
||||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
};
|
};
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
#include <iostream>
|
|
||||||
|
|
||||||
#include "arch/x86/segmentregs.hh"
|
|
||||||
#include "sim/host.hh"
|
|
||||||
#include "sim/tlb.hh"
|
|
||||||
|
|
||||||
class Checkpoint;
|
|
||||||
|
|
||||||
namespace X86ISA
|
|
||||||
{
|
|
||||||
static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
|
|
||||||
|
|
||||||
struct TlbEntry
|
|
||||||
{
|
|
||||||
Addr pageStart;
|
|
||||||
TlbEntry() {}
|
|
||||||
TlbEntry(Addr paddr) : pageStart(paddr) {}
|
|
||||||
|
|
||||||
void serialize(std::ostream &os);
|
|
||||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
|
||||||
};
|
|
||||||
|
|
||||||
class ITB : public GenericTLB
|
|
||||||
{
|
|
||||||
public:
|
|
||||||
ITB(const Params *p) : GenericTLB(p)
|
|
||||||
{}
|
|
||||||
};
|
|
||||||
|
|
||||||
class DTB : public GenericTLB
|
|
||||||
{
|
|
||||||
public:
|
|
||||||
DTB(const Params *p) : GenericTLB(p)
|
|
||||||
{}
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif // __ARCH_X86_TLB_HH__
|
#endif // __ARCH_X86_TLB_HH__
|
||||||
|
|
|
@ -68,9 +68,6 @@ class FunctionalPort;
|
||||||
namespace X86ISA
|
namespace X86ISA
|
||||||
{
|
{
|
||||||
|
|
||||||
PageTableEntry
|
|
||||||
kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, X86ISA::VAddr vaddr);
|
|
||||||
|
|
||||||
Addr vtophys(Addr vaddr);
|
Addr vtophys(Addr vaddr);
|
||||||
Addr vtophys(ThreadContext *tc, Addr vaddr);
|
Addr vtophys(ThreadContext *tc, Addr vaddr);
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue