arm: invalidate TLB miscreg cache on modification of HSCTLR
Change-Id: I5212c91c56435fe008950ed99feacc6921609226
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1 changed files with 2 additions and 1 deletions
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2010-2015 ARM Limited
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* Copyright (c) 2010-2016 ARM Limited
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* All rights reserved
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* All rights reserved
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*
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*
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* The license below extends only to copyright in the software and shall
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* The license below extends only to copyright in the software and shall
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@ -1629,6 +1629,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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case MISCREG_TCR_EL3:
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case MISCREG_TCR_EL3:
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case MISCREG_SCTLR_EL2:
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case MISCREG_SCTLR_EL2:
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case MISCREG_SCTLR_EL3:
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case MISCREG_SCTLR_EL3:
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case MISCREG_HSCTLR:
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case MISCREG_TTBR0_EL1:
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case MISCREG_TTBR0_EL1:
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case MISCREG_TTBR1_EL1:
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case MISCREG_TTBR1_EL1:
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case MISCREG_TTBR0_EL2:
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case MISCREG_TTBR0_EL2:
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