Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : 8d61b474428d494b1a5382e4cf95934ad54e35dd
This commit is contained in:
commit
4fbbb74a5c
1 changed files with 12 additions and 3 deletions
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@ -290,6 +290,8 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
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// memory system takes ownership of packet
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dcache_pkt = NULL;
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}
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} else {
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delete req;
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}
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// This will need a new way to tell if it has a dcache attached.
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@ -375,6 +377,8 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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dcache_pkt = NULL;
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}
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}
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} else {
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delete req;
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}
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// This will need a new way to tell if it's hooked up to a cache or not.
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@ -457,6 +461,8 @@ TimingSimpleCPU::fetch()
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ifetch_pkt = NULL;
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}
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} else {
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delete ifetch_req;
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delete ifetch_pkt;
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// fetch fault: advance directly to next instruction (fault handler)
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advanceInst(fault);
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}
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@ -490,13 +496,13 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
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_status = Running;
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delete pkt->req;
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delete pkt;
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numCycles += curTick - previousTick;
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previousTick = curTick;
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if (getState() == SimObject::Draining) {
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delete pkt->req;
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delete pkt;
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completeDrain();
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return;
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}
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@ -528,6 +534,9 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
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postExecute();
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advanceInst(fault);
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}
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delete pkt->req;
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delete pkt;
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}
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void
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