ARM: Decode the scalar saturating add/subtract instructions.
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@ -116,12 +116,7 @@ format DataOp {
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0x3: decode OPCODE {
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0x3: decode OPCODE {
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0x9: ArmBlxReg::armBlxReg();
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0x9: ArmBlxReg::armBlxReg();
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}
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}
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0x5: decode OPCODE {
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0x5: ArmSatAddSub::armSatAddSub();
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0x8: WarnUnimpl::qadd();
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0x9: WarnUnimpl::qsub();
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0xa: WarnUnimpl::qdadd();
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0xb: WarnUnimpl::qdsub();
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}
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}
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}
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0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
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0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
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}
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}
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@ -341,6 +341,28 @@ def format ArmDataProcImm() {{
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'''
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'''
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}};
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}};
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def format ArmSatAddSub() {{
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decode_block = '''
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{
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IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
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IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
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IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
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switch (OPCODE) {
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case 0x8:
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return new QaddRegCc(machInst, rd, rm, rn, 0, LSL);
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case 0x9:
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return new QsubRegCc(machInst, rd, rm, rn, 0, LSL);
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case 0xa:
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return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL);
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case 0xb:
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return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL);
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default:
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return new Unknown(machInst);
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}
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}
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'''
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}};
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def format Thumb16ShiftAddSubMoveCmp() {{
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def format Thumb16ShiftAddSubMoveCmp() {{
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decode_block = '''
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decode_block = '''
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{
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{
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