stats: update stats for insts/ops and master id changes
This commit is contained in:
Ali Saidi
parent
542d0ceebc
commit
4f8d1a4cef
403 changed files with 29252 additions and 23559 deletions
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@ -11,14 +11,14 @@ type=LinuxAlphaSystem
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children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
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boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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console=/scratch/nilay/GEM5/system/binaries/console
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console=/dist/m5/system/binaries/console
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init_param=0
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kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
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kernel=/dist/m5/system/binaries/vmlinux
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load_addr_mask=1099511627775
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mem_mode=timing
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memories=system.physmem
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num_work_ids=16
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pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
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pal=/dist/m5/system/binaries/ts_osfpal
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physmem=system.physmem
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readfile=tests/halt.sh
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symbolfile=
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@ -152,20 +152,13 @@ is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=4
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num_cpus=1
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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size=32768
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subblock_size=0
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system=system
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tgts_per_mshr=20
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trace_addr=0
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two_queue=false
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@ -451,20 +444,13 @@ is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=4
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num_cpus=1
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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size=32768
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subblock_size=0
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system=system
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tgts_per_mshr=20
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trace_addr=0
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two_queue=false
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@ -590,20 +576,13 @@ is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=4
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num_cpus=1
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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size=32768
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subblock_size=0
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system=system
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tgts_per_mshr=20
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trace_addr=0
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two_queue=false
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@ -889,20 +868,13 @@ is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=4
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num_cpus=1
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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size=32768
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subblock_size=0
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system=system
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tgts_per_mshr=20
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trace_addr=0
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two_queue=false
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@ -937,7 +909,7 @@ table_size=65536
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[system.disk0.image.child]
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type=RawDiskImage
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image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
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image_file=/dist/m5/system/disks/linux-latest.img
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read_only=true
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[system.disk2]
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@ -957,7 +929,7 @@ table_size=65536
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[system.disk2.image.child]
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type=RawDiskImage
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image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
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image_file=/dist/m5/system/disks/linux-bigswap2.img
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read_only=true
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[system.intrctrl]
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@ -986,20 +958,13 @@ is_top_level=true
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latency=50000
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max_miss_count=0
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mshrs=20
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num_cpus=1
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=500000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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size=1024
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subblock_size=0
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system=system
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tgts_per_mshr=12
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trace_addr=0
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two_queue=false
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@ -1018,20 +983,13 @@ is_top_level=false
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latency=10000
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max_miss_count=0
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mshrs=92
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num_cpus=2
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=100000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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size=4194304
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subblock_size=0
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system=system
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tgts_per_mshr=16
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trace_addr=0
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two_queue=false
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@ -1085,7 +1043,7 @@ system=system
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[system.simple_disk.disk]
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type=RawDiskImage
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image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
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image_file=/dist/m5/system/disks/linux-latest.img
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read_only=true
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[system.terminal]
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@ -1,15 +1,12 @@
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Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
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Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Feb 3 2012 13:46:22
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gem5 started Feb 3 2012 13:46:34
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gem5 executing on ribera.cs.wisc.edu
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
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gem5 compiled Feb 11 2012 13:05:17
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gem5 started Feb 11 2012 13:47:49
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
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Global frequency set at 1000000000000 ticks per second
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0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
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info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
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info: kernel located at: /dist/m5/system/binaries/vmlinux
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info: Entering event queue @ 0. Starting simulation...
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info: Launching CPU 1 @ 106949500
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Exiting @ tick 1897464893500 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -11,14 +11,14 @@ type=LinuxAlphaSystem
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children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
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boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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console=/scratch/nilay/GEM5/system/binaries/console
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console=/dist/m5/system/binaries/console
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init_param=0
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kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
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kernel=/dist/m5/system/binaries/vmlinux
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load_addr_mask=1099511627775
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mem_mode=timing
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memories=system.physmem
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num_work_ids=16
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pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
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pal=/dist/m5/system/binaries/ts_osfpal
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physmem=system.physmem
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readfile=tests/halt.sh
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symbolfile=
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@ -152,20 +152,13 @@ is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=4
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num_cpus=1
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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size=32768
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subblock_size=0
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system=system
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tgts_per_mshr=20
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trace_addr=0
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two_queue=false
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@ -451,20 +444,13 @@ is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=4
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num_cpus=1
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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size=32768
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subblock_size=0
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system=system
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tgts_per_mshr=20
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trace_addr=0
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two_queue=false
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@ -499,7 +485,7 @@ table_size=65536
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[system.disk0.image.child]
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type=RawDiskImage
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image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
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image_file=/dist/m5/system/disks/linux-latest.img
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read_only=true
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[system.disk2]
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@ -519,7 +505,7 @@ table_size=65536
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[system.disk2.image.child]
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type=RawDiskImage
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image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
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image_file=/dist/m5/system/disks/linux-bigswap2.img
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read_only=true
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[system.intrctrl]
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@ -548,20 +534,13 @@ is_top_level=true
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latency=50000
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max_miss_count=0
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mshrs=20
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num_cpus=1
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=500000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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size=1024
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subblock_size=0
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system=system
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tgts_per_mshr=12
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trace_addr=0
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two_queue=false
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@ -580,20 +559,13 @@ is_top_level=false
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latency=10000
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max_miss_count=0
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mshrs=92
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num_cpus=1
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=100000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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size=4194304
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subblock_size=0
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system=system
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tgts_per_mshr=16
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trace_addr=0
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two_queue=false
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@ -647,7 +619,7 @@ system=system
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[system.simple_disk.disk]
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type=RawDiskImage
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image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
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image_file=/dist/m5/system/disks/linux-latest.img
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read_only=true
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[system.terminal]
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@ -1,14 +1,11 @@
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Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
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Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Feb 3 2012 13:46:22
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gem5 started Feb 3 2012 13:46:34
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gem5 executing on ribera.cs.wisc.edu
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
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gem5 compiled Feb 11 2012 13:05:17
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gem5 started Feb 11 2012 13:47:47
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3
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Global frequency set at 1000000000000 ticks per second
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0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
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info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
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info: kernel located at: /dist/m5/system/binaries/vmlinux
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 1859850554500 because m5_exit instruction encountered
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@ -4,11 +4,13 @@ sim_seconds 1.859851 # Nu
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sim_ticks 1859850554500 # Number of ticks simulated
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final_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 100457 # Simulator instruction rate (inst/s)
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host_tick_rate 3519496587 # Simulator tick rate (ticks/s)
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host_mem_usage 323652 # Number of bytes of host memory used
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host_seconds 528.44 # Real time elapsed on the host
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host_inst_rate 188989 # Simulator instruction rate (inst/s)
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host_op_rate 188989 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 6621174751 # Simulator tick rate (ticks/s)
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host_mem_usage 292896 # Number of bytes of host memory used
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host_seconds 280.89 # Real time elapsed on the host
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sim_insts 53085804 # Number of instructions simulated
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sim_ops 53085804 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 29820864 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 10193536 # Number of bytes written to this memory
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@ -25,83 +27,89 @@ system.l2c.total_refs 2406767 # To
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system.l2c.sampled_refs 424249 # Sample count of references to valid blocks.
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system.l2c.avg_refs 5.673006 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::0 12305.465353 # Average occupied blocks per context
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system.l2c.occ_blocks::1 22620.354669 # Average occupied blocks per context
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system.l2c.occ_percent::0 0.187767 # Average percentage of cache occupancy
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system.l2c.occ_percent::1 0.345159 # Average percentage of cache occupancy
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system.l2c.ReadReq_hits::0 1800764 # number of ReadReq hits
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system.l2c.occ_blocks::writebacks 22620.354669 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu.inst 4081.669847 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu.data 8223.795506 # Average occupied blocks per requestor
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system.l2c.occ_percent::writebacks 0.345159 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu.inst 0.062281 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu.data 0.125485 # Average percentage of cache occupancy
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system.l2c.occ_percent::total 0.532926 # Average percentage of cache occupancy
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system.l2c.ReadReq_hits::cpu.inst 988583 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu.data 812181 # number of ReadReq hits
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system.l2c.ReadReq_hits::total 1800764 # number of ReadReq hits
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system.l2c.Writeback_hits::0 835189 # number of Writeback hits
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system.l2c.Writeback_hits::writebacks 835189 # number of Writeback hits
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system.l2c.Writeback_hits::total 835189 # number of Writeback hits
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system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::0 183241 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 183241 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 183241 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::0 1984005 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 988583 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 995422 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1984005 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::0 1984005 # number of overall hits
|
||||
system.l2c.overall_hits::1 0 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 988583 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 995422 # number of overall hits
|
||||
system.l2c.overall_hits::total 1984005 # number of overall hits
|
||||
system.l2c.ReadReq_misses::0 308137 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 16626 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 291511 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 308137 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::0 35 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 35 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::0 116889 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 116889 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 116889 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::0 425026 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 16626 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 408400 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 425026 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::0 425026 # number of overall misses
|
||||
system.l2c.overall_misses::1 0 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 16626 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 408400 # number of overall misses
|
||||
system.l2c.overall_misses::total 425026 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency 16037812500 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency 424500 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency 6132457500 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency 22170270000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency 22170270000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::0 2108901 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 869674000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 15168138500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 16037812500 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 424500 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 424500 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 6132457500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 6132457500 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 869674000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 21300596000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 22170270000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 869674000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 21300596000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 22170270000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.inst 1005209 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 1103692 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2108901 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::0 835189 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 835189 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 835189 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::0 51 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 51 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 51 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::0 300130 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 300130 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 300130 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::0 2409031 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 1005209 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 1403822 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2409031 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::0 2409031 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 1005209 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 1403822 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2409031 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::0 0.146113 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::0 0.686275 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::0 0.389461 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::0 0.176430 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::0 0.176430 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::0 52047.668732 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::0 12128.571429 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::0 52463.940148 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::0 52162.150080 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::0 52162.150080 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.264124 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.686275 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.389461 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.290920 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.290920 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52308.071695 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52032.816943 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 12128.571429 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52463.940148 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -110,48 +118,59 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av
|
|||
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks 117762 # number of writebacks
|
||||
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.l2c.ReadReq_mshr_misses 308137 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses 116889 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses 425026 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses 425026 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.l2c.ReadReq_mshr_miss_latency 12334071500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency 1460000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency 4711233500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency 17045305000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency 17045305000 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency 809589500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency 1114928998 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency 1924518498 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::0 0.146113 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::0 0.686275 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::0 0.389461 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::0 0.176430 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::0 0.176430 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency 40027.882078 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency 41714.285714 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency 40305.191250 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.l2c.writebacks::writebacks 117762 # number of writebacks
|
||||
system.l2c.writebacks::total 117762 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 16626 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 291511 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 308137 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 116889 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 116889 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 16626 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 408400 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 425026 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 16626 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 408400 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 425026 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 666148500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 11667923000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 12334071500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1460000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 1460000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4711233500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 4711233500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 666148500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 16379156500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 17045305000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 666148500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 16379156500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 17045305000 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809589500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 809589500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114928998 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 1114928998 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924518498 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 1924518498 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264124 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.686275 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389461 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.672681 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40025.669700 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41714.285714 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40305.191250 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 41685 # number of replacements
|
||||
system.iocache.tagsinuse 1.276011 # Cycle average of tags in use
|
||||
|
|
@ -159,58 +178,41 @@ system.iocache.total_refs 0 # To
|
|||
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 1708338781000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::1 1.276011 # Average occupied blocks per context
|
||||
system.iocache.occ_percent::1 0.079751 # Average percentage of cache occupancy
|
||||
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
||||
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
||||
system.iocache.overall_hits::0 0 # number of overall hits
|
||||
system.iocache.overall_hits::1 0 # number of overall hits
|
||||
system.iocache.overall_hits::total 0 # number of overall hits
|
||||
system.iocache.ReadReq_misses::1 173 # number of ReadReq misses
|
||||
system.iocache.occ_blocks::tsunami.ide 1.276011 # Average occupied blocks per requestor
|
||||
system.iocache.occ_percent::tsunami.ide 0.079751 # Average percentage of cache occupancy
|
||||
system.iocache.occ_percent::total 0.079751 # Average percentage of cache occupancy
|
||||
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
||||
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::0 0 # number of overall misses
|
||||
system.iocache.overall_misses::1 41725 # number of overall misses
|
||||
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
||||
system.iocache.overall_misses::total 41725 # number of overall misses
|
||||
system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles
|
||||
system.iocache.WriteReq_miss_latency 5721891806 # number of WriteReq miss cycles
|
||||
system.iocache.demand_miss_latency 5741829804 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency 5741829804 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles
|
||||
system.iocache.WriteReq_miss_latency::tsunami.ide 5721891806 # number of WriteReq miss cycles
|
||||
system.iocache.WriteReq_miss_latency::total 5721891806 # number of WriteReq miss cycles
|
||||
system.iocache.demand_miss_latency::tsunami.ide 5741829804 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency::total 5741829804 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency::tsunami.ide 5741829804 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency::total 5741829804 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
|
||||
system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency
|
||||
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
||||
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
|
||||
system.iocache.WriteReq_avg_miss_latency::1 137704.365759 # average WriteReq miss latency
|
||||
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::1 137611.259533 # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::1 137611.259533 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency
|
||||
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.365759 # average WriteReq miss latency
|
||||
system.iocache.demand_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked
|
||||
|
|
@ -219,38 +221,32 @@ system.iocache.avg_blocked_cycles::no_mshrs 6168.215752 #
|
|||
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks 41512 # number of writebacks
|
||||
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
||||
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_latency 3561041984 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency 3571983982 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency 3571983982 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
||||
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
||||
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency 85700.856373 # average WriteReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
||||
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
|
||||
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
|
||||
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
||||
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561041984 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_latency::total 3561041984 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::tsunami.ide 3571983982 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency::total 3571983982 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::tsunami.ide 3571983982 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency::total 3571983982 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
|
||||
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
||||
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85700.856373 # average WriteReq mshr miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
|
|
@ -518,6 +514,7 @@ system.cpu.iew.wb_rate 0.487979 # in
|
|||
system.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 56280196 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted
|
||||
|
|
@ -538,7 +535,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
|
|||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle
|
||||
system.cpu.commit.count 56280196 # Number of instructions committed
|
||||
system.cpu.commit.committedInsts 56280196 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 56280196 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 15504446 # Number of memory references committed
|
||||
system.cpu.commit.loads 9112319 # Number of loads committed
|
||||
|
|
@ -555,6 +553,7 @@ system.cpu.timesIdled 1255783 # Nu
|
|||
system.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
||||
system.cpu.committedInsts 53085804 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 53085804 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 53085804 # Number of Instructions Simulated
|
||||
system.cpu.cpi 2.190256 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads
|
||||
|
|
@ -603,51 +602,39 @@ system.cpu.icache.total_refs 7985769 # To
|
|||
system.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 509.963959 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.996023 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::0 7985770 # number of ReadReq hits
|
||||
system.cpu.icache.occ_blocks::cpu.inst 509.963959 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.996023 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.996023 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 7985770 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::0 7985770 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 7985770 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 7985770 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::0 7985770 # number of overall hits
|
||||
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 7985770 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 7985770 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::0 1065446 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1065446 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::0 1065446 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1065446 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::0 1065446 # number of overall misses
|
||||
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1065446 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1065446 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 15927822494 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 15927822494 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 15927822494 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::0 9051216 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15927822494 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15927822494 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15927822494 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15927822494 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15927822494 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15927822494 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9051216 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::0 9051216 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9051216 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 9051216 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::0 9051216 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 9051216 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::0 0.117713 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::0 0.117713 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::0 0.117713 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::0 14949.441355 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::0 14949.441355 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::0 14949.441355 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117713 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.117713 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.117713 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14949.441355 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 1315496 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked
|
||||
|
|
@ -656,33 +643,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 10871.867769
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 234 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 60134 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 60134 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 60134 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 1005312 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 1005312 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 1005312 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 12047333996 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 12047333996 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 12047333996 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111069 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::0 0.111069 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::0 0.111069 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.676705 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.writebacks::writebacks 234 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 234 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60134 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 60134 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 60134 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 60134 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 60134 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 60134 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1005312 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 1005312 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 1005312 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 1005312 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1005312 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1005312 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12047333996 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12047333996 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12047333996 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12047333996 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12047333996 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12047333996 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.676705 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1403406 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.996008 # Cycle average of tags in use
|
||||
|
|
@ -690,84 +676,69 @@ system.cpu.dcache.total_refs 12086534 # To
|
|||
system.cpu.dcache.sampled_refs 1403918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 8.609145 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 511.996008 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::0 7453772 # number of ReadReq hits
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.996008 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7453772 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7453772 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::0 4220462 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4220462 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 4220462 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::0 192050 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 192050 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 192050 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::0 220033 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 220033 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 220033 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::0 11674234 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 11674234 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 11674234 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::0 11674234 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::1 0 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 11674234 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 11674234 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::0 1809182 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1809182 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1809182 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::0 1936475 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1936475 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1936475 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::0 22599 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22599 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 22599 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::0 3745657 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3745657 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3745657 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::0 3745657 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3745657 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3745657 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 38930236000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 57815325976 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 338636000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 96745561976 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 96745561976 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::0 9262954 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 38930236000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 38930236000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57815325976 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57815325976 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 338636000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 338636000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 28500 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::total 28500 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 96745561976 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 96745561976 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 96745561976 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 96745561976 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9262954 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9262954 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::0 6156937 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6156937 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6156937 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::0 214649 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214649 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 214649 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::0 220035 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 220035 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 220035 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::0 15419891 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15419891 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15419891 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::0 15419891 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15419891 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15419891 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::0 0.195314 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::0 0.314519 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105284 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::0 0.242911 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::0 0.242911 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::0 21518.142453 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.963013 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14984.556839 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::0 25828.729640 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::0 25828.729640 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195314 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314519 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.105284 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.242911 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.242911 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21518.142453 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29855.963013 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14984.556839 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14250 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 920169326 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 212000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 101826 # number of cycles access was blocked
|
||||
|
|
@ -776,57 +747,63 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 9036.683421
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 834955 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 721461 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1637588 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 5103 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 2359049 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 2359049 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1087721 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 298887 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 17496 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 1386608 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 1386608 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 24804888500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 8509686826 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206420500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 33314575326 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 33314575326 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904009500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234178998 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 2138188498 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117427 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048545 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081510 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::0 0.089923 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::0 0.089923 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22804.458588 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28471.251095 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.153864 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 834955 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 834955 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721461 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 721461 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1637588 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1637588 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5103 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5103 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2359049 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2359049 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2359049 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2359049 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1087721 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1087721 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298887 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 298887 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17496 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17496 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1386608 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1386608 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1386608 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1386608 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24804888500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24804888500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509686826 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509686826 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 206420500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 206420500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33314575326 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 33314575326 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33314575326 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 33314575326 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904009500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904009500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234178998 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234178998 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138188498 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138188498 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.117427 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048545 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.081510 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22804.458588 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28471.251095 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11798.153864 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed
|
||||
|
|
|
|||
|
|
@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader_mem=system.nvmem
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
|
|
@ -62,7 +62,7 @@ table_size=65536
|
|||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu0]
|
||||
|
|
@ -173,20 +173,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -481,20 +474,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -629,20 +615,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -937,20 +916,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -1002,20 +974,13 @@ is_top_level=false
|
|||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=500000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -1034,20 +999,13 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
num_cpus=2
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 3 2012 14:00:40
|
||||
gem5 started Feb 3 2012 14:01:00
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
gem5 compiled Feb 11 2012 13:10:40
|
||||
gem5 started Feb 11 2012 16:40:16
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2582494330500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_loader_mem=system.nvmem
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
|
|
@ -62,7 +62,7 @@ table_size=65536
|
|||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -173,20 +173,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -481,20 +474,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -546,20 +532,13 @@ is_top_level=false
|
|||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=500000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -578,20 +557,13 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 3 2012 14:00:40
|
||||
gem5 started Feb 3 2012 14:01:01
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
gem5 compiled Feb 11 2012 13:10:40
|
||||
gem5 started Feb 11 2012 16:39:00
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2503580880500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 2.503581 # Nu
|
|||
sim_ticks 2503580880500 # Number of ticks simulated
|
||||
final_tick 2503580880500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 56444 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1840259079 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 413160 # Number of bytes of host memory used
|
||||
host_seconds 1360.45 # Real time elapsed on the host
|
||||
sim_insts 76789886 # Number of instructions simulated
|
||||
host_inst_rate 80550 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 104045 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3392180683 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 382816 # Number of bytes of host memory used
|
||||
host_seconds 738.04 # Real time elapsed on the host
|
||||
sim_insts 59449329 # Number of instructions simulated
|
||||
sim_ops 76789886 # Number of ops (including micro ops) simulated
|
||||
system.nvmem.bytes_read 64 # Number of bytes read from this memory
|
||||
system.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
|
||||
system.nvmem.bytes_written 0 # Number of bytes written to this memory
|
||||
|
|
@ -34,91 +36,132 @@ system.l2c.total_refs 1795685 # To
|
|||
system.l2c.sampled_refs 150314 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 11.946226 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::0 11478.014025 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 14356.915365 # Average occupied blocks per context
|
||||
system.l2c.occ_percent::0 0.175141 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::1 0.219069 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::0 1349535 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::1 153277 # number of ReadReq hits
|
||||
system.l2c.occ_blocks::writebacks 14304.535648 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.dtb.walker 48.618373 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.itb.walker 3.761343 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.inst 6047.704729 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu.data 5430.309296 # Average occupied blocks per requestor
|
||||
system.l2c.occ_percent::writebacks 0.218270 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.dtb.walker 0.000742 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.inst 0.092281 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::cpu.data 0.082860 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::total 0.394210 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::cpu.dtb.walker 143695 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.itb.walker 9582 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.inst 973305 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu.data 376230 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1502812 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::0 630148 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::writebacks 630148 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 630148 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::0 47 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu.data 47 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::0 17 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu.data 17 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::0 105970 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu.data 105970 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 105970 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::0 1455505 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::1 153277 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.dtb.walker 143695 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.itb.walker 9582 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.inst 973305 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu.data 482200 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1608782 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::0 1455505 # number of overall hits
|
||||
system.l2c.overall_hits::1 153277 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.dtb.walker 143695 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.itb.walker 9582 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.inst 973305 # number of overall hits
|
||||
system.l2c.overall_hits::cpu.data 482200 # number of overall hits
|
||||
system.l2c.overall_hits::total 1608782 # number of overall hits
|
||||
system.l2c.ReadReq_misses::0 36088 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::1 150 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.dtb.walker 134 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.itb.walker 16 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.inst 17088 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu.data 19000 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 36238 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::0 3252 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu.data 3252 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 3252 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::0 4 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::0 140397 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu.data 140397 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 140397 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::0 176485 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::1 150 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.dtb.walker 134 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.itb.walker 16 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.inst 17088 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu.data 159397 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 176635 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::0 176485 # number of overall misses
|
||||
system.l2c.overall_misses::1 150 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.dtb.walker 134 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.itb.walker 16 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.inst 17088 # number of overall misses
|
||||
system.l2c.overall_misses::cpu.data 159397 # number of overall misses
|
||||
system.l2c.overall_misses::total 176635 # number of overall misses
|
||||
system.l2c.ReadReq_miss_latency 1895542500 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency 1059500 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency 7383005500 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency 9278548000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency 9278548000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::0 1385623 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::1 153427 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7004000 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.itb.walker 843500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.inst 894670500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::cpu.data 993024500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_latency::total 1895542500 # number of ReadReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu.data 1059500 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 1059500 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu.data 7383005500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 7383005500 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.dtb.walker 7004000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.itb.walker 843500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.inst 894670500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu.data 8376030000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 9278548000 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.dtb.walker 7004000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.itb.walker 843500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.inst 894670500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu.data 8376030000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 9278548000 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu.dtb.walker 143829 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.itb.walker 9598 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.inst 990393 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu.data 395230 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1539050 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::0 630148 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 630148 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 630148 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::0 3299 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu.data 3299 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 3299 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::0 21 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu.data 21 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 21 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::0 246367 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu.data 246367 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 246367 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::0 1631990 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::1 153427 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.dtb.walker 143829 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.itb.walker 9598 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.inst 990393 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu.data 641597 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1785417 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::0 1631990 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::1 153427 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.dtb.walker 143829 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.itb.walker 9598 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.inst 990393 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu.data 641597 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1785417 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::0 0.026045 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::1 0.000978 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.027022 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::0 0.985753 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::0 0.190476 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::0 0.569869 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::0 0.108141 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::1 0.000978 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.109119 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::0 0.108141 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::1 0.000978 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.109119 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::0 52525.562514 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::1 12636950 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 12689475.562514 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::0 325.799508 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::0 52586.632905 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::0 52574.145111 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::1 61856986.666667 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 61909560.811778 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::0 52574.145111 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::1 61856986.666667 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 61909560.811778 # average overall miss latency
|
||||
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000932 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.inst 0.017254 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu.data 0.048073 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu.data 0.985753 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.190476 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu.data 0.569869 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000932 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.inst 0.017254 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu.data 0.248438 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000932 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.inst 0.017254 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu.data 0.248438 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52268.656716 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52718.750000 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52356.653792 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::cpu.data 52264.447368 # average ReadReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 325.799508 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52586.632905 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52268.656716 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52718.750000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.inst 52356.653792 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu.data 52548.228637 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52268.656716 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52718.750000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.inst 52356.653792 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu.data 52548.228637 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -127,55 +170,102 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av
|
|||
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks 102643 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits
|
||||
system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits
|
||||
system.l2c.overall_mshr_hits 94 # number of overall MSHR hits
|
||||
system.l2c.ReadReq_mshr_misses 36144 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses 3252 # number of UpgradeReq MSHR misses
|
||||
system.l2c.SCUpgradeReq_mshr_misses 4 # number of SCUpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses 140397 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses 176541 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses 176541 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.l2c.ReadReq_mshr_miss_latency 1450468000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency 131324500 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency 160000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency 5639183500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency 7089651500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency 7089651500 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency 131770082500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency 32364127897 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency 164134210397 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::0 0.026085 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::1 0.235578 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 0.261663 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::0 0.985753 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.190476 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::0 0.569869 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::0 0.108175 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::1 1.150651 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 1.258827 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::0 0.108175 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::1 1.150651 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 1.258827 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency 40130.256751 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency 40382.687577 # average UpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency 40165.982891 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency 40158.668525 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency 40158.668525 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.l2c.writebacks::writebacks 102643 # number of writebacks
|
||||
system.l2c.writebacks::total 102643 # number of writebacks
|
||||
system.l2c.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits
|
||||
system.l2c.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits
|
||||
system.l2c.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
|
||||
system.l2c.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_hits::cpu.data 80 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
|
||||
system.l2c.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_hits::cpu.data 80 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_hits::total 94 # number of overall MSHR hits
|
||||
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 134 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 16 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.inst 17074 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::cpu.data 18920 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_misses::total 36144 # number of ReadReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::cpu.data 3252 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses::total 3252 # number of UpgradeReq MSHR misses
|
||||
system.l2c.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses
|
||||
system.l2c.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::cpu.data 140397 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadExReq_mshr_misses::total 140397 # number of ReadExReq MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.dtb.walker 134 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.itb.walker 16 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.inst 17074 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::cpu.data 159317 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_misses::total 176541 # number of demand (read+write) MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.dtb.walker 134 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.itb.walker 16 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.inst 17074 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu.data 159317 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 176541 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 5376000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 651000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 685402500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu.data 759038500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 1450468000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 131324500 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 131324500 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 160000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::total 160000 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5639183500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 5639183500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 5376000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 651000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.inst 685402500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu.data 6398222000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 7089651500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 5376000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 651000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.inst 685402500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu.data 6398222000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 7089651500 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 4738500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765344000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 131770082500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32364127897 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 32364127897 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.inst 4738500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu.data 164129471897 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 164134210397 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.047871 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985753 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.190476 # mshr miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569869 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::cpu.data 0.248313 # mshr miss rate for demand accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu.data 0.248313 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.053766 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40118.313953 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40382.687577 # average UpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40165.982891 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.053766 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40160.321874 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.053766 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40160.321874 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
|
|
@ -429,9 +519,9 @@ system.cpu.iew.iewDispNonSpecInsts 1227782 # Nu
|
|||
system.cpu.iew.iewIQFullEvents 84296 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 7341 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 32675 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 852505 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 852504 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 256815 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 1109320 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.branchMispredicts 1109319 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 123469909 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 52917262 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 3434775 # Number of squashed instructions skipped in execute
|
||||
|
|
@ -449,7 +539,8 @@ system.cpu.iew.wb_penalized 0 # nu
|
|||
system.cpu.iew.wb_rate 0.209988 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.543006 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 76940267 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedInsts 59599710 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 76940267 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 27835988 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 1499707 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 978113 # The number of times a branch was mispredicted
|
||||
|
|
@ -470,7 +561,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
|
|||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 151014616 # Number of insts commited each cycle
|
||||
system.cpu.commit.count 76940267 # Number of instructions committed
|
||||
system.cpu.commit.committedInsts 59599710 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 76940267 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 27459843 # Number of memory references committed
|
||||
system.cpu.commit.loads 15680763 # Number of loads committed
|
||||
|
|
@ -486,12 +578,13 @@ system.cpu.rob.rob_writes 214319630 # Th
|
|||
system.cpu.timesIdled 1877181 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 260374175 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.quiesceCycles 4591130340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
||||
system.cpu.committedInsts 76789886 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 76789886 # Number of Instructions Simulated
|
||||
system.cpu.cpi 5.416643 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 5.416643 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.184616 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.184616 # IPC: Total IPC of All Threads
|
||||
system.cpu.committedInsts 59449329 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 76789886 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 59449329 # Number of Instructions Simulated
|
||||
system.cpu.cpi 6.996604 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.996604 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.142926 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.142926 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 559798057 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 89741069 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 8257 # number of floating regfile reads
|
||||
|
|
@ -504,51 +597,39 @@ system.cpu.icache.total_refs 13035657 # To
|
|||
system.cpu.icache.sampled_refs 991689 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 13.144904 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 511.615293 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.999249 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::0 13035657 # number of ReadReq hits
|
||||
system.cpu.icache.occ_blocks::cpu.inst 511.615293 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 13035657 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 13035657 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::0 13035657 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 13035657 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 13035657 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::0 13035657 # number of overall hits
|
||||
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 13035657 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 13035657 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::0 1079227 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1079227 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1079227 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::0 1079227 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1079227 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1079227 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::0 1079227 # number of overall misses
|
||||
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1079227 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1079227 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 15906225491 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 15906225491 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 15906225491 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::0 14114884 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15906225491 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15906225491 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15906225491 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15906225491 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15906225491 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15906225491 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 14114884 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 14114884 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::0 14114884 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::cpu.inst 14114884 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 14114884 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::0 14114884 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 14114884 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 14114884 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::0 0.076460 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::0 0.076460 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::0 0.076460 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::0 14738.535536 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::0 14738.535536 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::0 14738.535536 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.076460 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.076460 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.076460 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14738.535536 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14738.535536 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14738.535536 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 2390996 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked
|
||||
|
|
@ -557,35 +638,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7011.718475
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 57255 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 87505 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 87505 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 87505 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 991722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 991722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 991722 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 11850340996 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 11850340996 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 11850340996 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency 6359500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 6359500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070261 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::0 0.070261 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::0 0.070261 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11949.256945 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11949.256945 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11949.256945 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.writebacks::writebacks 57255 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 57255 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87505 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 87505 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 87505 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 87505 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 87505 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 87505 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 991722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 991722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 991722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 991722 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 991722 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11850340996 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 11850340996 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11850340996 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 11850340996 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11850340996 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 11850340996 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6359500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6359500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6359500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::total 6359500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11949.256945 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11949.256945 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11949.256945 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 643728 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use
|
||||
|
|
@ -593,84 +677,69 @@ system.cpu.dcache.total_refs 22270301 # To
|
|||
system.cpu.dcache.sampled_refs 644240 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 34.568330 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 511.991681 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999984 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::0 14416609 # number of ReadReq hits
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.991681 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 14416609 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 14416609 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::0 7264899 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 7264899 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 7264899 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::0 299899 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 299899 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 299899 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::0 285488 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 285488 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 285488 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::0 21681508 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 21681508 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 21681508 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::0 21681508 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::1 0 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 21681508 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 21681508 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::0 722544 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 722544 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 722544 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::0 2966373 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2966373 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2966373 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::0 13502 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13502 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 13502 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::0 21 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 21 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::0 3688917 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3688917 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3688917 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::0 3688917 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3688917 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3688917 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 10864923000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 110367485740 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 219139000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency 467500 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 121232408740 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 121232408740 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::0 15139153 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10864923000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 10864923000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 110367485740 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 110367485740 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 219139000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 219139000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 467500 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::total 467500 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 121232408740 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 121232408740 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 121232408740 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 121232408740 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 15139153 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 15139153 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::0 10231272 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10231272 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10231272 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::0 313401 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 313401 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 313401 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::0 285509 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 285509 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 285509 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::0 25370425 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 25370425 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 25370425 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::0 25370425 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 25370425 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 25370425 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::0 0.047727 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::0 0.289932 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043082 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::0 0.000074 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::0 0.145402 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::0 0.145402 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::0 15037.039959 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::0 37206.206280 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16230.114057 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::0 22261.904762 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::0 32863.956749 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::0 32863.956749 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047727 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289932 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.043082 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000074 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.145402 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.145402 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15037.039959 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37206.206280 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16230.114057 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22261.904762 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32863.956749 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32863.956749 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 16658435 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 7526500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 2975 # number of cycles access was blocked
|
||||
|
|
@ -679,57 +748,63 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 5599.473950
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets 27171.480144 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 572893 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 336628 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 2716799 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 1453 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 3053427 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 3053427 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 385916 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 249574 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 12049 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses 21 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 635490 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 635490 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 5245615500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 8926036935 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161663500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency 398500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 14171652435 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 14171652435 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147159299000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42287348315 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 189446647315 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025491 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024393 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038446 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000074 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::0 0.025048 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::0 0.025048 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13592.635444 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35765.091456 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13417.171550 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 18976.190476 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 22300.354742 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 22300.354742 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 572893 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 572893 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 336628 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 336628 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716799 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2716799 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 3053427 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 3053427 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 3053427 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 3053427 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385916 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 385916 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249574 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 249574 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12049 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12049 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 21 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses::total 21 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 635490 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 635490 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 635490 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 635490 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5245615500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5245615500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8926036935 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8926036935 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 161663500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 161663500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 398500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 398500 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14171652435 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14171652435 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14171652435 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14171652435 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159299000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159299000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42287348315 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42287348315 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189446647315 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 189446647315 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025491 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024393 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.038446 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13592.635444 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35765.091456 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13417.171550 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18976.190476 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 0 # number of replacements
|
||||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
|
|
@ -737,38 +812,6 @@ system.iocache.total_refs 0 # To
|
|||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
||||
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
||||
system.iocache.overall_hits::0 0 # number of overall hits
|
||||
system.iocache.overall_hits::1 0 # number of overall hits
|
||||
system.iocache.overall_hits::total 0 # number of overall hits
|
||||
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::0 0 # number of overall misses
|
||||
system.iocache.overall_misses::1 0 # number of overall misses
|
||||
system.iocache.overall_misses::total 0 # number of overall misses
|
||||
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
|
||||
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
||||
system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
||||
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -777,28 +820,12 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value #
|
|||
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks 0 # number of writebacks
|
||||
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
||||
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency 1307927966543 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency 1307927966543 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
||||
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
||||
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::total 1307927966543 # number of ReadReq MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.overall_mshr_uncacheable_latency::total 1307927966543 # number of overall MSHR uncacheable cycles
|
||||
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 87993 # number of quiesce instructions executed
|
||||
|
|
|
|||
|
|
@ -8,14 +8,14 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxX86System
|
||||
children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
|
||||
children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
|
||||
acpi_description_table_pointer=system.acpi_description_table_pointer
|
||||
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
e820_table=system.e820_table
|
||||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
|
|
@ -50,6 +50,17 @@ oem_id=
|
|||
oem_revision=0
|
||||
oem_table_id=
|
||||
|
||||
[system.apicbridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=11529215046068469760:11529215046068473855
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.membus.port[2]
|
||||
slave=system.iobus.port[1]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
|
|
@ -169,20 +180,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -212,20 +216,13 @@ is_top_level=false
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -507,20 +504,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -559,20 +549,13 @@ is_top_level=false
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -946,17 +929,6 @@ subtractive_decode=true
|
|||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=11529215046068469760:11529215046068473855
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.membus.port[2]
|
||||
slave=system.iobus.port[1]
|
||||
|
||||
[system.iobus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
|
|
@ -966,7 +938,7 @@ header_cycles=1
|
|||
use_default_range=true
|
||||
width=64
|
||||
default=system.pc.pciconfig.pio
|
||||
port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
|
||||
port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
|
|
@ -979,20 +951,13 @@ is_top_level=false
|
|||
latency=50000
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=500000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=1024
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=12
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -1011,20 +976,13 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -1042,7 +1000,7 @@ header_cycles=1
|
|||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
|
|
@ -1303,7 +1261,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
image_file=/dist/m5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1323,7 +1281,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
|
|||
|
|
@ -1,15 +1,12 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 3 2012 12:36:19
|
||||
gem5 started Feb 3 2012 12:37:07
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 15:31:16
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5163317092500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=true
|
||||
time_sync_enable=false
|
||||
time_sync_period=200000000
|
||||
time_sync_spin_threshold=200000
|
||||
|
|
@ -8,7 +9,6 @@ time_sync_spin_threshold=200000
|
|||
[system]
|
||||
type=SparcSystem
|
||||
children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000
|
||||
boot_cpu_frequency=1
|
||||
boot_osflags=a
|
||||
hypervisor_addr=1099243257856
|
||||
hypervisor_bin=/dist/m5/system/binaries/q_new.bin
|
||||
|
|
@ -19,7 +19,7 @@ init_param=0
|
|||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem2 system.nvram system.partition_desc system.rom system.physmem system.hypervisor_desc
|
||||
memories=system.rom system.hypervisor_desc system.physmem2 system.nvram system.physmem system.partition_desc
|
||||
num_work_ids=16
|
||||
nvram=system.nvram
|
||||
nvram_addr=133429198848
|
||||
|
|
@ -83,6 +83,7 @@ simulate_inst_stalls=false
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.membus.port[11]
|
||||
icache_port=system.membus.port[10]
|
||||
|
||||
|
|
@ -106,7 +107,6 @@ children=image
|
|||
image=system.disk0.image
|
||||
pio_addr=134217728000
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
pio=system.iobus.port[15]
|
||||
|
||||
|
|
@ -165,7 +165,6 @@ fake_mem=false
|
|||
pio_addr=0
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -238,7 +237,6 @@ fake_mem=false
|
|||
pio_addr=644245094400
|
||||
pio_latency=2
|
||||
pio_size=4294967296
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -255,7 +253,6 @@ fake_mem=false
|
|||
pio_addr=549755813888
|
||||
pio_latency=2
|
||||
pio_size=4294967296
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -272,7 +269,6 @@ fake_mem=false
|
|||
pio_addr=725849473024
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -289,7 +285,6 @@ fake_mem=false
|
|||
pio_addr=725849473088
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -306,7 +301,6 @@ fake_mem=false
|
|||
pio_addr=725849473152
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -323,7 +317,6 @@ fake_mem=false
|
|||
pio_addr=725849473216
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -340,7 +333,6 @@ fake_mem=false
|
|||
pio_addr=734439407616
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -357,7 +349,6 @@ fake_mem=false
|
|||
pio_addr=734439407680
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -374,7 +365,6 @@ fake_mem=false
|
|||
pio_addr=734439407744
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -391,7 +381,6 @@ fake_mem=false
|
|||
pio_addr=734439407808
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -408,7 +397,6 @@ fake_mem=false
|
|||
pio_addr=648540061696
|
||||
pio_latency=2
|
||||
pio_size=16384
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -425,7 +413,6 @@ fake_mem=false
|
|||
pio_addr=1095216660480
|
||||
pio_latency=2
|
||||
pio_size=268435456
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -447,7 +434,6 @@ port=3456
|
|||
type=DumbTOD
|
||||
pio_addr=1099255906296
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.membus.port[1]
|
||||
|
|
|
|||
|
|
@ -1,14 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:05:05
|
||||
gem5 started Jan 23 2012 06:26:23
|
||||
gem5 compiled Feb 11 2012 13:08:33
|
||||
gem5 started Feb 11 2012 14:02:46
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC_FS/gem5.opt -d build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
|
||||
Global frequency set at 2000000000 ticks per second
|
||||
0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
|
||||
0: system.t1000.htod: Real-time clock set to 1230768000
|
||||
info: No kernel set for full system simulation. Assuming you know what you're doing...
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Ignoring write to SPARC ERROR regsiter
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 1.116889 # Nu
|
|||
sim_ticks 2233777512 # Number of ticks simulated
|
||||
final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 2000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3505728 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 3512989 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 500940 # Number of bytes of host memory used
|
||||
host_seconds 635.86 # Real time elapsed on the host
|
||||
sim_insts 2229160714 # Number of instructions simulated
|
||||
host_inst_rate 4520258 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 4522035 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4531400 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 500812 # Number of bytes of host memory used
|
||||
host_seconds 492.96 # Real time elapsed on the host
|
||||
sim_insts 2228284650 # Number of instructions simulated
|
||||
sim_ops 2229160714 # Number of ops (including micro ops) simulated
|
||||
system.hypervisor_desc.bytes_read 16792 # Number of bytes read from this memory
|
||||
system.hypervisor_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.hypervisor_desc.bytes_written 0 # Number of bytes written to this memory
|
||||
|
|
@ -17,6 +19,15 @@ system.hypervisor_desc.num_writes 0 # Nu
|
|||
system.hypervisor_desc.num_other 0 # Number of other requests responded to by this memory
|
||||
system.hypervisor_desc.bw_read 15035 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total 15035 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bytes_read 1128688 # Number of bytes read from this memory
|
||||
system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.bytes_written 0 # Number of bytes written to this memory
|
||||
system.rom.num_reads 195123 # Number of read requests responded to by this memory
|
||||
system.rom.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.rom.num_other 0 # Number of other requests responded to by this memory
|
||||
system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bytes_read 9813991967 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_inst_read 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem2.bytes_written 897268422 # Number of bytes written to this memory
|
||||
|
|
@ -36,23 +47,6 @@ system.nvram.num_other 0 # Nu
|
|||
system.nvram.bw_read 254 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write 82 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_total 337 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bytes_read 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.partition_desc.bytes_written 0 # Number of bytes written to this memory
|
||||
system.partition_desc.num_reads 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.partition_desc.num_other 0 # Number of other requests responded to by this memory
|
||||
system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bytes_read 1128688 # Number of bytes read from this memory
|
||||
system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.bytes_written 0 # Number of bytes written to this memory
|
||||
system.rom.num_reads 195123 # Number of read requests responded to by this memory
|
||||
system.rom.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.rom.num_other 0 # Number of other requests responded to by this memory
|
||||
system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read 709825348 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 612291324 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 15400223 # Number of bytes written to this memory
|
||||
|
|
@ -63,10 +57,19 @@ system.physmem.bw_read 635538091 # To
|
|||
system.physmem.bw_inst_read 548211557 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 13788502 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 649326593 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bytes_read 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.partition_desc.bytes_written 0 # Number of bytes written to this memory
|
||||
system.partition_desc.num_reads 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.partition_desc.num_other 0 # Number of other requests responded to by this memory
|
||||
system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 2229160714 # Number of instructions executed
|
||||
system.cpu.committedInsts 2228284650 # Number of instructions committed
|
||||
system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 44037246 # number of times a function call or return occured
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
|
|
@ -45,6 +52,7 @@ div32RepeatRate=1
|
|||
div8Latency=1
|
||||
div8RepeatRate=1
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchBuffSize=4
|
||||
|
|
@ -57,6 +65,7 @@ globalCtrBits=2
|
|||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
|
|
@ -72,6 +81,7 @@ multRepeatRate=1
|
|||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
stageTracing=false
|
||||
stageWidth=4
|
||||
|
|
@ -93,20 +103,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -129,20 +132,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -150,6 +146,9 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -165,20 +164,13 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -202,7 +194,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
|
||||
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:48:33
|
||||
gem5 started Jan 23 2012 05:24:12
|
||||
gem5 compiled Feb 11 2012 13:05:17
|
||||
gem5 started Feb 11 2012 13:10:21
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.274500 # Nu
|
|||
sim_ticks 274500333500 # Number of ticks simulated
|
||||
final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 113367 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 51705325 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 207980 # Number of bytes of host memory used
|
||||
host_seconds 5308.94 # Real time elapsed on the host
|
||||
host_inst_rate 160535 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 160535 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 73218214 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 209892 # Number of bytes of host memory used
|
||||
host_seconds 3749.07 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5894016 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3798080 # Number of bytes written to this memory
|
||||
|
|
@ -69,9 +71,10 @@ system.cpu.comNops 36304520 # Nu
|
|||
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
|
||||
system.cpu.comInts 349039879 # Number of Integer instructions committed
|
||||
system.cpu.comFloats 24 # Number of Floating Point instructions committed
|
||||
system.cpu.committedInsts 601856964 # Number of Instructions Simulated (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
|
||||
system.cpu.committedInsts_total 601856964 # Number of Instructions Simulated (Total)
|
||||
system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread)
|
||||
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads
|
||||
|
|
@ -125,26 +128,39 @@ system.cpu.icache.total_refs 27985205 # To
|
|||
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 728.259897 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.355596 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 27985205 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 27985205 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 27985205 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 1019 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 56646500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 56646500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 56646500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 27986224 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 27986224 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 27986224 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000036 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000036 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55590.284593 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 55590.284593 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 55590.284593 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 728.259897 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.355596 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.355596 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 27985205 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 27985205 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 27985205 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 27985205 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 27985205 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 27985205 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1019 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1019 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1019 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1019 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 56646500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 56646500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 56646500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 56646500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 56646500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 56646500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 27986224 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 27986224 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 27986224 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 27986224 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 27986224 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 27986224 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55590.284593 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -153,27 +169,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 164 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 164 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 164 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 855 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 45774000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 45774000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 45774000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000031 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53536.842105 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 164 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45774000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 45774000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45774000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 45774000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45774000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 45774000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.842105 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use
|
||||
|
|
@ -181,32 +200,49 @@ system.cpu.dcache.total_refs 152394244 # To
|
|||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4094.126386 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999543 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 114120509 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 38273735 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 152394244 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 152394244 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 393533 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 1177586 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 1571119 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 1571119 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 8150453500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 25245531000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 33395984500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 33395984500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.003437 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.029849 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.010204 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.010204 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20710.978495 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 21438.375626 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 21256.177603 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 21256.177603 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.126386 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 38273735 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 38273735 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 152394244 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 152394244 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 152394244 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 152394244 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393533 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1177586 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1177586 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1571119 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1571119 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1571119 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1571119 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150453500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8150453500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25245531000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 25245531000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 33395984500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 33395984500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 33395984500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 33395984500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029849 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.010204 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.010204 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20710.978495 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21438.375626 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 12016500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 3424460500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 2770 # number of cycles access was blocked
|
||||
|
|
@ -215,32 +251,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4338.086643
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 408188 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 192301 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 923423 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 1115724 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 1115724 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3562138000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5466740000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 9028878000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 9028878000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.647849 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21508.795537 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 408188 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 408188 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923423 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 923423 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1115724 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1115724 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1115724 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1115724 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562138000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562138000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466740000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466740000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028878000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9028878000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028878000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9028878000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.647849 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21508.795537 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 73797 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17695.095192 # Cycle average of tags in use
|
||||
|
|
@ -248,36 +292,72 @@ system.cpu.l2cache.total_refs 445688 # To
|
|||
system.cpu.l2cache.sampled_refs 89683 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.969593 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 1638.137841 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 16056.957351 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.049992 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.490019 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 170051 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 408188 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 194105 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 364156 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 364156 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 32019 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 60075 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 92094 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 92094 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1674917000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3134446000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 4809363000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 4809363000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 202070 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 408188 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 254180 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 456250 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 456250 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.158455 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.236348 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.201850 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.201850 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52310.097130 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.547233 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52222.327187 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52222.327187 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16056.957351 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 28.224139 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1609.913702 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.490019 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000861 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.049131 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.540011 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 170051 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 170051 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 408188 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 408188 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 194105 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 194105 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 364156 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 364156 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 364156 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 364156 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 31164 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 32019 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 60075 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 60075 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 855 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 91239 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 92094 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 855 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 91239 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 92094 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44769000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1630148000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1674917000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3134446000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3134446000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 44769000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4764594000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4809363000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 44769000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4764594000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4809363000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 201215 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 202070 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 408188 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 408188 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254180 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 254180 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154879 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236348 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200351 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200351 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.403509 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52308.689514 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52175.547233 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked
|
||||
|
|
@ -286,30 +366,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 59345 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32019 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 60075 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 92094 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 92094 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1281026000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406899500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3687925500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3687925500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158455 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236348 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.201850 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.201850 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.307567 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.910529 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 59345 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59345 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31164 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 32019 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60075 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 60075 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 91239 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 92094 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 91239 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 92094 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34345000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246681000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281026000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406899500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406899500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34345000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653580500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3687925500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34345000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653580500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3687925500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154879 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236348 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.882685 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.910529 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -52,6 +59,7 @@ decodeWidth=8
|
|||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchToDecodeDelay=1
|
||||
|
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
|||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -80,6 +89,7 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
|
|
@ -88,6 +98,7 @@ numRobs=1
|
|||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
|
|
@ -125,20 +136,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -424,20 +428,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -445,6 +442,9 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -460,20 +460,13 @@ is_top_level=false
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -497,7 +490,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:48:33
|
||||
gem5 started Jan 23 2012 05:24:12
|
||||
gem5 compiled Feb 11 2012 13:05:17
|
||||
gem5 started Feb 11 2012 13:10:26
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.144450 # Nu
|
|||
sim_ticks 144450185500 # Number of ticks simulated
|
||||
final_tick 144450185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 205040 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 52370107 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 208620 # Number of bytes of host memory used
|
||||
host_seconds 2758.26 # Real time elapsed on the host
|
||||
host_inst_rate 270959 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 270959 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 69206896 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 211048 # Number of bytes of host memory used
|
||||
host_seconds 2087.22 # Real time elapsed on the host
|
||||
sim_insts 565552443 # Number of instructions simulated
|
||||
sim_ops 565552443 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5936768 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 60416 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3797120 # Number of bytes written to this memory
|
||||
|
|
@ -272,6 +274,7 @@ system.cpu.iew.wb_rate 2.107953 # in
|
|||
system.cpu.iew.wb_fanout 0.790402 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 84796787 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 4132184 # The number of times a branch was mispredicted
|
||||
|
|
@ -292,7 +295,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
|
|||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 276422432 # Number of insts commited each cycle
|
||||
system.cpu.commit.count 601856963 # Number of instructions committed
|
||||
system.cpu.commit.committedInsts 601856963 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 153965363 # Number of memory references committed
|
||||
system.cpu.commit.loads 114514042 # Number of loads committed
|
||||
|
|
@ -308,6 +312,7 @@ system.cpu.rob.rob_writes 1385724156 # Th
|
|||
system.cpu.timesIdled 2221 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 68890 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.510829 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.510829 # CPI: Total CPI of All Threads
|
||||
|
|
@ -325,26 +330,39 @@ system.cpu.icache.total_refs 70951127 # To
|
|||
system.cpu.icache.sampled_refs 944 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 75160.092161 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 801.236568 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.391229 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 70951127 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 70951127 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 70951127 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 1272 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 1272 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 1272 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 45919500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 45919500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 45919500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 70952399 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 70952399 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 70952399 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36100.235849 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 36100.235849 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 36100.235849 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 801.236568 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.391229 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.391229 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 70951127 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 70951127 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 70951127 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 70951127 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 70951127 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 70951127 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1272 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1272 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1272 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1272 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1272 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1272 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 45919500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 45919500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 45919500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 45919500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 45919500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 45919500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 70952399 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 70952399 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 70952399 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 70952399 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 70952399 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 70952399 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000018 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000018 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000018 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36100.235849 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36100.235849 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36100.235849 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -353,27 +371,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 328 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 328 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 328 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 944 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 944 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 944 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 33676000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 33676000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 33676000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35673.728814 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35673.728814 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35673.728814 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 944 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 944 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 944 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 944 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 944 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 944 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33676000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 33676000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33676000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 33676000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33676000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 33676000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35673.728814 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35673.728814 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35673.728814 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 470690 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4093.940031 # Cycle average of tags in use
|
||||
|
|
@ -381,34 +402,53 @@ system.cpu.dcache.total_refs 151212527 # To
|
|||
system.cpu.dcache.sampled_refs 474786 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 318.485648 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126051000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4093.940031 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999497 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 113064898 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 38147626 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.demand_hits 151212524 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 151212524 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 732041 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 1303695 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 2035736 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 2035736 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 11783533000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 19632740219 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 31416273219 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 31416273219 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 113796939 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 153248260 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 153248260 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.006433 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.033046 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.013284 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.013284 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16096.821080 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 15059.304683 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 15432.390653 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 15432.390653 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.940031 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999497 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999497 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 113064898 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 113064898 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 38147626 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 38147626 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 151212524 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 151212524 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 151212524 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 151212524 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 732041 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 732041 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1303695 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1303695 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2035736 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2035736 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2035736 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2035736 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11783533000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11783533000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19632740219 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19632740219 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31416273219 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31416273219 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31416273219 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31416273219 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 113796939 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 113796939 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 153248260 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 153248260 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 153248260 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 153248260 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006433 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.033046 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.013284 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.013284 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16096.821080 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15059.304683 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15432.390653 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15432.390653 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 804496 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 116 # number of cycles access was blocked
|
||||
|
|
@ -417,32 +457,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 6935.310345
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 423044 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 513277 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1047673 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 1560950 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 1560950 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 218764 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 256022 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 474786 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 474786 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1640072500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3027658494 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4667730994 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4667730994 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001922 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.003098 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.003098 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7496.994478 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.774715 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 9831.231321 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 9831.231321 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 423044 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 423044 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 513277 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 513277 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1047673 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1047673 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1560950 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1560950 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1560950 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1560950 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 218764 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 218764 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 256022 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 256022 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 474786 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 474786 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 474786 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 474786 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1640072500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1640072500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3027658494 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3027658494 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4667730994 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 4667730994 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4667730994 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 4667730994 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001922 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003098 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003098 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7496.994478 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11825.774715 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9831.231321 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9831.231321 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 74463 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17661.712037 # Cycle average of tags in use
|
||||
|
|
@ -450,36 +498,72 @@ system.cpu.l2cache.total_refs 478021 # To
|
|||
system.cpu.l2cache.sampled_refs 90363 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.290008 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 1743.919943 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15917.792095 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.053220 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.485772 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 186750 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 423044 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 196218 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 382968 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 382968 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 32958 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 92762 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 92762 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1133680000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2065878500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 3199558500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 3199558500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 219708 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 423044 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 256022 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 475730 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 475730 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.150008 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.233589 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.194989 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.194989 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34397.718308 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34544.152565 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34492.125008 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34492.125008 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15917.792095 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 36.116254 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1707.803688 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.485772 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001102 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.538993 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 186750 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 186750 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 423044 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 423044 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 196218 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 196218 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 382968 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 382968 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 382968 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 382968 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 944 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 32014 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 32958 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 59804 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 59804 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 944 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 91818 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 92762 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 944 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 91818 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 92762 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32444500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1101235500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1133680000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2065878500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2065878500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 32444500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 3167114000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 3199558500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 32444500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 3167114000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 3199558500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 944 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 218764 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 219708 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 423044 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 423044 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 256022 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 256022 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 944 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 474786 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 475730 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 944 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 474786 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 475730 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.146340 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.233589 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.193388 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.193388 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34369.173729 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.560005 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34544.152565 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34369.173729 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34493.389096 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34369.173729 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34493.389096 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked
|
||||
|
|
@ -488,30 +572,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 59330 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32958 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 92762 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 92762 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1022345000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877543500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2899888500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2899888500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150008 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233589 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.194989 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.194989 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.631046 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31394.948498 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 59330 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59330 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 944 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32014 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 32958 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 59804 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 59804 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 944 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 91818 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 92762 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 944 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 91818 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 92762 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29409000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 992936000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1022345000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1877543500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1877543500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29409000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2870479500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 2899888500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29409000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2870479500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 2899888500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.146340 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.233589 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31153.601695 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.680640 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31394.948498 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
|
|||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -64,7 +77,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
|
||||
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:48:33
|
||||
gem5 started Jan 23 2012 05:24:12
|
||||
gem5 compiled Feb 11 2012 13:05:17
|
||||
gem5 started Feb 11 2012 13:10:30
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.300931 # Nu
|
|||
sim_ticks 300930958000 # Number of ticks simulated
|
||||
final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 4527143 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2263589972 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 198960 # Number of bytes of host memory used
|
||||
host_seconds 132.94 # Real time elapsed on the host
|
||||
host_inst_rate 5630967 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 5630966 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2815505896 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 200704 # Number of bytes of host memory used
|
||||
host_seconds 106.88 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 2782990928 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 152669504 # Number of bytes written to this memory
|
||||
|
|
@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu
|
|||
system.cpu.numCycles 601861917 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 601856964 # Number of instructions executed
|
||||
system.cpu.committedInsts 601856964 # Number of instructions committed
|
||||
system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -58,20 +68,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -94,20 +97,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -115,6 +111,9 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -130,20 +129,13 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -167,7 +159,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
|
||||
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:48:33
|
||||
gem5 started Jan 23 2012 05:24:12
|
||||
gem5 compiled Feb 11 2012 13:05:17
|
||||
gem5 started Feb 11 2012 13:10:31
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.765623 # Nu
|
|||
sim_ticks 765623032000 # Number of ticks simulated
|
||||
final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2199350 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2797795440 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 207676 # Number of bytes of host memory used
|
||||
host_seconds 273.65 # Real time elapsed on the host
|
||||
host_inst_rate 2698243 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2698243 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3432438217 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 209572 # Number of bytes of host memory used
|
||||
host_seconds 223.06 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5889984 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3797824 # Number of bytes written to this memory
|
||||
|
|
@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu
|
|||
system.cpu.numCycles 1531246064 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 601856964 # Number of instructions executed
|
||||
system.cpu.committedInsts 601856964 # Number of instructions committed
|
||||
system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
|
||||
|
|
@ -79,26 +82,39 @@ system.cpu.icache.total_refs 601861103 # To
|
|||
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 673.337154 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.328778 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 601861103 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 795 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 673.337154 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.328778 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.328778 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 601861103 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 601861103 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 601861103 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 795 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 795 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 795 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44520000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44520000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44520000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44520000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 601861898 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 601861898 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 795 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42135000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 42135000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42135000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 42135000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use
|
||||
|
|
@ -134,32 +148,49 @@ system.cpu.dcache.total_refs 153509968 # To
|
|||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4094.170317 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999553 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 153509968 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 455395 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 4126262000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 6081180000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 10207442000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 10207442000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20504.999205 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23926.299265 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 22414.479737 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 22414.479737 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.170317 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999553 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 153509968 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 455395 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4126262000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4126262000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6081180000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 6081180000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10207442000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10207442000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10207442000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10207442000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 408190 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3522566000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5318691000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 8841257000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 8841257000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17504.999205 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20926.299265 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 408190 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3522566000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3522566000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5318691000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5318691000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8841257000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 73734 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use
|
||||
|
|
@ -199,36 +232,72 @@ system.cpu.l2cache.total_refs 445709 # To
|
|||
system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 1722.436058 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 16101.078831 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.052565 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.491366 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 170065 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 408190 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 194094 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 364159 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 364159 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 31962 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 60069 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 92031 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 92031 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1662024000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3123588000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 4785612000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 4785612000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 408190 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.158207 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.236340 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.201738 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.201738 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16101.078831 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 29.487971 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1692.948088 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.491366 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000900 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.051665 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.543931 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 170065 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 170065 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 194094 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 194094 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 364159 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 364159 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 364159 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 364159 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 31167 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 31962 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 60069 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 60069 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 795 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 91236 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 92031 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 795 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 91236 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 92031 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41340000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1620684000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1662024000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123588000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3123588000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 41340000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4744272000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4785612000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 41340000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4744272000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4785612000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 456190 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 795 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -237,30 +306,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 59341 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 31962 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 60069 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 92031 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 92031 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1278480000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2402760000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3681240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3681240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158207 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.201738 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.201738 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59341 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31167 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 31962 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60069 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 60069 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 91236 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 92031 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 91236 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 92031 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1278480000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2402760000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2402760000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649440000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3681240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -136,20 +136,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -444,20 +437,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -492,20 +478,13 @@ is_top_level=false
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -529,12 +508,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
|
||||
cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 10 2012 00:18:03
|
||||
gem5 started Feb 10 2012 00:18:23
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
|
||||
gem5 compiled Feb 11 2012 13:10:40
|
||||
gem5 started Feb 11 2012 15:39:44
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.177117 # Nu
|
|||
sim_ticks 177116942500 # Number of ticks simulated
|
||||
final_tick 177116942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 89657 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 26362655 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 256136 # Number of bytes of host memory used
|
||||
host_seconds 6718.48 # Real time elapsed on the host
|
||||
sim_insts 602359810 # Number of instructions simulated
|
||||
host_inst_rate 193712 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 204690 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 60186856 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223404 # Number of bytes of host memory used
|
||||
host_seconds 2942.78 # Real time elapsed on the host
|
||||
sim_insts 570051603 # Number of instructions simulated
|
||||
sim_ops 602359810 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5833792 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3720320 # Number of bytes written to this memory
|
||||
|
|
@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu
|
|||
system.cpu.iew.wb_rate 1.835552 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.643966 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 602359861 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedInsts 570051654 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 602359861 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 100193357 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 6347 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 4062580 # The number of times a branch was mispredicted
|
||||
|
|
@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
|
|||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 339017045 # Number of insts commited each cycle
|
||||
system.cpu.commit.count 602359861 # Number of instructions committed
|
||||
system.cpu.commit.committedInsts 570051654 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 602359861 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 219173611 # Number of memory references committed
|
||||
system.cpu.commit.loads 148952596 # Number of loads committed
|
||||
|
|
@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 1023326216 # Th
|
|||
system.cpu.rob.rob_writes 1419524916 # The number of ROB writes
|
||||
system.cpu.timesIdled 37353 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 840358 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 602359810 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 602359810 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.588077 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.588077 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.700458 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.700458 # IPC: Total IPC of All Threads
|
||||
system.cpu.committedInsts 570051603 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 602359810 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 570051603 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.621407 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.621407 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.609252 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.609252 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 3275977261 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 676006750 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
|
|
@ -335,26 +340,39 @@ system.cpu.icache.total_refs 74421550 # To
|
|||
system.cpu.icache.sampled_refs 765 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 97283.071895 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 657.275674 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.320935 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 74421550 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 74421550 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 74421550 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 996 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 996 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 996 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 34937500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 34937500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 34937500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 74422546 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 74422546 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 74422546 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35077.811245 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 35077.811245 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 35077.811245 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 657.275674 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.320935 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.320935 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 74421550 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 74421550 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 74421550 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 74421550 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 74421550 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 74421550 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 996 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 996 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 996 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 996 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 996 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 996 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34937500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34937500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34937500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34937500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34937500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34937500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 74422546 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 74422546 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 74422546 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 74422546 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 74422546 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 74422546 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000013 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000013 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000013 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35077.811245 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35077.811245 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35077.811245 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -363,27 +381,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 231 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 231 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 231 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 765 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 765 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 765 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 26235000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 26235000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 26235000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34294.117647 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34294.117647 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34294.117647 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 231 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 231 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 231 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 231 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 231 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 231 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 765 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 765 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 765 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 765 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 765 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 765 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26235000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 26235000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26235000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 26235000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26235000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 26235000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34294.117647 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34294.117647 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34294.117647 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 441200 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.750887 # Cycle average of tags in use
|
||||
|
|
@ -391,40 +412,63 @@ system.cpu.dcache.total_refs 205785268 # To
|
|||
system.cpu.dcache.sampled_refs 445296 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 462.131409 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 87972000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4094.750887 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999695 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 137930344 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 67852261 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 1334 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits 1329 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits 205782605 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 205782605 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 248964 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 1565270 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses 1814234 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 1814234 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 3282822000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 27026336525 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 201000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 30309158525 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 30309158525 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 138179308 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses 1343 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses 1329 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 207596839 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 207596839 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001802 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.022549 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.006701 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.008739 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.008739 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 13185.930496 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 17266.245775 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 22333.333333 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 16706.311603 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 16706.311603 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.750887 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999695 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 137930344 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 137930344 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 67852261 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 67852261 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1334 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 1334 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 1329 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 1329 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 205782605 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 205782605 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 205782605 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 205782605 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 248964 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 248964 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1565270 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1565270 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 9 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 9 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1814234 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1814234 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1814234 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1814234 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3282822000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3282822000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 27026336525 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 27026336525 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 201000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 201000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 30309158525 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 30309158525 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 30309158525 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 30309158525 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 138179308 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 138179308 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1343 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 1343 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1329 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 1329 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 207596839 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 207596839 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 207596839 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 207596839 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001802 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022549 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.006701 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.008739 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.008739 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13185.930496 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17266.245775 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22333.333333 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16706.311603 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16706.311603 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked
|
||||
|
|
@ -433,33 +477,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 395250 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 51046 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1317892 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 1368938 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 1368938 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 197918 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 247378 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 445296 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 445296 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1625205500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2544318027 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4169523527 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4169523527 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001432 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002145 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002145 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8211.509312 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10285.142684 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 9363.487494 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 9363.487494 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 395250 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 395250 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51046 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 51046 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1317892 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1317892 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 9 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 9 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1368938 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1368938 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1368938 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1368938 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197918 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 197918 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247378 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 247378 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 445296 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 445296 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 445296 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 445296 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1625205500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1625205500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2544318027 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2544318027 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4169523527 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 4169523527 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4169523527 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 4169523527 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001432 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003564 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002145 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002145 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8211.509312 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10285.142684 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9363.487494 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9363.487494 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 72965 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17807.300199 # Cycle average of tags in use
|
||||
|
|
@ -467,36 +520,75 @@ system.cpu.l2cache.total_refs 421253 # To
|
|||
system.cpu.l2cache.sampled_refs 88492 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.760351 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 1881.136315 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15926.163884 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.057408 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.486028 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 165871 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 395250 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 189027 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 354898 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 354898 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 32808 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 58355 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 91163 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 91163 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1126263500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2003081500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 3129345000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 3129345000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 198679 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 395250 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 247382 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 446061 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 446061 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.165131 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.235890 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.204373 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.204373 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34328.928920 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34325.790421 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34326.919913 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34326.919913 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15926.163884 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 35.771827 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1845.364487 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.486028 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001092 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.056316 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.543436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 165841 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 165871 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 395250 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 395250 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 189027 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 189027 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 354868 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 354898 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 354868 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 354898 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 735 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 32073 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 32808 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 58355 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 58355 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 735 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 90428 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 91163 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 735 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 90428 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 91163 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25238000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1101025500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1126263500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2003081500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2003081500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 25238000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 3104107000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 3129345000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 25238000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 3104107000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 3129345000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 765 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 197914 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 198679 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 395250 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 395250 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247382 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 247382 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 765 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 445296 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 446061 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 765 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 445296 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 446061 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960784 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162055 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235890 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960784 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.203074 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960784 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.203074 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34337.414966 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.734450 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34325.790421 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34337.414966 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34326.834609 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34337.414966 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34326.834609 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked
|
||||
|
|
@ -505,31 +597,53 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 58130 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32798 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 58355 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 91153 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 91153 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1019340000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822214500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2841554500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2841554500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235890 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.204351 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.204351 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.334106 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31226.364493 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.461104 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.461104 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 58130 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 58130 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32064 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 32798 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58355 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 58355 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 90419 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 91153 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 90419 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 91153 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22853000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 996487000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1019340000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1822214500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1822214500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22853000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2818701500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 2841554500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22853000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2818701500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 2841554500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235890 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31134.877384 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31078.062625 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31226.364493 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.membus.port[5]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.membus.port[4]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -64,7 +95,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
|
||||
cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -88,7 +119,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:36:54
|
||||
gem5 compiled Feb 11 2012 13:10:40
|
||||
gem5 started Feb 11 2012 15:43:07
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.301191 # Nu
|
|||
sim_ticks 301191370000 # Number of ticks simulated
|
||||
final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2998309 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1499211130 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 210136 # Number of bytes of host memory used
|
||||
host_seconds 200.90 # Real time elapsed on the host
|
||||
sim_insts 602359851 # Number of instructions simulated
|
||||
host_inst_rate 3224710 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3407474 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1703801368 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 212692 # Number of bytes of host memory used
|
||||
host_seconds 176.78 # Real time elapsed on the host
|
||||
sim_insts 570051644 # Number of instructions simulated
|
||||
sim_ops 602359851 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 2680160157 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 2280298136 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 236359611 # Number of bytes written to this memory
|
||||
|
|
@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 48 # Nu
|
|||
system.cpu.numCycles 602382741 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 602359851 # Number of instructions executed
|
||||
system.cpu.committedInsts 570051644 # Number of instructions committed
|
||||
system.cpu.committedOps 602359851 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -58,20 +68,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.port[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -94,20 +106,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -115,9 +120,21 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.port[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
|
|
@ -130,25 +147,18 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.port[4]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
|
@ -159,7 +169,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -167,7 +177,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
|
||||
cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:40:26
|
||||
gem5 compiled Feb 11 2012 13:10:40
|
||||
gem5 started Feb 11 2012 15:45:54
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.796763 # Nu
|
|||
sim_ticks 796762926000 # Number of ticks simulated
|
||||
final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1450316 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1924652930 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 219100 # Number of bytes of host memory used
|
||||
host_seconds 413.98 # Real time elapsed on the host
|
||||
sim_insts 600398281 # Number of instructions simulated
|
||||
host_inst_rate 1806630 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1907867 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2531848956 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 221588 # Number of bytes of host memory used
|
||||
host_seconds 314.70 # Real time elapsed on the host
|
||||
sim_insts 568539343 # Number of instructions simulated
|
||||
sim_ops 600398281 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5759488 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3704704 # Number of bytes written to this memory
|
||||
|
|
@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 48 # Nu
|
|||
system.cpu.numCycles 1593525852 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 600398281 # Number of instructions executed
|
||||
system.cpu.committedInsts 568539343 # Number of instructions committed
|
||||
system.cpu.committedOps 600398281 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
|
||||
|
|
@ -89,26 +92,39 @@ system.cpu.icache.total_refs 570073892 # To
|
|||
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.282094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 570073892 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 570073892 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 570073892 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 643 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 643 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 570074535 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 570074535 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 577.728532 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.282094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.282094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 570073892 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 570073892 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 570073892 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 570073892 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 570073892 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 570073892 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 643 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34874000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34874000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34874000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34874000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34874000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34874000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 570074535 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 570074535 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 570074535 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 570074535 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 570074535 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 570074535 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 32945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 643 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32945000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 32945000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 32945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32945000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 32945000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 433468 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
|
||||
|
|
@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 216774473 # To
|
|||
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 147602036 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 69169783 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 1327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits 1327 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits 216771819 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 216771819 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 189816 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 437564 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 437564 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 3956274000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 9879688000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 9879688000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 147791852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses 1327 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses 1327 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 217209383 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001284 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.002014 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.002014 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.222434 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 147602036 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 147602036 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 216771819 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 216771819 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 216771819 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 216771819 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 437564 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3956274000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3956274000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5923414000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5923414000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9879688000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9879688000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9879688000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9879688000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 147791852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 147791852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 217209383 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 217209383 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 217209383 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 217209383 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 392392 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 189816 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 437564 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 437564 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3386826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 8566996000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 8566996000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002014 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002014 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 392392 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 392392 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5180170000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5180170000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8566996000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8566996000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 71804 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
|
||||
|
|
@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 411836 # To
|
|||
system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.053777 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.492610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 348215 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 89992 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1640132000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 392392 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16141.835335 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 24.672100 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1737.507245 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.492610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000753 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.053025 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.546387 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 158891 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 158918 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 392392 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 392392 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 189297 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 189297 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 348188 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 348215 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 348188 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 348215 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 30925 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 31541 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 58451 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 58451 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 89376 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 89992 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 89376 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 89992 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1608100000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1640132000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3039452000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3039452000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4647552000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4679584000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4647552000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4679584000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 392392 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 392392 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 437564 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 438207 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 57886 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3599680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.205364 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 57886 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 57886 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30925 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 31541 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58451 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 58451 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 89376 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 89992 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 89376 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 89992 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1237000000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1261640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2338040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2338040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3575040000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3599680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
|
|
@ -52,6 +59,7 @@ decodeWidth=8
|
|||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchToDecodeDelay=1
|
||||
|
|
@ -69,6 +77,7 @@ iewToDecodeDelay=1
|
|||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
|
|
@ -80,6 +89,7 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
|
|
@ -88,6 +98,7 @@ numRobs=1
|
|||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
|
|
@ -125,20 +136,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -424,20 +428,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -445,6 +442,9 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
|
@ -460,20 +460,13 @@ is_top_level=false
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -497,7 +490,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
|
||||
cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:02:00
|
||||
gem5 started Jan 23 2012 06:17:40
|
||||
gem5 compiled Feb 11 2012 13:08:33
|
||||
gem5 started Feb 11 2012 13:56:12
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.408816 # Nu
|
|||
sim_ticks 408816360000 # Number of ticks simulated
|
||||
final_tick 408816360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 175830 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 51139829 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 215728 # Number of bytes of host memory used
|
||||
host_seconds 7994.10 # Real time elapsed on the host
|
||||
sim_insts 1405604152 # Number of instructions simulated
|
||||
host_inst_rate 218783 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 219472 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 63832966 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214000 # Number of bytes of host memory used
|
||||
host_seconds 6404.47 # Real time elapsed on the host
|
||||
sim_insts 1401188958 # Number of instructions simulated
|
||||
sim_ops 1405604152 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 6021376 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 81792 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3792448 # Number of bytes written to this memory
|
||||
|
|
@ -237,7 +239,8 @@ system.cpu.iew.wb_penalized 0 # nu
|
|||
system.cpu.iew.wb_rate 1.812578 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.959383 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 179255835 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 5438120 # The number of times a branch was mispredicted
|
||||
|
|
@ -258,7 +261,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
|
|||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 791834306 # Number of insts commited each cycle
|
||||
system.cpu.commit.count 1489523295 # Number of instructions committed
|
||||
system.cpu.commit.committedInsts 1485108101 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 569360986 # Number of memory references committed
|
||||
system.cpu.commit.loads 402512844 # Number of loads committed
|
||||
|
|
@ -273,12 +277,13 @@ system.cpu.rob.rob_reads 2392297077 # Th
|
|||
system.cpu.rob.rob_writes 3363039880 # The number of ROB writes
|
||||
system.cpu.timesIdled 11286 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 357787 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.581695 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.581695 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.719114 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.719114 # IPC: Total IPC of All Threads
|
||||
system.cpu.committedInsts 1401188958 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.583528 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.583528 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.713714 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.713714 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 2016058791 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1303867666 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16986540 # number of floating regfile reads
|
||||
|
|
@ -291,26 +296,39 @@ system.cpu.icache.total_refs 170772098 # To
|
|||
system.cpu.icache.sampled_refs 1298 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 131565.560863 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 1031.400456 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.503614 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 170772098 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 170772098 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 170772098 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 1798 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 1798 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 1798 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 62741500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 62741500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 62741500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 170773896 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 170773896 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 170773896 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000011 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000011 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000011 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 34895.161290 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 34895.161290 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 34895.161290 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1031.400456 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.503614 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.503614 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 170772098 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 170772098 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 170772098 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 170772098 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 170772098 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 170772098 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1798 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1798 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1798 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1798 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1798 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1798 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 62741500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 62741500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 62741500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 62741500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 62741500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 62741500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 170773896 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 170773896 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 170773896 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 170773896 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 170773896 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 170773896 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000011 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000011 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000011 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34895.161290 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34895.161290 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34895.161290 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -319,27 +337,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 499 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 499 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 499 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 1299 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 1299 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 1299 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 45206000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 45206000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 45206000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34800.615858 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34800.615858 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34800.615858 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 499 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 499 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 499 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 499 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 499 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 499 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1299 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 1299 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 1299 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 1299 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1299 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1299 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45206000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 45206000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45206000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 45206000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45206000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 45206000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34800.615858 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34800.615858 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34800.615858 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 475353 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4095.165283 # Cycle average of tags in use
|
||||
|
|
@ -347,38 +368,59 @@ system.cpu.dcache.total_refs 385593109 # To
|
|||
system.cpu.dcache.sampled_refs 479449 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 804.242180 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 131001000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4095.165283 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999796 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 220654856 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 164936934 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits 385591790 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 385591790 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 815916 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 1909882 # number of WriteReq misses
|
||||
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
|
||||
system.cpu.dcache.demand_misses 2725798 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 2725798 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 11966603000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 29861651909 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 268000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 41828254909 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 41828254909 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 221470772 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 388317588 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 388317588 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.003684 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.011447 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.007020 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.007020 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14666.464440 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 15635.338680 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 38285.714286 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 15345.324528 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 15345.324528 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4095.165283 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999796 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999796 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 220654856 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 220654856 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 164936934 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 164936934 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 385591790 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 385591790 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 385591790 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 385591790 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 815916 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 815916 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1909882 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1909882 # number of WriteReq misses
|
||||
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2725798 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2725798 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2725798 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2725798 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11966603000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11966603000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 29861651909 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 29861651909 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 268000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 268000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 41828254909 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 41828254909 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 41828254909 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 41828254909 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 221470772 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 221470772 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 388317588 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 388317588 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 388317588 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 388317588 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003684 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011447 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.007020 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.007020 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14666.464440 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15635.338680 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38285.714286 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15345.324528 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15345.324528 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 28000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked
|
||||
|
|
@ -387,36 +429,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2153.846154
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 426654 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 603731 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1642625 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 2246356 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 2246356 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 212185 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 267257 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 479442 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 479442 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1589383500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3625603341 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 247000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5214986841 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5214986841 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000958 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001602 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.001235 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.001235 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7490.555412 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13565.980839 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35285.714286 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 10877.200665 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 10877.200665 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 426654 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 426654 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603731 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 603731 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642625 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1642625 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2246356 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2246356 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2246356 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2246356 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 212185 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 212185 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 267257 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 267257 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 479442 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 479442 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 479442 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 479442 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1589383500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1589383500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3625603341 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3625603341 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 247000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 247000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5214986841 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5214986841 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5214986841 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5214986841 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000958 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001602 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7490.555412 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13565.980839 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35285.714286 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 75859 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17814.801426 # Cycle average of tags in use
|
||||
|
|
@ -424,36 +476,75 @@ system.cpu.l2cache.total_refs 464590 # To
|
|||
system.cpu.l2cache.sampled_refs 91380 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.084154 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 2079.678027 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15735.123399 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.063467 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.480198 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 179822 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 426654 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 206842 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 386664 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 386664 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 33662 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 60422 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 94084 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 94084 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1145731000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2079178500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 3224909500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 3224909500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 213484 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 426654 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 267264 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 480748 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 480748 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.157679 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.226076 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.195703 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.195703 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34036.331769 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34410.951309 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34276.917435 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34276.917435 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15735.123399 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 94.212469 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1985.465558 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.480198 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002875 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.060592 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.543665 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 179801 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 179822 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 426654 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 426654 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 206842 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 206842 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 386643 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 386664 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 386643 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 386664 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 1278 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 32384 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 33662 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 60422 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 60422 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1278 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 92806 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 94084 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1278 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 92806 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 94084 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 43747500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1101983500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1145731000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2079178500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2079178500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 43747500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 3181162000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 3224909500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 43747500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 3181162000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 3224909500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1299 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 212185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 213484 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 426654 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 426654 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 267264 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 267264 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1299 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 479449 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 480748 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1299 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 479449 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 480748 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983834 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.152622 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.226076 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983834 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.193568 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983834 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.193568 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34231.220657 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34028.640687 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34410.951309 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34231.220657 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34277.546710 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34231.220657 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34277.546710 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -462,30 +553,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 59257 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33662 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 60422 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 94084 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 94084 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1043686000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1892150500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2935836500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2935836500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157679 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.226076 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.195703 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.195703 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.871962 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.588693 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.418392 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.418392 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 59257 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59257 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1278 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32384 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 33662 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60422 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 60422 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1278 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 92806 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 94084 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1278 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 92806 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 94084 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39610000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1004076000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1043686000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1892150500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1892150500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39610000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2896226500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 2935836500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39610000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2896226500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 2935836500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.152622 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.226076 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193568 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193568 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30993.740219 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.311265 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.588693 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30993.740219 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31207.319570 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30993.740219 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31207.319570 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
|
|||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
|
@ -64,7 +77,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
|
||||
cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:02:00
|
||||
gem5 started Jan 23 2012 06:18:03
|
||||
gem5 compiled Feb 11 2012 13:08:33
|
||||
gem5 started Feb 11 2012 13:56:17
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.744764 # Nu
|
|||
sim_ticks 744764119000 # Number of ticks simulated
|
||||
final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3773289 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1886650577 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 205844 # Number of bytes of host memory used
|
||||
host_seconds 394.75 # Real time elapsed on the host
|
||||
sim_insts 1489523295 # Number of instructions simulated
|
||||
host_inst_rate 4631105 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 4644873 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2322443893 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 203508 # Number of bytes of host memory used
|
||||
host_seconds 320.68 # Real time elapsed on the host
|
||||
sim_insts 1485108101 # Number of instructions simulated
|
||||
sim_ops 1489523295 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 7326269637 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 5940452044 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 614672063 # Number of bytes written to this memory
|
||||
|
|
@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 49 # Nu
|
|||
system.cpu.numCycles 1489528239 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 1489523295 # Number of instructions executed
|
||||
system.cpu.committedInsts 1485108101 # Number of instructions committed
|
||||
system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1207835 # number of times a function call or return occured
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -58,20 +68,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -94,20 +97,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -115,6 +111,9 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
|
@ -130,20 +129,13 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -167,7 +159,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
|
||||
cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:02:00
|
||||
gem5 started Jan 23 2012 06:19:05
|
||||
gem5 compiled Feb 11 2012 13:08:33
|
||||
gem5 started Feb 11 2012 13:56:19
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 2.064259 # Nu
|
|||
sim_ticks 2064258667000 # Number of ticks simulated
|
||||
final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1766930 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2448703239 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214556 # Number of bytes of host memory used
|
||||
host_seconds 843.00 # Real time elapsed on the host
|
||||
sim_insts 1489523295 # Number of instructions simulated
|
||||
host_inst_rate 2132645 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2138986 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2964317062 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 212372 # Number of bytes of host memory used
|
||||
host_seconds 696.37 # Real time elapsed on the host
|
||||
sim_insts 1485108101 # Number of instructions simulated
|
||||
sim_ops 1489523295 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5909952 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 70592 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3778240 # Number of bytes written to this memory
|
||||
|
|
@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 49 # Nu
|
|||
system.cpu.numCycles 4128517334 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 1489523295 # Number of instructions executed
|
||||
system.cpu.committedInsts 1485108101 # Number of instructions committed
|
||||
system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1207835 # number of times a function call or return occured
|
||||
|
|
@ -47,26 +50,39 @@ system.cpu.icache.total_refs 1485111905 # To
|
|||
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 906.450625 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.442603 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 1485111905 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 1485111905 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 1485111905 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 1107 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 1485113012 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 906.450625 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.442603 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.442603 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1485111905 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1485111905 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1485111905 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1107 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 61824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 61824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 61824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 61824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 61824000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 61824000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1485113012 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1107 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 1107 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 1107 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58503000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 58503000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58503000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 58503000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 449125 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use
|
||||
|
|
@ -102,38 +116,59 @@ system.cpu.dcache.total_refs 568907765 # To
|
|||
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4095.226955 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999811 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 166587088 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits 568906446 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 568906446 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 259728 # number of WriteReq misses
|
||||
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
|
||||
system.cpu.dcache.demand_misses 453214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 453214 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 4019834000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 6156948000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 392000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 10176782000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 10176782000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20775.839079 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23705.368693 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 22454.694692 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 22454.694692 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4095.226955 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999811 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999811 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 402319358 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 568906446 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 568906446 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 568906446 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 568906446 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 259728 # number of WriteReq misses
|
||||
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 453214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 453214 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4019834000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4019834000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6156948000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 6156948000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 392000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 392000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10176782000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10176782000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10176782000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10176782000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 569359660 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 569359660 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -142,34 +177,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 407009 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 259728 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 453214 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 453214 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3439376000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5377764000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 371000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 8817140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 8817140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17775.839079 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20705.368693 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 407009 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 407009 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 259728 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 453214 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3439376000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3439376000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5377764000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5377764000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 371000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 371000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8817140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 74112 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use
|
||||
|
|
@ -177,36 +216,75 @@ system.cpu.l2cache.total_refs 427085 # To
|
|||
system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 1873.919591 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15849.385934 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.057187 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.483685 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 162275 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 407009 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 199710 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 361985 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 361985 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 32318 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 60025 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 92343 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 92343 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1680536000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3121300000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 4801836000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 4801836000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 407009 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.166080 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.231101 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.203252 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.203252 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15849.385934 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 72.801131 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1801.118460 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.483685 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002222 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.054966 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.540872 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 4 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 162271 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 162275 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 407009 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 407009 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 199710 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 199710 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 361981 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 361985 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 4 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 361981 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 361985 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 1103 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 31215 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 32318 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 60025 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 60025 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1103 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 92343 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1103 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 92343 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57356000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1623180000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1680536000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3121300000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3121300000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 57356000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4744480000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4801836000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 57356000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4744480000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4801836000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 407009 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 407009 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 259735 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 259735 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1107 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 453221 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 454328 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996387 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.161330 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231101 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996387 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.201315 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996387 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -215,30 +293,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 59035 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32318 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 60025 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 92343 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 92343 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1292720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2401000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3693720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3693720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.231101 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.203252 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.203252 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 59035 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59035 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1103 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31215 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 32318 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60025 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 60025 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1103 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 92343 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1103 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 92343 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44120000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1248600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1292720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2401000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2401000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3693720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649600000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3693720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.161330 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -136,20 +136,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -442,20 +435,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -494,20 +480,13 @@ is_top_level=false
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -531,12 +510,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
|
||||
cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 9 2012 12:45:55
|
||||
gem5 started Feb 9 2012 12:46:40
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:08:06
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.586835 # Nu
|
|||
sim_ticks 586834596000 # Number of ticks simulated
|
||||
final_tick 586834596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 99458 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 35994653 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253740 # Number of bytes of host memory used
|
||||
host_seconds 16303.38 # Real time elapsed on the host
|
||||
sim_insts 1621493982 # Number of instructions simulated
|
||||
host_inst_rate 106927 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 197018 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 71302744 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 220908 # Number of bytes of host memory used
|
||||
host_seconds 8230.18 # Real time elapsed on the host
|
||||
sim_insts 880025312 # Number of instructions simulated
|
||||
sim_ops 1621493982 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5879616 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 57024 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3743488 # Number of bytes written to this memory
|
||||
|
|
@ -236,7 +238,8 @@ system.cpu.iew.wb_penalized 0 # nu
|
|||
system.cpu.iew.wb_rate 1.495458 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.672132 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 350742946 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 7896364 # The number of times a branch was mispredicted
|
||||
|
|
@ -257,7 +260,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
|
|||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 1125303290 # Number of insts commited each cycle
|
||||
system.cpu.commit.count 1621493982 # Number of instructions committed
|
||||
system.cpu.commit.committedInsts 880025312 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 607228182 # Number of memory references committed
|
||||
system.cpu.commit.loads 419042125 # Number of loads committed
|
||||
|
|
@ -272,12 +276,13 @@ system.cpu.rob.rob_reads 3082456564 # Th
|
|||
system.cpu.rob.rob_writes 3992764754 # The number of ROB writes
|
||||
system.cpu.timesIdled 21723 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 94408 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.723820 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.723820 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.381560 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.381560 # IPC: Total IPC of All Threads
|
||||
system.cpu.committedInsts 880025312 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.333677 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.333677 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.749807 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.749807 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 3268959976 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1746565098 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 12 # number of floating regfile reads
|
||||
|
|
@ -288,26 +293,39 @@ system.cpu.icache.total_refs 136532946 # To
|
|||
system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 152721.416107 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 807.278486 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.394179 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 136532946 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 136532946 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 136532946 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 1228 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 1228 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 1228 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 43195500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 43195500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 43195500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 136534174 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 136534174 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 136534174 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35175.488599 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 35175.488599 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 35175.488599 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 807.278486 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.394179 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.394179 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 136532946 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 136532946 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 136532946 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 136532946 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 136532946 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 136532946 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1228 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1228 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1228 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1228 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1228 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1228 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 43195500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 43195500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 43195500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 43195500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 43195500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 43195500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 136534174 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 136534174 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 136534174 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 136534174 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 136534174 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 136534174 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35175.488599 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35175.488599 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35175.488599 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -316,27 +334,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 334 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 334 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 334 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 894 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 894 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 894 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 31569000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 31569000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 31569000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.080537 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35312.080537 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35312.080537 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 334 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 894 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 894 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 894 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 894 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 894 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 894 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31569000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 31569000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31569000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 31569000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31569000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 31569000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35312.080537 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35312.080537 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35312.080537 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 459037 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.269422 # Cycle average of tags in use
|
||||
|
|
@ -344,32 +365,49 @@ system.cpu.dcache.total_refs 430357004 # To
|
|||
system.cpu.dcache.sampled_refs 463133 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 929.229841 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 414463000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4094.269422 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999577 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 242420503 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 187936501 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 430357004 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 430357004 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 217102 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 249556 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 466658 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 466658 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 2192767500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 3219007000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 5411774500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 5411774500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 242637605 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 430823662 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 430823662 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000895 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001326 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.001083 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.001083 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 10100.171809 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 12898.936511 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 11596.875013 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 11596.875013 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.269422 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999577 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999577 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 242420503 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 242420503 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 187936501 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 187936501 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 430357004 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 430357004 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 430357004 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 430357004 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 217102 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 217102 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 249556 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 249556 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 466658 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 466658 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 466658 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 466658 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2192767500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2192767500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3219007000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3219007000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 5411774500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 5411774500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 5411774500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 5411774500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 242637605 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 242637605 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 430823662 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 430823662 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 430823662 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 430823662 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000895 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001326 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.001083 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.001083 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10100.171809 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12898.936511 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 11596.875013 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 11596.875013 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -378,32 +416,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 409999 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 3488 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 35 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 3523 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 3523 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 213614 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 249521 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 463135 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 463135 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1523998500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2469759000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3993757500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3993757500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000880 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.001075 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.001075 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7134.356831 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9898.000569 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 8623.311777 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 8623.311777 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 409999 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 409999 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3488 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 35 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 3523 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 3523 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 3523 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 3523 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 213614 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 213614 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249521 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 249521 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 463135 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 463135 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 463135 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 463135 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1523998500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1523998500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2469759000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2469759000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3993757500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 3993757500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3993757500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 3993757500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000880 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001326 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001075 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001075 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7134.356831 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9898.000569 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 73601 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17971.586292 # Cycle average of tags in use
|
||||
|
|
@ -411,36 +457,75 @@ system.cpu.l2cache.total_refs 452847 # To
|
|||
system.cpu.l2cache.sampled_refs 89223 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.075451 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 1981.498209 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15990.088083 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.060471 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.487979 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 181345 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 409999 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 190815 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 372160 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 372160 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 33162 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 58707 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 91869 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 91869 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1129684500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2008512000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 3138196500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 3138196500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 214507 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 409999 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 249522 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 464029 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 464029 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.154596 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.235278 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.197981 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.197981 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34065.632350 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34212.478921 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34159.471639 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34159.471639 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15990.088083 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 59.987883 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1921.510326 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.487979 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001831 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.058640 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.548449 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 181342 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 181345 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 409999 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 409999 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 190815 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 190815 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 372157 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 372160 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 372157 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 372160 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 891 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 32271 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 33162 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 58707 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 58707 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 891 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 90978 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 91869 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 891 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 90978 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 91869 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30543500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1099141000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1129684500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2008512000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2008512000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 30543500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 3107653000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 3138196500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 30543500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 3107653000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 3138196500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 894 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 213613 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 214507 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 409999 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 409999 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 249522 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 249522 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 894 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 463135 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 464029 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 894 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 463135 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 464029 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996644 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.151072 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235278 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996644 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.196439 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996644 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.196439 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34280.022447 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34059.713055 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34212.478921 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34280.022447 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34158.291015 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34280.022447 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34158.291015 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -449,30 +534,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 58492 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33162 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 58707 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 91869 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 91869 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1028173500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1819949000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2848122500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2848122500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154596 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235278 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.197981 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.197981 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.568482 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.545080 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 58492 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 58492 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 891 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32271 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 33162 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58707 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 58707 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 891 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 90978 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 91869 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 891 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 90978 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 91869 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27674500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1000499000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028173500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1819949000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1819949000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27674500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2820448000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 2848122500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27674500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2820448000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 2848122500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151072 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235278 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.196439 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.196439 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.044893 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.036782 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.545080 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.044893 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.428917 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.044893 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.428917 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -52,11 +62,34 @@ icache_port=system.membus.port[2]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.port[5]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[7]
|
||||
pio=system.membus.port[6]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.port[4]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -64,7 +97,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
|
||||
cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -88,7 +121,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:33:19
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:08:56
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.963993 # Nu
|
|||
sim_ticks 963992704000 # Number of ticks simulated
|
||||
final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2202720 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1309536712 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 204800 # Number of bytes of host memory used
|
||||
host_seconds 736.13 # Real time elapsed on the host
|
||||
sim_insts 1621493983 # Number of instructions simulated
|
||||
host_inst_rate 1632386 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3007760 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1788140018 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 210284 # Number of bytes of host memory used
|
||||
host_seconds 539.10 # Real time elapsed on the host
|
||||
sim_insts 880025313 # Number of instructions simulated
|
||||
sim_ops 1621493983 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 11334586825 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 9492133912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 864451000 # Number of bytes written to this memory
|
||||
|
|
@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 48 # Nu
|
|||
system.cpu.numCycles 1927985409 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 1621493983 # Number of instructions executed
|
||||
system.cpu.committedInsts 880025313 # Number of instructions committed
|
||||
system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -58,20 +68,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -94,20 +104,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -115,9 +118,25 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[4]
|
||||
pio=system.membus.port[3]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
|
|
@ -130,25 +149,18 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.port[4]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
|
@ -159,7 +171,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -167,7 +179,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
|
||||
cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -191,7 +203,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:37:10
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:11:10
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 1.803259 # Nu
|
|||
sim_ticks 1803258587000 # Number of ticks simulated
|
||||
final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1279975 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1423455894 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213784 # Number of bytes of host memory used
|
||||
host_seconds 1266.82 # Real time elapsed on the host
|
||||
sim_insts 1621493983 # Number of instructions simulated
|
||||
host_inst_rate 972144 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1791227 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1992018099 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 219200 # Number of bytes of host memory used
|
||||
host_seconds 905.24 # Real time elapsed on the host
|
||||
sim_insts 880025313 # Number of instructions simulated
|
||||
sim_ops 1621493983 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5725952 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 46208 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3712448 # Number of bytes written to this memory
|
||||
|
|
@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 48 # Nu
|
|||
system.cpu.numCycles 3606517174 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 1621493983 # Number of instructions executed
|
||||
system.cpu.committedInsts 880025313 # Number of instructions committed
|
||||
system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
|
|
@ -47,26 +50,39 @@ system.cpu.icache.total_refs 1186516018 # To
|
|||
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 1186516018 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 722 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 722 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 660.186297 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.322357 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.322357 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1186516018 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1186516018 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1186516018 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 722 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 40432000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 40432000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 40432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 40432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 40432000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 40432000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1186516740 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1186516740 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1186516740 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1186516740 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38266000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 437952 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use
|
||||
|
|
@ -102,32 +116,49 @@ system.cpu.dcache.total_refs 606786134 # To
|
|||
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 187941335 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 606786134 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 442048 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 5872734000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001300 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.896939 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999731 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999731 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 187941335 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 606786134 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 606786134 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 606786134 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 606786134 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 442048 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4043270000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4043270000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5872734000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5872734000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9916004000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9916004000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9916004000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9916004000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 607228182 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 607228182 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 607228182 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 607228182 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 396372 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 8589860000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000728 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 396372 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 396372 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3451292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3451292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5138568000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5138568000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8589860000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8589860000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8589860000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8589860000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 71208 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use
|
||||
|
|
@ -167,36 +200,72 @@ system.cpu.l2cache.total_refs 423014 # To
|
|||
system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 186469 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 353302 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 58253 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 89468 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1623180000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 396372 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16187.723361 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 48.180025 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1821.019706 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.494010 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001470 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.055573 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.551054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 166833 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 166833 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 396372 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 396372 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 186469 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 186469 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 353302 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 353302 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 353302 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 353302 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 30493 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 31215 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 58253 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 58253 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 88746 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 89468 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 88746 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 89468 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37544000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1585636000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1623180000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3029156000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3029156000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 37544000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4614792000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4652336000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 37544000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4614792000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4652336000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 396372 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 396372 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 244722 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 244722 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 442048 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 442770 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 442048 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154531 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238037 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200761 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200761 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -205,30 +274,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 58007 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3578720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 58007 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 58007 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30493 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 31215 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58253 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 58253 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 88746 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 89468 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 88746 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 89468 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1219720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1248600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2330120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2330120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3549840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3578720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3549840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3578720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238037 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -136,20 +136,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -444,20 +437,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -492,20 +478,13 @@ is_top_level=false
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -529,14 +508,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 10 2012 00:18:03
|
||||
gem5 started Feb 10 2012 00:18:22
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
gem5 compiled Feb 11 2012 13:10:40
|
||||
gem5 started Feb 11 2012 15:46:15
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.033081 # Nu
|
|||
sim_ticks 33080570000 # Number of ticks simulated
|
||||
final_tick 33080570000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 45520 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 16502276 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 388968 # Number of bytes of host memory used
|
||||
host_seconds 2004.61 # Real time elapsed on the host
|
||||
sim_insts 91249885 # Number of instructions simulated
|
||||
host_inst_rate 183696 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 185015 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 67072888 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 356156 # Number of bytes of host memory used
|
||||
host_seconds 493.20 # Real time elapsed on the host
|
||||
sim_insts 90599331 # Number of instructions simulated
|
||||
sim_ops 91249885 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 997440 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 44864 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 2048 # Number of bytes written to this memory
|
||||
|
|
@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu
|
|||
system.cpu.iew.wb_rate 1.549573 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.621804 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 91262494 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedInsts 90611940 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 91262494 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 26696996 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 554844 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 1392644 # The number of times a branch was mispredicted
|
||||
|
|
@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
|
|||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 62124345 # Number of insts commited each cycle
|
||||
system.cpu.commit.count 91262494 # Number of instructions committed
|
||||
system.cpu.commit.committedInsts 90611940 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 91262494 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 27322621 # Number of memory references committed
|
||||
system.cpu.commit.loads 22575872 # Number of loads committed
|
||||
|
|
@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 175546960 # Th
|
|||
system.cpu.rob.rob_writes 239939856 # The number of ROB writes
|
||||
system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 29796 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 91249885 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 91249885 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.725055 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.725055 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.379207 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.379207 # IPC: Total IPC of All Threads
|
||||
system.cpu.committedInsts 90599331 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 91249885 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 90599331 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.730261 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.730261 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.369374 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.369374 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 496902735 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 120936098 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 197 # number of floating regfile reads
|
||||
|
|
@ -336,26 +341,39 @@ system.cpu.icache.total_refs 14743811 # To
|
|||
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 20420.790859 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 611.587679 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.298627 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 14743811 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 14743811 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 14743811 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 916 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 916 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 916 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 32376000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 32376000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 32376000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 14744727 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 14744727 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 14744727 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000062 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000062 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000062 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35344.978166 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 35344.978166 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 35344.978166 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 611.587679 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.298627 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.298627 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 14743811 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 14743811 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 14743811 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 14743811 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 14743811 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 14743811 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 916 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 916 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 916 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 916 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 916 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 916 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32376000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32376000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32376000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32376000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32376000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32376000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 14744727 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 14744727 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 14744727 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 14744727 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 14744727 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 14744727 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000062 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000062 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000062 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35344.978166 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35344.978166 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35344.978166 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -364,27 +382,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 194 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 194 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 24887000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 24887000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 24887000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000049 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000049 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000049 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34469.529086 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 194 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 194 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 194 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 194 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 194 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24887000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 24887000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24887000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 24887000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24887000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 24887000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000049 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34469.529086 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34469.529086 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34469.529086 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 943456 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3558.808733 # Cycle average of tags in use
|
||||
|
|
@ -392,40 +413,63 @@ system.cpu.dcache.total_refs 28819271 # To
|
|||
system.cpu.dcache.sampled_refs 947552 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 30.414448 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 12353041000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 3558.808733 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.868850 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 24247440 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 4559242 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 6797 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits 5792 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits 28806682 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 28806682 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 989267 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 175739 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses 1165006 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 1165006 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 5475545000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 4498707428 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 9974252428 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 9974252428 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 25236707 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses 6804 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses 5792 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 29971688 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 29971688 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.039200 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.037115 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.001029 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.038870 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.038870 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 5534.951636 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25598.799515 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 8561.545973 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 8561.545973 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3558.808733 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.868850 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.868850 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 24247440 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 24247440 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4559242 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 4559242 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 6797 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 6797 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 5792 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 5792 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 28806682 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 28806682 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 28806682 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 28806682 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 989267 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 989267 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 175739 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 175739 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1165006 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1165006 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1165006 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1165006 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5475545000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5475545000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4498707428 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4498707428 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 124500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 124500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9974252428 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9974252428 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9974252428 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9974252428 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 25236707 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 25236707 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6804 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 6804 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5792 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 5792 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 29971688 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 29971688 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 29971688 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 29971688 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039200 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037115 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001029 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.038870 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.038870 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5534.951636 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25598.799515 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17785.714286 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 8561.545973 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 8561.545973 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 23239503 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 8123 # number of cycles access was blocked
|
||||
|
|
@ -434,33 +478,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.950757
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 942907 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 86240 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 131213 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 217453 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 217453 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 903027 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 44526 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 947553 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 947553 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2253076500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1081063056 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3334139556 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3334139556 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035782 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009404 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.031615 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.031615 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2495.026727 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.366123 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3518.683974 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3518.683974 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 942907 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 942907 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86240 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 86240 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131213 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 131213 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 217453 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 217453 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 217453 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 217453 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903027 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 903027 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 44526 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 44526 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 947553 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 947553 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 947553 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 947553 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2253076500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2253076500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1081063056 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1081063056 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3334139556 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 3334139556 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3334139556 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 3334139556 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035782 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009404 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031615 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031615 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2495.026727 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24279.366123 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3518.683974 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3518.683974 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 744 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 9229.669691 # Cycle average of tags in use
|
||||
|
|
@ -468,36 +521,75 @@ system.cpu.l2cache.total_refs 1596774 # To
|
|||
system.cpu.l2cache.sampled_refs 15569 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 102.561115 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 392.792276 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 8836.877415 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.011987 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.269680 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 901413 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 942907 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 31267 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 932680 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 932680 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 1057 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 14538 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 15595 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 15595 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 36209000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 498763000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 534972000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 534972000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 902470 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 942907 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 45805 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 948275 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 948275 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.001171 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.317389 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.016446 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.016446 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34256.385998 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34307.538864 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34304.071818 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34304.071818 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 8836.877415 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 199.760007 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 193.032269 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.269680 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.006096 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.005891 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.281667 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 901393 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 901413 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 942907 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 942907 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 31267 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 31267 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 932660 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 932680 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 932660 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 932680 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 702 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 355 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1057 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 702 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14893 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15595 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 702 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14893 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15595 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24071000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12138000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 36209000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 498763000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 498763000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 24071000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 510901000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 534972000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 24071000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 510901000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 534972000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 901748 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 902470 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 942907 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 942907 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 45805 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 45805 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 947553 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 948275 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 947553 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 948275 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.972299 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000394 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.317389 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.972299 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015717 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.972299 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015717 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.173789 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34191.549296 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34307.538864 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.173789 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34304.774055 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.173789 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34304.774055 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -506,31 +598,53 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 32 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1047 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 14538 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 15585 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 15585 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 32560500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451777500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 484338000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 484338000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001160 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317389 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.016435 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.016435 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.853868 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.629385 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 32 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 701 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 346 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1047 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 701 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 14884 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 15585 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 701 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14884 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15585 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21793500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10767000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32560500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 451777500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 451777500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21793500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462544500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 484338000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21793500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462544500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 484338000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000384 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.317389 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015708 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015708 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31089.158345 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31118.497110 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31075.629385 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31089.158345 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31076.625907 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31089.158345 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31076.625907 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.membus.port[5]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.membus.port[4]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -64,7 +95,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
|
||||
cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -88,7 +119,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:47:31
|
||||
gem5 compiled Feb 11 2012 13:10:40
|
||||
gem5 started Feb 11 2012 15:51:19
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.054241 # Nu
|
|||
sim_ticks 54240666000 # Number of ticks simulated
|
||||
final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2777644 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1651027932 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 342980 # Number of bytes of host memory used
|
||||
host_seconds 32.85 # Real time elapsed on the host
|
||||
sim_insts 91252969 # Number of instructions simulated
|
||||
host_inst_rate 3177444 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3200257 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1902228216 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 345536 # Number of bytes of host memory used
|
||||
host_seconds 28.51 # Real time elapsed on the host
|
||||
sim_insts 90602415 # Number of instructions simulated
|
||||
sim_ops 91252969 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 521339715 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 431323116 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 18908138 # Number of bytes written to this memory
|
||||
|
|
@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 442 # Nu
|
|||
system.cpu.numCycles 108481333 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 91252969 # Number of instructions executed
|
||||
system.cpu.committedInsts 90602415 # Number of instructions committed
|
||||
system.cpu.committedOps 91252969 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 96832 # number of times a function call or return occured
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -58,20 +68,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.port[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -94,20 +106,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -115,9 +120,21 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.port[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
|
|
@ -130,25 +147,18 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.port[4]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
|
@ -159,7 +169,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -167,7 +177,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
|
||||
cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:48:15
|
||||
gem5 compiled Feb 11 2012 13:10:40
|
||||
gem5 started Feb 11 2012 15:51:58
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.148086 # Nu
|
|||
sim_ticks 148086239000 # Number of ticks simulated
|
||||
final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1300672 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2111359212 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 351948 # Number of bytes of host memory used
|
||||
host_seconds 70.14 # Real time elapsed on the host
|
||||
sim_insts 91226321 # Number of instructions simulated
|
||||
host_inst_rate 1696896 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1709063 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2774293546 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 354444 # Number of bytes of host memory used
|
||||
host_seconds 53.38 # Real time elapsed on the host
|
||||
sim_insts 90576869 # Number of instructions simulated
|
||||
sim_ops 91226321 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 986112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 36992 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 2048 # Number of bytes written to this memory
|
||||
|
|
@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 442 # Nu
|
|||
system.cpu.numCycles 296172478 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 91226321 # Number of instructions executed
|
||||
system.cpu.committedInsts 90576869 # Number of instructions committed
|
||||
system.cpu.committedOps 91226321 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 96832 # number of times a function call or return occured
|
||||
|
|
@ -89,26 +92,39 @@ system.cpu.icache.total_refs 107830181 # To
|
|||
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.249187 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 107830181 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 107830181 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 107830181 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 599 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 599 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 599 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 32662000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 32662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 32662000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 107830780 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 107830780 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 54527.545910 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 54527.545910 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.335448 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 107830181 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 107830181 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 107830181 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 107830181 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 107830181 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 107830181 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 599 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32662000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32662000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 107830780 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 107830780 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 107830780 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 107830780 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 599 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 599 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 599 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 30865000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 30865000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 30865000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 942702 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use
|
||||
|
|
@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 26345365 # To
|
|||
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 21649219 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 4688372 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits 26337591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 26337591 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 900189 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 46609 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 946798 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 946798 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 12614490000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 1263542000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 13878032000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 13878032000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 22549408 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 27284389 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.039921 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.009844 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.034701 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.034701 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 14657.859438 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3568.549501 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.871228 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.871228 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21649219 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21649219 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26337591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26337591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26337591 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26337591 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 946798 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12614490000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12614490000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1263542000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1263542000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13878032000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13878032000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13878032000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13878032000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22549408 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22549408 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 27284389 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 27284389 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 27284389 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 27284389 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 942309 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 900189 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 46609 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 946798 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 9913923000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1123715000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 11037638000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 11037638000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.039921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009844 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.034701 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.034701 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 942309 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 942309 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9913923000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9913923000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11037638000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11037638000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11037638000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11037638000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 634 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use
|
||||
|
|
@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 1594542 # To
|
|||
system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 325.097811 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 8910.209882 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.009921 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.271918 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 899928 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 942309 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 32061 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 931989 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 931989 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 860 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 14548 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 15408 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 15408 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 44720000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 756496000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 801216000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 801216000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 900788 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 942309 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 947397 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.000955 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.312129 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.016264 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.016264 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 8910.209882 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 165.071875 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 160.025936 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.271918 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005038 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.004884 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.281839 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 899907 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 899928 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 942309 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 942309 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 931968 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 931989 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 931968 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 931989 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 578 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 282 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 860 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 578 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14830 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15408 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14830 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15408 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30056000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14664000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 44720000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756496000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 756496000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 30056000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 771160000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 801216000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 30056000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 771160000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 801216000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 942309 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 942309 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000313 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015663 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015663 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 32 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 860 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 14548 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 15408 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 15408 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 34400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 581920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 616320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 616320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000955 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312129 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.016264 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.016264 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 32 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 578 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 282 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 860 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 578 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 14830 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 15408 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14830 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15408 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23120000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 581920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 581920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 593200000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 616320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 593200000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 616320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000313 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
|
|||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
|
@ -64,7 +77,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
|
||||
cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:02:00
|
||||
gem5 started Jan 23 2012 06:20:13
|
||||
gem5 compiled Feb 11 2012 13:08:33
|
||||
gem5 started Feb 11 2012 13:56:49
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.122216 # Nu
|
|||
sim_ticks 122215830000 # Number of ticks simulated
|
||||
final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3409932 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1709135687 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 338176 # Number of bytes of host memory used
|
||||
host_seconds 71.51 # Real time elapsed on the host
|
||||
sim_insts 243835278 # Number of instructions simulated
|
||||
host_inst_rate 4048457 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 4048623 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2029262264 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 335836 # Number of bytes of host memory used
|
||||
host_seconds 60.23 # Real time elapsed on the host
|
||||
sim_insts 243825163 # Number of instructions simulated
|
||||
sim_ops 243835278 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 1306360053 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 977686044 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 91606089 # Number of bytes written to this memory
|
||||
|
|
@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 443 # Nu
|
|||
system.cpu.numCycles 244431661 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 243835278 # Number of instructions executed
|
||||
system.cpu.committedInsts 243825163 # Number of instructions committed
|
||||
system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -58,20 +68,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -94,20 +97,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -115,6 +111,9 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
|
@ -130,20 +129,13 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -167,7 +159,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
|
||||
cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:02:00
|
||||
gem5 started Jan 23 2012 06:21:35
|
||||
gem5 compiled Feb 11 2012 13:08:33
|
||||
gem5 started Feb 11 2012 13:58:00
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.362431 # Nu
|
|||
sim_ticks 362430887000 # Number of ticks simulated
|
||||
final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1587659 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2359857170 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 346888 # Number of bytes of host memory used
|
||||
host_seconds 153.58 # Real time elapsed on the host
|
||||
sim_insts 243835278 # Number of instructions simulated
|
||||
host_inst_rate 1947938 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1948018 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2895487158 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 344700 # Number of bytes of host memory used
|
||||
host_seconds 125.17 # Real time elapsed on the host
|
||||
sim_insts 243825163 # Number of instructions simulated
|
||||
sim_ops 243835278 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 1001472 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 2560 # Number of bytes written to this memory
|
||||
|
|
@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 443 # Nu
|
|||
system.cpu.numCycles 724861774 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 243835278 # Number of instructions executed
|
||||
system.cpu.committedInsts 243825163 # Number of instructions committed
|
||||
system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
|
||||
|
|
@ -47,26 +50,39 @@ system.cpu.icache.total_refs 244420630 # To
|
|||
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 725.567632 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.354281 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 244420630 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 882 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 49266000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 49266000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 49266000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55857.142857 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 55857.142857 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 55857.142857 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 725.567632 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 244420630 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 882 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49266000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 49266000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 49266000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 49266000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 49266000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 46620000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 46620000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 46620000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52857.142857 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 935475 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use
|
||||
|
|
@ -102,38 +116,59 @@ system.cpu.dcache.total_refs 104186700 # To
|
|||
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 3563.824259 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.870074 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 22855241 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits 3882 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits 104182818 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 104182818 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 46710 # number of WriteReq misses
|
||||
system.cpu.dcache.SwapReq_misses 4 # number of SwapReq misses
|
||||
system.cpu.dcache.demand_misses 939567 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 939567 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 12508482000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 1265712000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 98000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 13774194000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 13774194000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002040 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.001029 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.008938 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14009.502082 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27097.238279 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 24500 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 14660.150899 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 14660.150899 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 104182818 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 104182818 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 104182818 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 104182818 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
|
||||
system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12508482000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12508482000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13774194000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13774194000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13774194000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13774194000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -142,34 +177,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 935237 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 46710 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 4 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 939567 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 9829911000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1125582000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 86000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10955493000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10955493000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002040 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.001029 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.008938 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.502082 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24097.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 21500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 935237 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9829911000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9829911000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10955493000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 865 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use
|
||||
|
|
@ -177,36 +216,75 @@ system.cpu.l2cache.total_refs 1585884 # To
|
|||
system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 375.506440 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 8861.245791 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.011460 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.270424 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 892658 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 935237 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 924805 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 924805 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 1081 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 14567 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 15648 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 15648 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 56212000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 757484000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 813696000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 813696000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 935237 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.001210 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.311834 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.016639 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.016639 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 8861.245791 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 244.574580 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 130.931861 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.270424 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.007464 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.003996 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.281883 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 892655 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 892658 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 935237 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 935237 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 924802 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 924805 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 924802 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 924805 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14769 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15648 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14769 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15648 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10504000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 56212000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 767988000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 813696000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 767988000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 813696000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 935237 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 935237 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -215,30 +293,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 40 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1081 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 15648 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 15648 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 43240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 582680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 625920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 625920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001210 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.016639 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.016639 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 40 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 14769 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 15648 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14769 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15648 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -136,20 +136,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -442,20 +435,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -494,20 +480,13 @@ is_top_level=false
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -531,14 +510,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 9 2012 12:45:55
|
||||
gem5 started Feb 9 2012 12:46:40
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:13:01
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.070047 # Nu
|
|||
sim_ticks 70046988500 # Number of ticks simulated
|
||||
final_tick 70046988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 78701 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 19816485 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 388420 # Number of bytes of host memory used
|
||||
host_seconds 3534.78 # Real time elapsed on the host
|
||||
sim_insts 278192519 # Number of instructions simulated
|
||||
host_inst_rate 120922 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 212925 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 53613076 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 355612 # Number of bytes of host memory used
|
||||
host_seconds 1306.53 # Real time elapsed on the host
|
||||
sim_insts 157988582 # Number of instructions simulated
|
||||
sim_ops 278192519 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 3895936 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 65216 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 892288 # Number of bytes written to this memory
|
||||
|
|
@ -236,7 +238,8 @@ system.cpu.iew.wb_penalized 0 # nu
|
|||
system.cpu.iew.wb_rate 2.229177 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.730584 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 65103374 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 1332005 # The number of times a branch was mispredicted
|
||||
|
|
@ -257,7 +260,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
|
|||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 130436298 # Number of insts commited each cycle
|
||||
system.cpu.commit.count 278192519 # Number of instructions committed
|
||||
system.cpu.commit.committedInsts 157988582 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 122219139 # Number of memory references committed
|
||||
system.cpu.commit.loads 90779388 # Number of loads committed
|
||||
|
|
@ -272,12 +276,13 @@ system.cpu.rob.rob_reads 457952368 # Th
|
|||
system.cpu.rob.rob_writes 695479183 # The number of ROB writes
|
||||
system.cpu.timesIdled 23894 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 787486 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.503586 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.503586 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.985756 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.985756 # IPC: Total IPC of All Threads
|
||||
system.cpu.committedInsts 157988582 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.886735 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.886735 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.127733 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.127733 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 554395898 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 279799467 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 352 # number of floating regfile reads
|
||||
|
|
@ -289,26 +294,39 @@ system.cpu.icache.total_refs 28212585 # To
|
|||
system.cpu.icache.sampled_refs 1024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 27551.352539 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 822.534021 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.401628 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 28212585 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 28212585 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 28212585 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 1300 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 1300 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 1300 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 46952500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 46952500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 46952500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 28213885 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 28213885 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 28213885 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36117.307692 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 36117.307692 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 36117.307692 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 822.534021 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.401628 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.401628 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 28212585 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 28212585 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 28212585 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 28212585 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 28212585 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 28212585 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1300 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1300 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1300 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1300 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1300 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1300 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 46952500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 46952500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 46952500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 46952500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 46952500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 46952500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 28213885 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 28213885 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 28213885 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 28213885 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 28213885 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 28213885 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000046 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000046 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000046 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36117.307692 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -317,27 +335,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 275 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 275 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 1025 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 1025 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 1025 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 36071500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 36071500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 36071500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35191.707317 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35191.707317 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35191.707317 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 275 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 275 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 275 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 275 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 275 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 1025 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 1025 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1025 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1025 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 36071500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 36071500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 36071500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35191.707317 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35191.707317 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35191.707317 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2072906 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4073.029614 # Cycle average of tags in use
|
||||
|
|
@ -345,32 +366,49 @@ system.cpu.dcache.total_refs 77489413 # To
|
|||
system.cpu.dcache.sampled_refs 2077002 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 37.308300 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 23588256000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4073.029614 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.994392 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 46135653 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 31353751 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 77489404 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 77489404 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 2289012 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 86000 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 2375012 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 2375012 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 13766771000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 1501245288 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 15268016288 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 15268016288 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 48424665 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 79864416 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 79864416 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.047270 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002735 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.029738 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.029738 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 6014.285203 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 17456.340558 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 6428.605956 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 6428.605956 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4073.029614 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.994392 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.994392 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 46135653 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 46135653 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31353751 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 31353751 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 77489404 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 77489404 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 77489404 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 77489404 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 2289012 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 2289012 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 86000 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 86000 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2375012 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2375012 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2375012 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2375012 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13766771000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 13766771000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1501245288 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1501245288 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 15268016288 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 15268016288 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 15268016288 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 15268016288 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 48424665 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 48424665 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 79864416 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 79864416 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 79864416 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 79864416 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047270 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002735 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.029738 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.029738 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6014.285203 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17456.340558 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 6428.605956 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 6428.605956 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -379,32 +417,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 1880780 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 294089 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 3918 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 298007 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 298007 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1994923 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 82082 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2077005 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2077005 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 5565133500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1157645788 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 6722779288 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 6722779288 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.041196 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002611 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.026007 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.026007 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2789.648272 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14103.528033 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3236.766059 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3236.766059 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 1880780 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1880780 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 294089 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 294089 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3918 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 3918 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 298007 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 298007 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 298007 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 298007 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994923 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1994923 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82082 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 82082 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2077005 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2077005 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2077005 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2077005 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5565133500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5565133500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1157645788 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1157645788 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6722779288 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6722779288 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6722779288 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6722779288 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041196 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2789.648272 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14103.528033 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3236.766059 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3236.766059 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 33246 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18964.988080 # Cycle average of tags in use
|
||||
|
|
@ -412,39 +458,80 @@ system.cpu.l2cache.total_refs 3764517 # To
|
|||
system.cpu.l2cache.sampled_refs 61253 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 61.458492 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 6037.038666 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 12927.949414 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.184236 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.394530 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1964445 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 1880780 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 52709 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 2017154 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 2017154 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 31361 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 29513 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 60874 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 60874 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1071202500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1006190000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 2077392500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 2077392500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 1995806 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 1880780 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 82222 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 2078028 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 2078028 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.015713 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.358943 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.029294 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.029294 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34157.153790 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34093.111510 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34126.104741 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34126.104741 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 12927.949414 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 243.086422 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 5793.952244 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.394530 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.007418 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.176817 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.578766 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1964440 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1964445 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1880780 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1880780 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 52709 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 52709 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2017149 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2017154 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2017149 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2017154 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 30342 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 31361 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 29513 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 29513 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 59855 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 60874 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1019 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 59855 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 60874 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34913500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1036289000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1071202500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1006190000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1006190000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 34913500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 2042479000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 2077392500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 34913500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 2042479000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 2077392500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1024 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1994782 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1995806 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1880780 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1880780 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 82222 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 82222 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1024 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2077004 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2078028 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1024 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2077004 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2078028 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995117 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015211 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358943 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995117 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.028818 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995117 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.028818 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34262.512267 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34153.615451 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34093.111510 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34262.512267 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34123.782474 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34262.512267 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34123.782474 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -453,34 +540,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 13942 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 31361 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 29513 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 60874 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 60874 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 972854000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 914925500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1887779500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1887779500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.015713 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.358943 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.029294 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.029294 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.140907 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.762376 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.260965 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.260965 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 13942 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 13942 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30342 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 31361 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29513 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 29513 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 59855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 60874 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 59855 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 60874 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31643000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 941211000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 972854000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 914925500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 914925500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31643000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856136500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1887779500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31643000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856136500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1887779500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015211 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358943 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.993131 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.071188 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.762376 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -52,11 +62,34 @@ icache_port=system.membus.port[2]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.port[5]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[7]
|
||||
pio=system.membus.port[6]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.port[4]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -64,7 +97,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
|
||||
cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -88,7 +121,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:52:52
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:18:06
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.168950 # Nu
|
|||
sim_ticks 168950072000 # Number of ticks simulated
|
||||
final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2042288 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1240309006 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 339312 # Number of bytes of host memory used
|
||||
host_seconds 136.22 # Real time elapsed on the host
|
||||
sim_insts 278192520 # Number of instructions simulated
|
||||
host_inst_rate 1605694 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2827368 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1717098424 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 344660 # Number of bytes of host memory used
|
||||
host_seconds 98.39 # Real time elapsed on the host
|
||||
sim_insts 157988583 # Number of instructions simulated
|
||||
sim_ops 278192520 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 2458815679 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 1741569664 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 243173115 # Number of bytes written to this memory
|
||||
|
|
@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 444 # Nu
|
|||
system.cpu.numCycles 337900145 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 278192520 # Number of instructions executed
|
||||
system.cpu.committedInsts 157988583 # Number of instructions committed
|
||||
system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -58,20 +68,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -94,20 +104,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -115,9 +118,25 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[4]
|
||||
pio=system.membus.port[3]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
|
|
@ -130,25 +149,18 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.port[4]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
|
@ -159,7 +171,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -167,7 +179,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
|
||||
cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -191,7 +203,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:55:19
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:19:55
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.370011 # Nu
|
|||
sim_ticks 370010840000 # Number of ticks simulated
|
||||
final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1163147 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1547047043 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 348152 # Number of bytes of host memory used
|
||||
host_seconds 239.17 # Real time elapsed on the host
|
||||
sim_insts 278192520 # Number of instructions simulated
|
||||
host_inst_rate 912216 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1606265 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2136418129 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 353708 # Number of bytes of host memory used
|
||||
host_seconds 173.19 # Real time elapsed on the host
|
||||
sim_insts 157988583 # Number of instructions simulated
|
||||
sim_ops 278192520 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 4900800 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 1885440 # Number of bytes written to this memory
|
||||
|
|
@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 444 # Nu
|
|||
system.cpu.numCycles 740021680 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 278192520 # Number of instructions executed
|
||||
system.cpu.committedInsts 157988583 # Number of instructions committed
|
||||
system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
|
|
@ -47,26 +50,39 @@ system.cpu.icache.total_refs 217695401 # To
|
|||
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 217695401 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 808 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 666.191948 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.325289 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.325289 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 217695401 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 217695401 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 808 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 45248000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 45248000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 45248000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 45248000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 45248000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 45248000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 217696209 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
|
||||
|
|
@ -102,32 +116,49 @@ system.cpu.dcache.total_refs 120152372 # To
|
|||
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 120152372 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 2066829 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.661903 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 120152372 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 120152372 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 120152372 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 120152372 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28849058000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 28849058000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3268793000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3268793000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 32117851000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 32117851000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 32117851000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 32117851000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 122219201 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 122219201 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 1437080 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 1437080 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1437080 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22966898000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22966898000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2950464500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2950464500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25917362500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 25917362500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25917362500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 25917362500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 49212 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use
|
||||
|
|
@ -167,36 +200,72 @@ system.cpu.l2cache.total_refs 3296079 # To
|
|||
system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 1991062 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 76575 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 12062.804989 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 196.794797 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 6355.003474 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.368128 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.006006 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.193939 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.568073 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1927411 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1927411 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1437080 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1437080 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 63651 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 63651 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1991062 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1991062 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1991062 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1991062 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 33309 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 34117 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 42458 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 42458 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 75767 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 76575 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 808 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 75767 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 76575 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1732068000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1774084000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2207845500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2207845500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 3939913500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 3981929500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 3939913500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 3981929500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1437080 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1437080 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.016988 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.400136 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.036659 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.036659 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -205,30 +274,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 29460 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 29460 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 29460 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33309 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 34117 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42458 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 42458 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 75767 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 76575 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 75767 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 76575 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1332360000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1364680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1698320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1698320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3030680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3063000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -136,20 +136,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -444,20 +437,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -492,20 +478,13 @@ is_top_level=false
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -529,14 +508,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 10 2012 00:18:03
|
||||
gem5 started Feb 10 2012 00:18:20
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
gem5 compiled Feb 11 2012 13:10:40
|
||||
gem5 started Feb 11 2012 15:53:02
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.274128 # Nu
|
|||
sim_ticks 274128411000 # Number of ticks simulated
|
||||
final_tick 274128411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 67477 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 32262353 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260864 # Number of bytes of host memory used
|
||||
host_seconds 8496.85 # Real time elapsed on the host
|
||||
sim_insts 573341187 # Number of instructions simulated
|
||||
host_inst_rate 133293 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 150155 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 71792865 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228092 # Number of bytes of host memory used
|
||||
host_seconds 3818.32 # Real time elapsed on the host
|
||||
sim_insts 508954626 # Number of instructions simulated
|
||||
sim_ops 573341187 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 15240192 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 229568 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 10959680 # Number of bytes written to this memory
|
||||
|
|
@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu
|
|||
system.cpu.iew.wb_rate 1.265299 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.595401 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 574685071 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedInsts 510298510 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 574685071 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 312438031 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 3878199 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 20478103 # The number of times a branch was mispredicted
|
||||
|
|
@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
|
|||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 495250570 # Number of insts commited each cycle
|
||||
system.cpu.commit.count 574685071 # Number of instructions committed
|
||||
system.cpu.commit.committedInsts 510298510 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 574685071 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 184376791 # Number of memory references committed
|
||||
system.cpu.commit.loads 126772935 # Number of loads committed
|
||||
|
|
@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 1367535962 # Th
|
|||
system.cpu.rob.rob_writes 1823647630 # The number of ROB writes
|
||||
system.cpu.timesIdled 94158 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 3785113 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 573341187 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 573341187 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.956249 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.956249 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.045753 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.045753 # IPC: Total IPC of All Threads
|
||||
system.cpu.committedInsts 508954626 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 573341187 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 508954626 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.077221 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.077221 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.928314 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.928314 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 3289345591 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 815117578 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
|
|
@ -335,26 +340,39 @@ system.cpu.icache.total_refs 141602716 # To
|
|||
system.cpu.icache.sampled_refs 14723 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 9617.789581 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 1062.179544 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.518642 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 141602717 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 141602717 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 141602717 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 16509 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 16509 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 16509 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 235489500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 235489500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 235489500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 141619226 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 141619226 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 141619226 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000117 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000117 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000117 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 14264.310376 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 14264.310376 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 14264.310376 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1062.179544 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.518642 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.518642 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 141602717 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 141602717 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 141602717 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 141602717 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 141602717 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 141602717 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 16509 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 16509 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 16509 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 16509 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 16509 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 16509 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 235489500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 235489500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 235489500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 235489500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 235489500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 235489500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 141619226 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 141619226 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 141619226 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 141619226 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 141619226 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 141619226 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000117 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000117 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000117 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14264.310376 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -363,27 +381,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 1 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 1646 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 1646 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 1646 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 14863 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 14863 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 14863 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 154537000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 154537000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 154537000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10397.429859 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 10397.429859 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 10397.429859 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1646 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 1646 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 1646 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 1646 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 1646 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 1646 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 14863 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 14863 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 14863 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 14863 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 14863 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 14863 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 154537000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 154537000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 154537000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 154537000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 154537000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 154537000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10397.429859 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1212291 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4058.220860 # Cycle average of tags in use
|
||||
|
|
@ -391,40 +414,63 @@ system.cpu.dcache.total_refs 203801196 # To
|
|||
system.cpu.dcache.sampled_refs 1216387 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 167.546345 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 5623769000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4058.220860 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.990777 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 146308743 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 52772298 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 2488014 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits 2231920 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits 199081041 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 199081041 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 1241922 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 1467008 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses 55 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses 2708930 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 2708930 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 14257023500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 24962643993 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 523000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 39219667493 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 39219667493 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 147550665 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses 2488069 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses 2231920 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 201789971 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 201789971 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.008417 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.027047 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.000022 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.013425 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.013425 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 11479.805898 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 17016.024448 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 9509.090909 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 14477.918401 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 14477.918401 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4058.220860 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.990777 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.990777 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 146308743 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 146308743 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 52772298 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 52772298 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 2488014 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 2488014 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 2231920 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 2231920 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 199081041 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 199081041 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 199081041 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 199081041 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1241922 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1241922 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1467008 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1467008 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 55 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 55 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2708930 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2708930 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2708930 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2708930 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14257023500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 14257023500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24962643993 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 24962643993 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 523000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 523000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 39219667493 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 39219667493 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 39219667493 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 39219667493 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 147550665 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 147550665 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2488069 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 2488069 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231920 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 2231920 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 201789971 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 201789971 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 201789971 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 201789971 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008417 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027047 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000022 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.013425 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.013425 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11479.805898 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17016.024448 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9509.090909 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14477.918401 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14477.918401 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 484000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -433,33 +479,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets 7934.426230 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 1079423 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 365990 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1126420 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 55 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 1492410 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 1492410 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 875932 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 340588 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 1216520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 1216520 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 6305474000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 4364186500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10669660500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10669660500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005936 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006279 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006029 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006029 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7198.588475 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12813.682514 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 8770.641255 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 8770.641255 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 1079423 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1079423 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365990 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 365990 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1126420 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1126420 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 55 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 55 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1492410 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1492410 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1492410 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1492410 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 875932 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 875932 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 340588 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 340588 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1216520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1216520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1216520 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1216520 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6305474000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6305474000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4364186500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4364186500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10669660500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10669660500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10669660500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10669660500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005936 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006279 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006029 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006029 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7198.588475 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12813.682514 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8770.641255 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8770.641255 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 218982 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21063.326998 # Cycle average of tags in use
|
||||
|
|
@ -467,42 +522,85 @@ system.cpu.l2cache.total_refs 1568375 # To
|
|||
system.cpu.l2cache.sampled_refs 239342 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 6.552862 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 204310095000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 7519.880092 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13543.446906 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.229489 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.413313 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 760536 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 1079424 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits 96 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits 232415 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 992951 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 992951 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 129729 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses 35 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 108423 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 238152 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 238152 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 4437312000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 171500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3713377000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 8150689000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 8150689000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 890265 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 1079424 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses 131 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 340838 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 1231103 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 1231103 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.145720 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.267176 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.318107 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.193446 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.193446 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34204.472400 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4900 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34248.978538 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34224.734623 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34224.734623 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 13543.446906 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 176.680615 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 7343.199477 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.413313 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005392 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.224097 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.642802 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 11134 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 749402 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 760536 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1079424 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1079424 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 96 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 96 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 232415 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 232415 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 11134 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 981817 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 992951 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 11134 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 981817 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 992951 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3590 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 126139 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 129729 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 108423 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 108423 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3590 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 234562 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 238152 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3590 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 234562 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 238152 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 123146500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4314165500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 4437312000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 171500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 171500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3713377000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3713377000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 123146500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8027542500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8150689000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 123146500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8027542500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8150689000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 14724 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 875541 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 890265 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1079424 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1079424 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 131 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 131 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 340838 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 340838 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 14724 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1216379 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 1231103 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 14724 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1216379 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1231103 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.243820 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.144070 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.267176 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.318107 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.243820 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.192836 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.243820 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.192836 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.646240 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34201.678307 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4900 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34248.978538 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.646240 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34223.542176 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.646240 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34223.542176 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -511,35 +609,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 171245 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 22 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 129707 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 108423 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 238130 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 238130 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4027357500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1085000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3362010000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 7389367500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 7389367500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.145695 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.267176 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.318107 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.193428 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.193428 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31049.654221 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.273152 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.813001 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.813001 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 171245 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 171245 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3587 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 126120 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 129707 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 108423 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 108423 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3587 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 234543 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 238130 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3587 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 234543 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 238130 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111526500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3915831000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4027357500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1085000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1085000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3362010000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3362010000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111526500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7277841000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 7389367500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111526500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7277841000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 7389367500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.144048 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.267176 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.318107 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.859493 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31048.453853 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.273152 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.membus.port[5]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.membus.port[4]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -64,7 +95,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
|
||||
cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -88,7 +119,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:54:41
|
||||
gem5 compiled Feb 11 2012 13:10:40
|
||||
gem5 started Feb 11 2012 15:54:26
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.290499 # Nu
|
|||
sim_ticks 290498972000 # Number of ticks simulated
|
||||
final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3123764 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1589318228 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213568 # Number of bytes of host memory used
|
||||
host_seconds 182.78 # Real time elapsed on the host
|
||||
sim_insts 570968176 # Number of instructions simulated
|
||||
host_inst_rate 2958479 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3334501 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1696537892 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 216124 # Number of bytes of host memory used
|
||||
host_seconds 171.23 # Real time elapsed on the host
|
||||
sim_insts 506581615 # Number of instructions simulated
|
||||
sim_ops 570968176 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 2489298238 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 2066445536 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 216067624 # Number of bytes written to this memory
|
||||
|
|
@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 548 # Nu
|
|||
system.cpu.numCycles 580997945 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 570968176 # Number of instructions executed
|
||||
system.cpu.committedInsts 506581615 # Number of instructions committed
|
||||
system.cpu.committedOps 570968176 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -58,20 +68,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.port[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -94,20 +106,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -115,9 +120,21 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
max_backoff=100000
|
||||
min_backoff=0
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.port[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
|
|
@ -130,25 +147,18 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.port[4]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
|
@ -159,7 +169,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -167,7 +177,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
|
||||
cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:54:55
|
||||
gem5 compiled Feb 11 2012 13:10:40
|
||||
gem5 started Feb 11 2012 15:54:39
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.722234 # Nu
|
|||
sim_ticks 722234364000 # Number of ticks simulated
|
||||
final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1518630 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1927485562 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222536 # Number of bytes of host memory used
|
||||
host_seconds 374.70 # Real time elapsed on the host
|
||||
sim_insts 569034848 # Number of instructions simulated
|
||||
host_inst_rate 1769028 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1993395 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2530070907 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225284 # Number of bytes of host memory used
|
||||
host_seconds 285.46 # Real time elapsed on the host
|
||||
sim_insts 504986861 # Number of instructions simulated
|
||||
sim_ops 569034848 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 14797056 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 11027328 # Number of bytes written to this memory
|
||||
|
|
@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 548 # Nu
|
|||
system.cpu.numCycles 1444468728 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 569034848 # Number of instructions executed
|
||||
system.cpu.committedInsts 504986861 # Number of instructions committed
|
||||
system.cpu.committedOps 569034848 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
|
||||
|
|
@ -89,26 +92,39 @@ system.cpu.icache.total_refs 516599864 # To
|
|||
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 516599864 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 11521 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 984.426148 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.480677 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.480677 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 516599864 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 516599864 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 516599864 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 516599864 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 516599864 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 516599864 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11521 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 285068000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 285068000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 285068000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 285068000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 285068000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 285068000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 516611385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 516611385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 516611385 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 516611385 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250505000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 250505000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250505000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 250505000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
|
||||
|
|
@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 179817787 # To
|
|||
system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 176840705 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 1138918 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4065.490059 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.992551 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.992551 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 122957659 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 122957659 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 176840705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 176840705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 176840705 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 176840705 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 15502704000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 15502704000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10028942000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10028942000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 25531646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 25531646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 25531646000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 25531646000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 123740317 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 123740317 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 177979623 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 177979623 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 1025440 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1025440 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13154730000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 13154730000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8960162000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8960162000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22114892000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 212089 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
|
||||
|
|
@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 1426644 # To
|
|||
system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 919235 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 231204 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 14594.006011 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 132.842413 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 5716.315189 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.445374 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.174448 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.623876 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8574 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 674432 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 683006 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1025440 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1025440 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 236229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 236229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 8574 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 910661 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 919235 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 8574 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 910661 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 919235 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2947 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 108226 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 111173 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 120031 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 120031 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2947 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 228257 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 231204 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2947 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 228257 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 231204 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153244000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5627752000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 5780996000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6241612000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6241612000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 153244000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 11869364000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 12022608000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 153244000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 11869364000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 12022608000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1025440 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1025440 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 172302 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 172302 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2947 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108226 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 111173 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 120031 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 120031 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2947 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 228257 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 231204 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2947 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 228257 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 231204 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4329040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4446920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4801240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4801240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 9248160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -136,20 +136,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -442,20 +435,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=20
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -494,20 +480,13 @@ is_top_level=false
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -531,14 +510,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 9 2012 12:45:55
|
||||
gem5 started Feb 9 2012 12:46:40
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:22:59
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.488026 # Nu
|
|||
sim_ticks 488026375000 # Number of ticks simulated
|
||||
final_tick 488026375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 87795 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 28022613 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289796 # Number of bytes of host memory used
|
||||
host_seconds 17415.45 # Real time elapsed on the host
|
||||
sim_insts 1528988756 # Number of instructions simulated
|
||||
host_inst_rate 101458 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 187607 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 59880945 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 257144 # Number of bytes of host memory used
|
||||
host_seconds 8149.94 # Real time elapsed on the host
|
||||
sim_insts 826877144 # Number of instructions simulated
|
||||
sim_ops 1528988756 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 37539712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 347136 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 26338560 # Number of bytes written to this memory
|
||||
|
|
@ -238,7 +240,8 @@ system.cpu.iew.wb_penalized 0 # nu
|
|||
system.cpu.iew.wb_rate 1.917211 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.675773 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions
|
||||
system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 745779287 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 16577287 # The number of times a branch was mispredicted
|
||||
|
|
@ -259,7 +262,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
|
|||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 856525585 # Number of insts commited each cycle
|
||||
system.cpu.commit.count 1528988756 # Number of instructions committed
|
||||
system.cpu.commit.committedInsts 826877144 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 533262345 # Number of memory references committed
|
||||
system.cpu.commit.loads 384102160 # Number of loads committed
|
||||
|
|
@ -274,12 +278,13 @@ system.cpu.rob.rob_reads 3076935822 # Th
|
|||
system.cpu.rob.rob_writes 4651204201 # The number of ROB writes
|
||||
system.cpu.timesIdled 418807 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 18030123 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.638365 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.638365 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.566502 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.566502 # IPC: Total IPC of All Threads
|
||||
system.cpu.committedInsts 826877144 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.180408 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.180408 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.847164 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.847164 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 3175693593 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1742205758 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 120 # number of floating regfile reads
|
||||
|
|
@ -290,26 +295,39 @@ system.cpu.icache.total_refs 193659156 # To
|
|||
system.cpu.icache.sampled_refs 11601 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 16693.315749 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 973.820201 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.475498 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 193665655 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 193665655 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 193665655 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 234749 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 234749 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 234749 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 1699920500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1699920500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1699920500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 193900404 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 193900404 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 193900404 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.001211 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.001211 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.001211 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 7241.438728 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 7241.438728 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 7241.438728 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 973.820201 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.475498 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.475498 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 193665655 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 193665655 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 193665655 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 193665655 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 193665655 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 193665655 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 234749 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 234749 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 234749 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 234749 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 234749 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 234749 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1699920500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1699920500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1699920500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1699920500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1699920500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1699920500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 193900404 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 193900404 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 193900404 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 193900404 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 193900404 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 193900404 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001211 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001211 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001211 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7241.438728 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -318,27 +336,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 4 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 2040 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 2040 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 2040 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 232709 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 232709 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 232709 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 952455000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 952455000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 952455000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.001200 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.001200 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.001200 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4092.901435 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 4092.901435 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 4092.901435 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.writebacks::writebacks 4 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 4 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2040 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 2040 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 2040 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 2040 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 2040 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 2040 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 232709 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 232709 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 232709 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 232709 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 232709 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 232709 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 952455000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 952455000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 952455000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 952455000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 952455000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 952455000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001200 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001200 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001200 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4092.901435 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4092.901435 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4092.901435 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2529316 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4087.520068 # Cycle average of tags in use
|
||||
|
|
@ -346,32 +369,49 @@ system.cpu.dcache.total_refs 427611101 # To
|
|||
system.cpu.dcache.sampled_refs 2533412 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 168.788614 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 2115074000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4087.520068 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.997930 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 278887188 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 148162157 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 427049345 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 427049345 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 2665882 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 998044 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 3663926 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 3663926 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 39487902000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 20586128000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 60074030000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 60074030000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 281553070 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 430713271 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 430713271 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.009468 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.006691 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.008507 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.008507 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14812.321776 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 20626.473382 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 16396.081689 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 16396.081689 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4087.520068 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997930 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 278887188 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 278887188 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148162157 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 148162157 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 427049345 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 427049345 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 427049345 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 427049345 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 2665882 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 2665882 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 998044 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 998044 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3663926 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3663926 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3663926 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3663926 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39487902000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 39487902000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20586128000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20586128000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 60074030000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 60074030000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 60074030000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 60074030000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 281553070 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 281553070 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 430713271 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 430713271 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 430713271 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 430713271 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009468 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006691 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.008507 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.008507 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14812.321776 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20626.473382 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16396.081689 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16396.081689 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -380,32 +420,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 2229932 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 902993 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 909446 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 909446 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1762889 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 991591 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2754480 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2754480 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 14966916500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 17535799000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 32502715500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 32502715500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.006261 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006648 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006395 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006395 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8489.993698 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17684.508028 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 11799.946088 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 11799.946088 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 2229932 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2229932 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 902993 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 902993 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6453 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6453 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 909446 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 909446 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 909446 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 909446 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762889 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1762889 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 991591 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 991591 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2754480 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2754480 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2754480 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2754480 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14966916500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 14966916500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17535799000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17535799000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32502715500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 32502715500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32502715500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 32502715500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006261 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006648 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006395 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006395 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8489.993698 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17684.508028 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11799.946088 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11799.946088 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 575774 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21621.732877 # Cycle average of tags in use
|
||||
|
|
@ -413,42 +461,85 @@ system.cpu.l2cache.total_refs 3195554 # To
|
|||
system.cpu.l2cache.sampled_refs 594946 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.371166 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 268816776000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 7838.250700 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13783.482177 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.239204 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.420638 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1434280 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 2229936 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits 1289 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits 524029 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 1958309 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 1958309 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 339456 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses 219771 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 247125 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 586581 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 586581 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 11594725000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 9650000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 8467808500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 20062533500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 20062533500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 1773736 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 2229936 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses 221060 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 771154 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 2544890 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 2544890 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.191379 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.994169 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.320461 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.230494 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.230494 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34156.783206 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 43.909342 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34265.284775 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34202.494626 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34202.494626 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 13783.482177 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 57.596580 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 7780.654120 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.420638 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001758 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.237447 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.659843 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 6132 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1428148 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1434280 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2229936 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2229936 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1289 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 1289 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 524029 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 524029 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 6132 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1952177 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1958309 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 6132 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1952177 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1958309 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 5424 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 334032 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 339456 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 219771 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 219771 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 247125 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 247125 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 5424 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 581157 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 586581 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 5424 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 581157 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 586581 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 185788500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11408936500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 11594725000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9650000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 9650000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8467808500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 8467808500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 185788500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 19876745000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20062533500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 185788500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 19876745000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20062533500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11556 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1762180 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1773736 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2229936 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2229936 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 221060 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 221060 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 771154 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 771154 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 11556 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2533334 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2544890 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 11556 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2533334 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2544890 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.469367 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189556 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994169 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320461 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.469367 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229404 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.469367 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229404 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34253.042035 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34155.220159 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 43.909342 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34265.284775 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34253.042035 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34202.022861 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.042035 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34202.022861 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -457,34 +548,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 411540 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 339456 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 219771 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 247125 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 586581 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 586581 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 10530013500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6813351000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7661828500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 18191842000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 18191842000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191379 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994169 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320461 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.230494 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.230494 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.260358 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.047586 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31003.858371 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.350245 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.350245 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 411540 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 411540 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5424 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 334032 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 339456 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 219771 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 219771 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247125 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 247125 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 5424 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 581157 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 586581 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5424 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 581157 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 586581 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168319500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10361694000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10530013500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6813351000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6813351000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7661828500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7661828500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168319500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18023522500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18191842000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168319500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18023522500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18191842000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189556 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994169 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320461 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229404 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229404 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31032.356195 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.063946 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31002.047586 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31003.858371 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31032.356195 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.172860 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31032.356195 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.172860 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -52,11 +62,34 @@ icache_port=system.membus.port[2]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.port[5]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[7]
|
||||
pio=system.membus.port[6]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.port[4]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -64,7 +97,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
|
||||
cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -88,7 +121,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:59:28
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:26:26
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 0.885229 # Nu
|
|||
sim_ticks 885229360000 # Number of ticks simulated
|
||||
final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2258239 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1307438877 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 208528 # Number of bytes of host memory used
|
||||
host_seconds 677.07 # Real time elapsed on the host
|
||||
sim_insts 1528988757 # Number of instructions simulated
|
||||
host_inst_rate 1663979 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3076883 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1781404357 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214024 # Number of bytes of host memory used
|
||||
host_seconds 496.93 # Real time elapsed on the host
|
||||
sim_insts 826877145 # Number of instructions simulated
|
||||
sim_ops 1528988757 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 10832432532 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 8546776872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 991849460 # Number of bytes written to this memory
|
||||
|
|
@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 551 # Nu
|
|||
system.cpu.numCycles 1770458721 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 1528988757 # Number of instructions executed
|
||||
system.cpu.committedInsts 826877145 # Number of instructions committed
|
||||
system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,16 +30,18 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
|
|
@ -40,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -58,20 +68,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -94,20 +104,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -115,9 +118,25 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
int_latency=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[4]
|
||||
pio=system.membus.port[3]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
|
|
@ -130,25 +149,18 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.port[4]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
|
|
@ -159,7 +171,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -167,7 +179,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
|
||||
cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -191,7 +203,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 07:10:56
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:34:54
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,13 @@ sim_seconds 1.658730 # Nu
|
|||
sim_ticks 1658729604000 # Number of ticks simulated
|
||||
final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1326745 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1439324936 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 217512 # Number of bytes of host memory used
|
||||
host_seconds 1152.44 # Real time elapsed on the host
|
||||
sim_insts 1528988757 # Number of instructions simulated
|
||||
host_inst_rate 1021382 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1888649 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2048908881 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222932 # Number of bytes of host memory used
|
||||
host_seconds 809.57 # Real time elapsed on the host
|
||||
sim_insts 826877145 # Number of instructions simulated
|
||||
sim_ops 1528988757 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 37094976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 148544 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 26349376 # Number of bytes written to this memory
|
||||
|
|
@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 551 # Nu
|
|||
system.cpu.numCycles 3317459208 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 1528988757 # Number of instructions executed
|
||||
system.cpu.committedInsts 826877145 # Number of instructions committed
|
||||
system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
|
|
@ -47,26 +50,39 @@ system.cpu.icache.total_refs 1068344296 # To
|
|||
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 1068344296 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 2814 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::cpu.inst 882.231489 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.430777 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.430777 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1068344296 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1068344296 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1068344296 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 2814 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 136878000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 136878000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 136878000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 136878000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 136878000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 136878000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 128436000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 128436000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 128436000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128436000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 128436000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128436000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 128436000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use
|
||||
|
|
@ -102,32 +116,49 @@ system.cpu.dcache.total_refs 530743932 # To
|
|||
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 148369157 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 530743932 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 2518458 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 21492013500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005303 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4086.472055 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997674 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997674 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 530743932 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 530743932 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 530743932 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 530743932 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 38012508000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 38012508000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21492013500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21492013500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 59504521500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 59504521500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 59504521500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 59504521500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 2223170 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 51949140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 51949140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005303 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.writebacks::writebacks 2223170 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2223170 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32830264000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 32830264000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19118876000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19118876000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51949140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 568906 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use
|
||||
|
|
@ -167,36 +200,75 @@ system.cpu.l2cache.total_refs 3146531 # To
|
|||
system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1398652 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 2223170 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 543011 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 1941663 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 1941663 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 331576 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 248033 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 579609 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 17241952000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 2223170 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency
|
||||
system.cpu.l2cache.occ_blocks::writebacks 13679.064710 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 30.006309 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 7519.122292 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.417452 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000916 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.229465 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.647833 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 493 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1398159 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1398652 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2223170 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2223170 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 543011 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 543011 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 493 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1941170 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1941663 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 493 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1941170 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1941663 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2321 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 329255 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 331576 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 248033 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 248033 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2321 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 577288 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 579609 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2321 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 577288 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 579609 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120692000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17121260000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 17241952000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12897722000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 12897722000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 120692000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 30018982000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30139674000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 120692000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 30018982000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30139674000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2223170 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2223170 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -205,30 +277,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 411709 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 23184360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.229888 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.writebacks::writebacks 411709 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 411709 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2321 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 329255 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 331576 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 248033 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 248033 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2321 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 577288 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 579609 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2321 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 577288 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 579609 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92840000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13170200000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13263040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9921320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9921320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23091520000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23184360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -23,7 +30,7 @@ system_port=system.membus.port[0]
|
|||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
|
|
@ -45,6 +52,7 @@ div32RepeatRate=1
|
|||
div8Latency=1
|
||||
div8RepeatRate=1
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchBuffSize=4
|
||||
|
|
@ -57,6 +65,7 @@ globalCtrBits=2
|
|||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
instShiftAmt=2
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
|
|
@ -72,6 +81,7 @@ multRepeatRate=1
|
|||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
profile=0
|
||||
progress_interval=0
|
||||
stageTracing=false
|
||||
stageWidth=4
|
||||
|
|
@ -93,20 +103,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -129,20 +132,13 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -150,6 +146,9 @@ write_buffers=8
|
|||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -165,20 +164,13 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
|
|
@ -202,7 +194,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
|
||||
cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue