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use the dedicated flag, no more exposing the m5reg directly

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dev/ns_gige.cc:
    stop exposing the m5reg to the configuration stuff and build it
    based on exposed flags.  Expose dedicated now.
dev/ns_gige.hh:
    goodbye m5reg hello dedicated
dev/ns_gige_reg.h:
    Flags for the M5REG

--HG--
extra : convert_revision : 11134fe67cdf5291caacf9b3041739c437b983e3
This commit is contained in:
Nathan Binkert 2005-10-18 21:01:05 -04:00
parent e999645caf
commit 4f43bc65ea
4 changed files with 12 additions and 6 deletions
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10
dev/ns_gige.cc
View file

@ -771,7 +771,9 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
break; break;
case M5REG: case M5REG:
reg = params()->m5reg; reg = 0;
if (params()->dedicated)
reg |= M5REG_DEDICATED;
break; break;
default: default:
@ -3009,7 +3011,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
Param<uint32_t> pci_func; Param<uint32_t> pci_func;
Param<uint32_t> tx_fifo_size; Param<uint32_t> tx_fifo_size;
Param<uint32_t> rx_fifo_size; Param<uint32_t> rx_fifo_size;
Param<uint32_t> m5reg; Param<bool> dedicated;
Param<bool> dma_no_allocate; Param<bool> dma_no_allocate;
END_DECLARE_SIM_OBJECT_PARAMS(NSGigE) END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
@ -3043,7 +3045,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(pci_func, "PCI function code"), INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(tx_fifo_size, "max size in bytes of txFifo", 131072), INIT_PARAM_DFLT(tx_fifo_size, "max size in bytes of txFifo", 131072),
INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072), INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072),
INIT_PARAM(m5reg, "m5 register"), INIT_PARAM(dedicated, "dedicate a kernel thread to the driver"),
INIT_PARAM_DFLT(dma_no_allocate, "Should DMA reads allocate cache lines", true) INIT_PARAM_DFLT(dma_no_allocate, "Should DMA reads allocate cache lines", true)
END_INIT_SIM_OBJECT_PARAMS(NSGigE) END_INIT_SIM_OBJECT_PARAMS(NSGigE)
@ -3081,7 +3083,7 @@ CREATE_SIM_OBJECT(NSGigE)
params->eaddr = hardware_address; params->eaddr = hardware_address;
params->tx_fifo_size = tx_fifo_size; params->tx_fifo_size = tx_fifo_size;
params->rx_fifo_size = rx_fifo_size; params->rx_fifo_size = rx_fifo_size;
params->m5reg = m5reg; params->dedicated = dedicated;
params->dma_no_allocate = dma_no_allocate; params->dma_no_allocate = dma_no_allocate;
return new NSGigE(params); return new NSGigE(params);
} }

2
dev/ns_gige.hh
View file

@ -385,7 +385,7 @@ class NSGigE : public PciDev
Net::EthAddr eaddr; Net::EthAddr eaddr;
uint32_t tx_fifo_size; uint32_t tx_fifo_size;
uint32_t rx_fifo_size; uint32_t rx_fifo_size;
uint32_t m5reg; bool dedicated;
bool dma_no_allocate; bool dma_no_allocate;
}; };

4
dev/ns_gige_reg.h
View file

@ -304,6 +304,10 @@
#define TANAR_FULL_DUP 0x00000020 #define TANAR_FULL_DUP 0x00000020
#define TANAR_UNUSED 0x00000E1F #define TANAR_UNUSED 0x00000E1F
/* M5 control register */
#define M5REG_RESERVED 0xfffffffe
#define M5REG_DEDICATED 0x00000001
struct ns_desc32 { struct ns_desc32 {
uint32_t link; /* link field to next descriptor in linked list */ uint32_t link; /* link field to next descriptor in linked list */
uint32_t bufptr; /* pointer to the first fragment or buffer */ uint32_t bufptr; /* pointer to the first fragment or buffer */

2
python/m5/objects/Ethernet.py
View file

@ -83,7 +83,7 @@ class NSGigE(PciDevice):
rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo") rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo")
tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo") tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo")
m5reg = Param.UInt32(0, "Register for m5 usage") dedicated = Param.Bool(False, "dedicated kernel thread for driver")
intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds") intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")