Ozone updates.
cpu/ozone/front_end.hh: cpu/ozone/front_end_impl.hh: cpu/ozone/lw_back_end.hh: Support latency for Ozone FE and BE. cpu/ozone/lw_back_end_impl.hh: Support latency for Ozone FE and BE. Also fixes for switching out, profiling. cpu/ozone/lw_lsq.hh: cpu/ozone/lw_lsq_impl.hh: Fixes for switching out. cpu/ozone/simple_params.hh: Updated parameters. --HG-- extra : convert_revision : 21d4846a59a2239bfdf8fe92e47fd0972debe4f5
This commit is contained in:
parent
ad2fa1e1c9
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7 changed files with 236 additions and 67 deletions
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@ -31,6 +31,7 @@
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#include <deque>
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#include <deque>
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#include "base/timebuf.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/bpred_unit.hh"
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#include "cpu/o3/bpred_unit.hh"
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#include "cpu/ozone/rename_table.hh"
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#include "cpu/ozone/rename_table.hh"
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@ -210,15 +211,21 @@ class FrontEnd
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void dumpInsts();
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void dumpInsts();
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private:
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private:
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TimeBuffer<int> numInstsReady;
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typedef typename std::deque<DynInstPtr> InstBuff;
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typedef typename std::deque<DynInstPtr> InstBuff;
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typedef typename InstBuff::iterator InstBuffIt;
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typedef typename InstBuff::iterator InstBuffIt;
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InstBuff feBuffer;
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InstBuff instBuffer;
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InstBuff instBuffer;
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int instBufferSize;
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int instBufferSize;
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int maxInstBufferSize;
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int maxInstBufferSize;
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int latency;
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int width;
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int width;
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int freeRegs;
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int freeRegs;
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@ -41,8 +41,10 @@ template <class Impl>
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FrontEnd<Impl>::FrontEnd(Params *params)
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FrontEnd<Impl>::FrontEnd(Params *params)
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: branchPred(params),
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: branchPred(params),
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icacheInterface(params->icacheInterface),
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icacheInterface(params->icacheInterface),
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numInstsReady(params->frontEndLatency, 0),
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instBufferSize(0),
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instBufferSize(0),
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maxInstBufferSize(params->maxInstBufferSize),
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maxInstBufferSize(params->maxInstBufferSize),
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latency(params->frontEndLatency),
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width(params->frontEndWidth),
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width(params->frontEndWidth),
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freeRegs(params->numPhysicalRegs),
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freeRegs(params->numPhysicalRegs),
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numPhysRegs(params->numPhysicalRegs),
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numPhysRegs(params->numPhysicalRegs),
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@ -261,6 +263,18 @@ FrontEnd<Impl>::tick()
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if (switchedOut)
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if (switchedOut)
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return;
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return;
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for (int insts_to_queue = numInstsReady[-latency];
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!instBuffer.empty() && insts_to_queue;
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--insts_to_queue)
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{
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DPRINTF(FE, "Transferring instruction [sn:%lli] to the feBuffer\n",
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instBuffer.front()->seqNum);
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feBuffer.push_back(instBuffer.front());
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instBuffer.pop_front();
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}
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numInstsReady.advance();
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// @todo: Maybe I want to just have direct communication...
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// @todo: Maybe I want to just have direct communication...
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if (fromCommit->doneSeqNum) {
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if (fromCommit->doneSeqNum) {
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branchPred.update(fromCommit->doneSeqNum, 0);
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branchPred.update(fromCommit->doneSeqNum, 0);
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@ -349,6 +363,7 @@ FrontEnd<Impl>::tick()
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// latency
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// latency
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instBuffer.push_back(inst);
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instBuffer.push_back(inst);
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++instBufferSize;
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++instBufferSize;
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numInstsReady[0]++;
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++num_inst;
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++num_inst;
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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@ -570,6 +585,7 @@ FrontEnd<Impl>::handleFault(Fault &fault)
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instruction->fault = fault;
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instruction->fault = fault;
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instruction->setCanIssue();
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instruction->setCanIssue();
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instBuffer.push_back(instruction);
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instBuffer.push_back(instruction);
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numInstsReady[0]++;
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++instBufferSize;
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++instBufferSize;
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}
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}
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@ -599,6 +615,21 @@ FrontEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC,
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freeRegs+= inst->numDestRegs();
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freeRegs+= inst->numDestRegs();
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}
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}
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while (!feBuffer.empty() &&
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feBuffer.back()->seqNum > squash_num) {
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DynInstPtr inst = feBuffer.back();
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DPRINTF(FE, "Squashing instruction [sn:%lli] PC %#x\n",
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inst->seqNum, inst->readPC());
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inst->clearDependents();
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feBuffer.pop_back();
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--instBufferSize;
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freeRegs+= inst->numDestRegs();
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}
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// Copy over rename table from the back end.
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// Copy over rename table from the back end.
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renameTable.copyFrom(backEnd->renameTable);
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renameTable.copyFrom(backEnd->renameTable);
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@ -633,13 +664,13 @@ template <class Impl>
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typename Impl::DynInstPtr
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typename Impl::DynInstPtr
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FrontEnd<Impl>::getInst()
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FrontEnd<Impl>::getInst()
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{
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{
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if (instBufferSize == 0) {
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if (feBuffer.empty()) {
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return NULL;
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return NULL;
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}
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}
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DynInstPtr inst = instBuffer.front();
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DynInstPtr inst = feBuffer.front();
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instBuffer.pop_front();
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feBuffer.pop_front();
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--instBufferSize;
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--instBufferSize;
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@ -857,6 +888,7 @@ FrontEnd<Impl>::doSwitchOut()
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squash(0, 0);
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squash(0, 0);
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instBuffer.clear();
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instBuffer.clear();
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instBufferSize = 0;
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instBufferSize = 0;
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feBuffer.clear();
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status = Idle;
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status = Idle;
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}
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}
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@ -78,7 +78,7 @@ class LWBackEnd
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TimeBuffer<IssueToExec> i2e;
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TimeBuffer<IssueToExec> i2e;
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typename TimeBuffer<IssueToExec>::wire instsToExecute;
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typename TimeBuffer<IssueToExec>::wire instsToExecute;
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TimeBuffer<ExecToCommit> e2c;
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TimeBuffer<ExecToCommit> e2c;
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TimeBuffer<Writeback> numInstsToWB;
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TimeBuffer<int> numInstsToWB;
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TimeBuffer<CommStruct> *comm;
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TimeBuffer<CommStruct> *comm;
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typename TimeBuffer<CommStruct>::wire toIEW;
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typename TimeBuffer<CommStruct>::wire toIEW;
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@ -157,7 +157,7 @@ class LWBackEnd
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Tick lastCommitCycle;
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Tick lastCommitCycle;
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bool robEmpty() { return instList.empty(); }
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bool robEmpty() { return numInsts == 0; }
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bool isFull() { return numInsts >= numROBEntries; }
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bool isFull() { return numInsts >= numROBEntries; }
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bool isBlocked() { return status == Blocked || dispatchStatus == Blocked; }
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bool isBlocked() { return status == Blocked || dispatchStatus == Blocked; }
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@ -212,6 +212,7 @@ class LWBackEnd
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}
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}
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void instToCommit(DynInstPtr &inst);
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void instToCommit(DynInstPtr &inst);
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void readyInstsForCommit();
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void switchOut();
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void switchOut();
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void doSwitchOut();
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void doSwitchOut();
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@ -293,12 +294,13 @@ class LWBackEnd
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MemReqPtr memReq;
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MemReqPtr memReq;
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int latency;
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// General back end width. Used if the more specific isn't given.
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// General back end width. Used if the more specific isn't given.
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int width;
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int width;
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// Dispatch width.
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// Dispatch width.
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int dispatchWidth;
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int dispatchWidth;
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int numDispatchEntries;
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int dispatchSize;
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int dispatchSize;
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int waitingInsts;
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int waitingInsts;
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@ -323,6 +325,7 @@ class LWBackEnd
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int numROBEntries;
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int numROBEntries;
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int numInsts;
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int numInsts;
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bool lsqLimits;
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std::set<InstSeqNum> waitingMemOps;
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std::set<InstSeqNum> waitingMemOps;
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typedef std::set<InstSeqNum>::iterator MemIt;
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typedef std::set<InstSeqNum>::iterator MemIt;
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@ -333,9 +336,6 @@ class LWBackEnd
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InstSeqNum squashSeqNum;
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InstSeqNum squashSeqNum;
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Addr squashNextPC;
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Addr squashNextPC;
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Fault faultFromFetch;
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bool fetchHasFault;
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bool switchedOut;
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bool switchedOut;
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bool switchPending;
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bool switchPending;
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@ -359,8 +359,6 @@ class LWBackEnd
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std::list<DynInstPtr> replayList;
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std::list<DynInstPtr> replayList;
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std::list<DynInstPtr> writeback;
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std::list<DynInstPtr> writeback;
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int latency;
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int squashLatency;
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int squashLatency;
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bool exactFullStall;
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bool exactFullStall;
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@ -397,9 +395,11 @@ class LWBackEnd
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Stats::Scalar<> lsqInversion;
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Stats::Scalar<> lsqInversion;
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Stats::Vector<> nIssuedDist;
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Stats::Vector<> nIssuedDist;
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/*
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Stats::VectorDistribution<> issueDelayDist;
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Stats::VectorDistribution<> issueDelayDist;
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Stats::VectorDistribution<> queueResDist;
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Stats::VectorDistribution<> queueResDist;
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*/
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/*
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/*
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Stats::Vector<> stat_fu_busy;
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Stats::Vector<> stat_fu_busy;
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Stats::Vector2d<> stat_fuBusy;
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Stats::Vector2d<> stat_fuBusy;
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@ -447,7 +447,7 @@ class LWBackEnd
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Stats::Vector<> ROBCount; // cumulative ROB occupancy
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Stats::Vector<> ROBCount; // cumulative ROB occupancy
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Stats::Formula ROBOccRate;
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Stats::Formula ROBOccRate;
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Stats::VectorDistribution<> ROBOccDist;
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// Stats::VectorDistribution<> ROBOccDist;
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public:
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public:
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void dumpInsts();
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void dumpInsts();
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@ -151,8 +151,10 @@ LWBackEnd<Impl>::LdWritebackEvent::process()
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// iewStage->wakeCPU();
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// iewStage->wakeCPU();
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if (be->isSwitchedOut())
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assert(inst->isSquashed() || !be->isSwitchedOut());
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return;
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// if (be->isSwitchedOut() && inst->isLoad())
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// return;
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if (dcacheMiss) {
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if (dcacheMiss) {
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be->removeDcacheMiss(inst);
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be->removeDcacheMiss(inst);
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@ -208,14 +210,14 @@ LWBackEnd<Impl>::DCacheCompletionEvent::description()
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template <class Impl>
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template <class Impl>
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LWBackEnd<Impl>::LWBackEnd(Params *params)
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LWBackEnd<Impl>::LWBackEnd(Params *params)
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: d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(5, 5),
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: d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(params->backEndLatency, 0),
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trapSquash(false), xcSquash(false), cacheCompletionEvent(this),
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trapSquash(false), xcSquash(false), cacheCompletionEvent(this),
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dcacheInterface(params->dcacheInterface), width(params->backEndWidth),
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dcacheInterface(params->dcacheInterface), latency(params->backEndLatency),
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width(params->backEndWidth), lsqLimits(params->lsqLimits),
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exactFullStall(true)
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exactFullStall(true)
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{
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{
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numROBEntries = params->numROBEntries;
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numROBEntries = params->numROBEntries;
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numInsts = 0;
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numInsts = 0;
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numDispatchEntries = 32;
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maxOutstandingMemOps = params->maxOutstandingMemOps;
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maxOutstandingMemOps = params->maxOutstandingMemOps;
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numWaitingMemOps = 0;
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numWaitingMemOps = 0;
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waitingInsts = 0;
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waitingInsts = 0;
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@ -251,6 +253,8 @@ void
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LWBackEnd<Impl>::regStats()
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LWBackEnd<Impl>::regStats()
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{
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{
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using namespace Stats;
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using namespace Stats;
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LSQ.regStats();
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robCapEvents
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robCapEvents
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.init(cpu->number_of_threads)
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.init(cpu->number_of_threads)
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.name(name() + ".ROB:cap_events")
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.name(name() + ".ROB:cap_events")
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@ -377,6 +381,7 @@ LWBackEnd<Impl>::regStats()
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.desc("Number of insts issued each cycle")
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.desc("Number of insts issued each cycle")
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.flags(total | pdf | dist)
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.flags(total | pdf | dist)
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;
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;
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/*
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issueDelayDist
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issueDelayDist
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.init(Num_OpClasses,0,99,2)
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.init(Num_OpClasses,0,99,2)
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.name(name() + ".ISSUE:")
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.name(name() + ".ISSUE:")
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@ -393,7 +398,7 @@ LWBackEnd<Impl>::regStats()
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for (int i = 0; i < Num_OpClasses; ++i) {
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for (int i = 0; i < Num_OpClasses; ++i) {
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queueResDist.subname(i, opClassStrings[i]);
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queueResDist.subname(i, opClassStrings[i]);
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}
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}
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*/
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writebackCount
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writebackCount
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.init(cpu->number_of_threads)
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.init(cpu->number_of_threads)
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.name(name() + ".WB:count")
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.name(name() + ".WB:count")
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@ -555,13 +560,14 @@ LWBackEnd<Impl>::regStats()
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.flags(total)
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.flags(total)
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;
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;
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ROBOccRate = ROBCount / cpu->numCycles;
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ROBOccRate = ROBCount / cpu->numCycles;
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/*
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ROBOccDist
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ROBOccDist
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.init(cpu->number_of_threads,0,numROBEntries,2)
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.init(cpu->number_of_threads,0,numROBEntries,2)
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.name(name() + ".ROB:occ_dist")
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.name(name() + ".ROB:occ_dist")
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.desc("ROB Occupancy per cycle")
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.desc("ROB Occupancy per cycle")
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.flags(total | cdf)
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.flags(total | cdf)
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;
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;
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*/
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}
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}
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template <class Impl>
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template <class Impl>
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@ -654,18 +660,22 @@ LWBackEnd<Impl>::tick()
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{
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{
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DPRINTF(BE, "Ticking back end\n");
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DPRINTF(BE, "Ticking back end\n");
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// Read in any done instruction information and update the IQ or LSQ.
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updateStructures();
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if (switchPending && robEmpty() && !LSQ.hasStoresToWB()) {
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if (switchPending && robEmpty() && !LSQ.hasStoresToWB()) {
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cpu->signalSwitched();
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cpu->signalSwitched();
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return;
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return;
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}
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}
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readyInstsForCommit();
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numInstsToWB.advance();
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ROBCount[0]+= numInsts;
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ROBCount[0]+= numInsts;
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wbCycle = 0;
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wbCycle = 0;
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// Read in any done instruction information and update the IQ or LSQ.
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updateStructures();
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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checkInterrupts();
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checkInterrupts();
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@ -740,6 +750,10 @@ LWBackEnd<Impl>::dispatchInsts()
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while (numInsts < numROBEntries &&
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while (numInsts < numROBEntries &&
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numWaitingMemOps < maxOutstandingMemOps) {
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numWaitingMemOps < maxOutstandingMemOps) {
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// Get instruction from front of time buffer
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// Get instruction from front of time buffer
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if (lsqLimits && LSQ.isFull()) {
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break;
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}
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DynInstPtr inst = frontEnd->getInst();
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DynInstPtr inst = frontEnd->getInst();
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if (!inst) {
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if (!inst) {
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break;
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break;
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@ -798,6 +812,7 @@ LWBackEnd<Impl>::dispatchInsts()
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inst->setIssued();
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inst->setIssued();
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inst->setExecuted();
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inst->setExecuted();
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inst->setCanCommit();
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inst->setCanCommit();
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numInstsToWB[0]++;
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} else {
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} else {
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DPRINTF(BE, "Instruction [sn:%lli] ready, addding to "
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DPRINTF(BE, "Instruction [sn:%lli] ready, addding to "
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||||||
"exeList.\n",
|
"exeList.\n",
|
||||||
|
@ -987,16 +1002,10 @@ template<class Impl>
|
||||||
void
|
void
|
||||||
LWBackEnd<Impl>::instToCommit(DynInstPtr &inst)
|
LWBackEnd<Impl>::instToCommit(DynInstPtr &inst)
|
||||||
{
|
{
|
||||||
|
|
||||||
DPRINTF(BE, "Sending instructions to commit [sn:%lli] PC %#x.\n",
|
DPRINTF(BE, "Sending instructions to commit [sn:%lli] PC %#x.\n",
|
||||||
inst->seqNum, inst->readPC());
|
inst->seqNum, inst->readPC());
|
||||||
|
|
||||||
if (!inst->isSquashed()) {
|
if (!inst->isSquashed()) {
|
||||||
DPRINTF(BE, "Writing back instruction [sn:%lli] PC %#x.\n",
|
|
||||||
inst->seqNum, inst->readPC());
|
|
||||||
|
|
||||||
inst->setCanCommit();
|
|
||||||
|
|
||||||
if (inst->isExecuted()) {
|
if (inst->isExecuted()) {
|
||||||
inst->setResultReady();
|
inst->setResultReady();
|
||||||
int dependents = wakeDependents(inst);
|
int dependents = wakeDependents(inst);
|
||||||
|
@ -1007,8 +1016,32 @@ LWBackEnd<Impl>::instToCommit(DynInstPtr &inst)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
writeback.push_back(inst);
|
||||||
|
|
||||||
|
numInstsToWB[0]++;
|
||||||
|
|
||||||
writebackCount[0]++;
|
writebackCount[0]++;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
LWBackEnd<Impl>::readyInstsForCommit()
|
||||||
|
{
|
||||||
|
for (int i = numInstsToWB[-latency];
|
||||||
|
!writeback.empty() && i;
|
||||||
|
--i)
|
||||||
|
{
|
||||||
|
DynInstPtr inst = writeback.front();
|
||||||
|
writeback.pop_front();
|
||||||
|
if (!inst->isSquashed()) {
|
||||||
|
DPRINTF(BE, "Writing back instruction [sn:%lli] PC %#x.\n",
|
||||||
|
inst->seqNum, inst->readPC());
|
||||||
|
|
||||||
|
inst->setCanCommit();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
|
@ -1221,6 +1254,20 @@ LWBackEnd<Impl>::commitInst(int inst_num)
|
||||||
++freed_regs;
|
++freed_regs;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
if (thread->profile) {
|
||||||
|
// bool usermode =
|
||||||
|
// (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
|
||||||
|
// thread->profilePC = usermode ? 1 : inst->readPC();
|
||||||
|
thread->profilePC = inst->readPC();
|
||||||
|
ProfileNode *node = thread->profile->consume(thread->getXCProxy(),
|
||||||
|
inst->staticInst);
|
||||||
|
|
||||||
|
if (node)
|
||||||
|
thread->profileNode = node;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
if (inst->traceData) {
|
if (inst->traceData) {
|
||||||
inst->traceData->setFetchSeq(inst->seqNum);
|
inst->traceData->setFetchSeq(inst->seqNum);
|
||||||
inst->traceData->setCPSeq(thread->numInst);
|
inst->traceData->setCPSeq(thread->numInst);
|
||||||
|
@ -1280,9 +1327,9 @@ LWBackEnd<Impl>::commitInsts()
|
||||||
while (!instList.empty() && inst_num < commitWidth) {
|
while (!instList.empty() && inst_num < commitWidth) {
|
||||||
if (instList.back()->isSquashed()) {
|
if (instList.back()->isSquashed()) {
|
||||||
instList.back()->clearDependents();
|
instList.back()->clearDependents();
|
||||||
|
ROBSquashedInsts[instList.back()->threadNumber]++;
|
||||||
instList.pop_back();
|
instList.pop_back();
|
||||||
--numInsts;
|
--numInsts;
|
||||||
ROBSquashedInsts[instList.back()->threadNumber]++;
|
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1304,10 +1351,10 @@ LWBackEnd<Impl>::squash(const InstSeqNum &sn)
|
||||||
LSQ.squash(sn);
|
LSQ.squash(sn);
|
||||||
|
|
||||||
int freed_regs = 0;
|
int freed_regs = 0;
|
||||||
InstListIt waiting_list_end = waitingList.end();
|
InstListIt insts_end_it = waitingList.end();
|
||||||
InstListIt insts_it = waitingList.begin();
|
InstListIt insts_it = waitingList.begin();
|
||||||
|
|
||||||
while (insts_it != waiting_list_end && (*insts_it)->seqNum > sn)
|
while (insts_it != insts_end_it && (*insts_it)->seqNum > sn)
|
||||||
{
|
{
|
||||||
if ((*insts_it)->isSquashed()) {
|
if ((*insts_it)->isSquashed()) {
|
||||||
++insts_it;
|
++insts_it;
|
||||||
|
@ -1333,6 +1380,7 @@ LWBackEnd<Impl>::squash(const InstSeqNum &sn)
|
||||||
while (!instList.empty() && (*insts_it)->seqNum > sn)
|
while (!instList.empty() && (*insts_it)->seqNum > sn)
|
||||||
{
|
{
|
||||||
if ((*insts_it)->isSquashed()) {
|
if ((*insts_it)->isSquashed()) {
|
||||||
|
panic("Instruction should not be already squashed and on list!");
|
||||||
++insts_it;
|
++insts_it;
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
@ -1364,18 +1412,6 @@ LWBackEnd<Impl>::squash(const InstSeqNum &sn)
|
||||||
--numInsts;
|
--numInsts;
|
||||||
}
|
}
|
||||||
|
|
||||||
insts_it = waitingList.begin();
|
|
||||||
while (!waitingList.empty() && insts_it != waitingList.end()) {
|
|
||||||
if ((*insts_it)->seqNum < sn) {
|
|
||||||
++insts_it;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
assert((*insts_it)->isSquashed());
|
|
||||||
|
|
||||||
waitingList.erase(insts_it++);
|
|
||||||
waitingInsts--;
|
|
||||||
}
|
|
||||||
|
|
||||||
while (memBarrier && memBarrier->seqNum > sn) {
|
while (memBarrier && memBarrier->seqNum > sn) {
|
||||||
DPRINTF(BE, "[sn:%lli] Memory barrier squashed (or previously "
|
DPRINTF(BE, "[sn:%lli] Memory barrier squashed (or previously "
|
||||||
"squashed)\n", memBarrier->seqNum);
|
"squashed)\n", memBarrier->seqNum);
|
||||||
|
@ -1393,6 +1429,18 @@ LWBackEnd<Impl>::squash(const InstSeqNum &sn)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
insts_it = replayList.begin();
|
||||||
|
insts_end_it = replayList.end();
|
||||||
|
while (!replayList.empty() && insts_it != insts_end_it) {
|
||||||
|
if ((*insts_it)->seqNum < sn) {
|
||||||
|
++insts_it;
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
assert((*insts_it)->isSquashed());
|
||||||
|
|
||||||
|
replayList.erase(insts_it++);
|
||||||
|
}
|
||||||
|
|
||||||
frontEnd->addFreeRegs(freed_regs);
|
frontEnd->addFreeRegs(freed_regs);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1463,14 +1511,6 @@ LWBackEnd<Impl>::squashDueToMemBlocked(DynInstPtr &inst)
|
||||||
frontEnd->squash(inst->seqNum - 1, inst->readPC());
|
frontEnd->squash(inst->seqNum - 1, inst->readPC());
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
|
||||||
void
|
|
||||||
LWBackEnd<Impl>::fetchFault(Fault &fault)
|
|
||||||
{
|
|
||||||
faultFromFetch = fault;
|
|
||||||
fetchHasFault = true;
|
|
||||||
}
|
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
LWBackEnd<Impl>::switchOut()
|
LWBackEnd<Impl>::switchOut()
|
||||||
|
@ -1489,16 +1529,25 @@ LWBackEnd<Impl>::doSwitchOut()
|
||||||
// yet written back.
|
// yet written back.
|
||||||
assert(robEmpty());
|
assert(robEmpty());
|
||||||
assert(!LSQ.hasStoresToWB());
|
assert(!LSQ.hasStoresToWB());
|
||||||
|
writeback.clear();
|
||||||
|
for (int i = 0; i < numInstsToWB.getSize() + 1; ++i)
|
||||||
|
numInstsToWB.advance();
|
||||||
|
|
||||||
|
// squash(0);
|
||||||
|
assert(waitingList.empty());
|
||||||
|
assert(instList.empty());
|
||||||
|
assert(replayList.empty());
|
||||||
|
assert(writeback.empty());
|
||||||
LSQ.switchOut();
|
LSQ.switchOut();
|
||||||
|
|
||||||
squash(0);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
LWBackEnd<Impl>::takeOverFrom(ExecContext *old_xc)
|
LWBackEnd<Impl>::takeOverFrom(ExecContext *old_xc)
|
||||||
{
|
{
|
||||||
|
assert(!squashPending);
|
||||||
|
squashSeqNum = 0;
|
||||||
|
squashNextPC = 0;
|
||||||
xcSquash = false;
|
xcSquash = false;
|
||||||
trapSquash = false;
|
trapSquash = false;
|
||||||
|
|
||||||
|
@ -1641,6 +1690,45 @@ LWBackEnd<Impl>::dumpInsts()
|
||||||
++num;
|
++num;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
inst_list_it = --(writeback.end());
|
||||||
|
|
||||||
|
cprintf("Writeback list size: %i\n", writeback.size());
|
||||||
|
|
||||||
|
while (inst_list_it != writeback.end())
|
||||||
|
{
|
||||||
|
cprintf("Instruction:%i\n",
|
||||||
|
num);
|
||||||
|
if (!(*inst_list_it)->isSquashed()) {
|
||||||
|
if (!(*inst_list_it)->isIssued()) {
|
||||||
|
++valid_num;
|
||||||
|
cprintf("Count:%i\n", valid_num);
|
||||||
|
} else if ((*inst_list_it)->isMemRef() &&
|
||||||
|
!(*inst_list_it)->memOpDone) {
|
||||||
|
// Loads that have not been marked as executed still count
|
||||||
|
// towards the total instructions.
|
||||||
|
++valid_num;
|
||||||
|
cprintf("Count:%i\n", valid_num);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
|
||||||
|
"Issued:%i\nSquashed:%i\n",
|
||||||
|
(*inst_list_it)->readPC(),
|
||||||
|
(*inst_list_it)->seqNum,
|
||||||
|
(*inst_list_it)->threadNumber,
|
||||||
|
(*inst_list_it)->isIssued(),
|
||||||
|
(*inst_list_it)->isSquashed());
|
||||||
|
|
||||||
|
if ((*inst_list_it)->isMemRef()) {
|
||||||
|
cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
|
||||||
|
}
|
||||||
|
|
||||||
|
cprintf("\n");
|
||||||
|
|
||||||
|
inst_list_it--;
|
||||||
|
++num;
|
||||||
|
}
|
||||||
|
|
||||||
cprintf("Waiting list size: %i\n", waitingList.size());
|
cprintf("Waiting list size: %i\n", waitingList.size());
|
||||||
|
|
||||||
inst_list_it = --(waitingList.end());
|
inst_list_it = --(waitingList.end());
|
||||||
|
|
|
@ -110,6 +110,8 @@ class OzoneLWLSQ {
|
||||||
/** Returns the name of the LSQ unit. */
|
/** Returns the name of the LSQ unit. */
|
||||||
std::string name() const;
|
std::string name() const;
|
||||||
|
|
||||||
|
void regStats();
|
||||||
|
|
||||||
/** Sets the CPU pointer. */
|
/** Sets the CPU pointer. */
|
||||||
void setCPU(FullCPU *cpu_ptr)
|
void setCPU(FullCPU *cpu_ptr)
|
||||||
{ cpu = cpu_ptr; }
|
{ cpu = cpu_ptr; }
|
||||||
|
@ -203,7 +205,7 @@ class OzoneLWLSQ {
|
||||||
int numLoads() { return loads; }
|
int numLoads() { return loads; }
|
||||||
|
|
||||||
/** Returns the number of stores in the SQ. */
|
/** Returns the number of stores in the SQ. */
|
||||||
int numStores() { return stores; }
|
int numStores() { return stores + storesInFlight; }
|
||||||
|
|
||||||
/** Returns if either the LQ or SQ is full. */
|
/** Returns if either the LQ or SQ is full. */
|
||||||
bool isFull() { return lqFull() || sqFull(); }
|
bool isFull() { return lqFull() || sqFull(); }
|
||||||
|
@ -212,7 +214,7 @@ class OzoneLWLSQ {
|
||||||
bool lqFull() { return loads >= (LQEntries - 1); }
|
bool lqFull() { return loads >= (LQEntries - 1); }
|
||||||
|
|
||||||
/** Returns if the SQ is full. */
|
/** Returns if the SQ is full. */
|
||||||
bool sqFull() { return stores >= (SQEntries - 1); }
|
bool sqFull() { return (stores + storesInFlight) >= (SQEntries - 1); }
|
||||||
|
|
||||||
/** Debugging function to dump instructions in the LSQ. */
|
/** Debugging function to dump instructions in the LSQ. */
|
||||||
void dumpInsts();
|
void dumpInsts();
|
||||||
|
@ -241,7 +243,9 @@ class OzoneLWLSQ {
|
||||||
|
|
||||||
private:
|
private:
|
||||||
/** Completes the store at the specified index. */
|
/** Completes the store at the specified index. */
|
||||||
void completeStore(int store_idx);
|
void completeStore(DynInstPtr &inst);
|
||||||
|
|
||||||
|
void removeStore(int store_idx);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
/** Pointer to the CPU. */
|
/** Pointer to the CPU. */
|
||||||
|
@ -342,6 +346,10 @@ class OzoneLWLSQ {
|
||||||
|
|
||||||
int storesToWB;
|
int storesToWB;
|
||||||
|
|
||||||
|
public:
|
||||||
|
int storesInFlight;
|
||||||
|
|
||||||
|
private:
|
||||||
/// @todo Consider moving to a more advanced model with write vs read ports
|
/// @todo Consider moving to a more advanced model with write vs read ports
|
||||||
/** The number of cache ports available each cycle. */
|
/** The number of cache ports available each cycle. */
|
||||||
int cachePorts;
|
int cachePorts;
|
||||||
|
@ -351,6 +359,9 @@ class OzoneLWLSQ {
|
||||||
|
|
||||||
//list<InstSeqNum> mshrSeqNums;
|
//list<InstSeqNum> mshrSeqNums;
|
||||||
|
|
||||||
|
/** Tota number of memory ordering violations. */
|
||||||
|
Stats::Scalar<> lsqMemOrderViolation;
|
||||||
|
|
||||||
//Stats::Scalar<> dcacheStallCycles;
|
//Stats::Scalar<> dcacheStallCycles;
|
||||||
Counter lastDcacheStall;
|
Counter lastDcacheStall;
|
||||||
|
|
||||||
|
|
|
@ -57,6 +57,7 @@ OzoneLWLSQ<Impl>::StoreCompletionEvent::process()
|
||||||
|
|
||||||
// lsqPtr->cpu->wakeCPU();
|
// lsqPtr->cpu->wakeCPU();
|
||||||
if (lsqPtr->isSwitchedOut()) {
|
if (lsqPtr->isSwitchedOut()) {
|
||||||
|
panic("Should not be switched out!");
|
||||||
if (wbEvent)
|
if (wbEvent)
|
||||||
delete wbEvent;
|
delete wbEvent;
|
||||||
|
|
||||||
|
@ -68,7 +69,11 @@ OzoneLWLSQ<Impl>::StoreCompletionEvent::process()
|
||||||
delete wbEvent;
|
delete wbEvent;
|
||||||
}
|
}
|
||||||
|
|
||||||
lsqPtr->completeStore(inst->sqIdx);
|
lsqPtr->completeStore(inst);
|
||||||
|
lsqPtr->removeStore(inst->sqIdx);
|
||||||
|
--(lsqPtr->storesInFlight);
|
||||||
|
|
||||||
|
DPRINTF(OzoneLSQ, "StoresInFlight: %i\n", lsqPtr->storesInFlight);
|
||||||
if (miss)
|
if (miss)
|
||||||
be->removeDcacheMiss(inst);
|
be->removeDcacheMiss(inst);
|
||||||
}
|
}
|
||||||
|
@ -82,7 +87,7 @@ OzoneLWLSQ<Impl>::StoreCompletionEvent::description()
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
OzoneLWLSQ<Impl>::OzoneLWLSQ()
|
OzoneLWLSQ<Impl>::OzoneLWLSQ()
|
||||||
: loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
|
: loads(0), stores(0), storesToWB(0), storesInFlight(0), stalled(false), isLoadBlocked(false),
|
||||||
loadBlockedHandled(false)
|
loadBlockedHandled(false)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
@ -121,6 +126,15 @@ OzoneLWLSQ<Impl>::name() const
|
||||||
return "lsqunit";
|
return "lsqunit";
|
||||||
}
|
}
|
||||||
|
|
||||||
|
template<class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::regStats()
|
||||||
|
{
|
||||||
|
lsqMemOrderViolation
|
||||||
|
.name(name() + ".memOrderViolation")
|
||||||
|
.desc("Number of memory ordering violations");
|
||||||
|
}
|
||||||
|
|
||||||
template<class Impl>
|
template<class Impl>
|
||||||
void
|
void
|
||||||
OzoneLWLSQ<Impl>::clearLQ()
|
OzoneLWLSQ<Impl>::clearLQ()
|
||||||
|
@ -257,7 +271,7 @@ unsigned
|
||||||
OzoneLWLSQ<Impl>::numFreeEntries()
|
OzoneLWLSQ<Impl>::numFreeEntries()
|
||||||
{
|
{
|
||||||
unsigned free_lq_entries = LQEntries - loads;
|
unsigned free_lq_entries = LQEntries - loads;
|
||||||
unsigned free_sq_entries = SQEntries - stores;
|
unsigned free_sq_entries = SQEntries - (stores + storesInFlight);
|
||||||
|
|
||||||
// Both the LQ and SQ entries have an extra dummy entry to differentiate
|
// Both the LQ and SQ entries have an extra dummy entry to differentiate
|
||||||
// empty/full conditions. Subtract 1 from the free entries.
|
// empty/full conditions. Subtract 1 from the free entries.
|
||||||
|
@ -397,6 +411,7 @@ OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
|
||||||
// A load incorrectly passed this store. Squash and refetch.
|
// A load incorrectly passed this store. Squash and refetch.
|
||||||
// For now return a fault to show that it was unsuccessful.
|
// For now return a fault to show that it was unsuccessful.
|
||||||
memDepViolator = (*lq_it);
|
memDepViolator = (*lq_it);
|
||||||
|
++lsqMemOrderViolation;
|
||||||
|
|
||||||
return TheISA::genMachineCheckFault();
|
return TheISA::genMachineCheckFault();
|
||||||
}
|
}
|
||||||
|
@ -483,8 +498,8 @@ OzoneLWLSQ<Impl>::writebackStores()
|
||||||
|
|
||||||
if ((*sq_it).size == 0 && !(*sq_it).completed) {
|
if ((*sq_it).size == 0 && !(*sq_it).completed) {
|
||||||
sq_it--;
|
sq_it--;
|
||||||
completeStore(inst->sqIdx);
|
removeStore(inst->sqIdx);
|
||||||
|
completeStore(inst);
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -540,6 +555,8 @@ OzoneLWLSQ<Impl>::writebackStores()
|
||||||
inst->sqIdx,inst->readPC(),
|
inst->sqIdx,inst->readPC(),
|
||||||
req->paddr, *(req->data),
|
req->paddr, *(req->data),
|
||||||
inst->seqNum);
|
inst->seqNum);
|
||||||
|
DPRINTF(OzoneLSQ, "StoresInFlight: %i\n",
|
||||||
|
storesInFlight + 1);
|
||||||
|
|
||||||
if (dcacheInterface) {
|
if (dcacheInterface) {
|
||||||
assert(!req->completionEvent);
|
assert(!req->completionEvent);
|
||||||
|
@ -601,6 +618,8 @@ OzoneLWLSQ<Impl>::writebackStores()
|
||||||
}
|
}
|
||||||
sq_it--;
|
sq_it--;
|
||||||
}
|
}
|
||||||
|
++storesInFlight;
|
||||||
|
// removeStore(inst->sqIdx);
|
||||||
} else {
|
} else {
|
||||||
panic("Must HAVE DCACHE!!!!!\n");
|
panic("Must HAVE DCACHE!!!!!\n");
|
||||||
}
|
}
|
||||||
|
@ -617,7 +636,7 @@ void
|
||||||
OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
|
OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
|
||||||
{
|
{
|
||||||
DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
|
DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
|
||||||
"(Loads:%i Stores:%i)\n",squashed_num,loads,stores);
|
"(Loads:%i Stores:%i)\n",squashed_num,loads,stores+storesInFlight);
|
||||||
|
|
||||||
|
|
||||||
LQIt lq_it = loadQueue.begin();
|
LQIt lq_it = loadQueue.begin();
|
||||||
|
@ -732,7 +751,7 @@ OzoneLWLSQ<Impl>::dumpInsts()
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
OzoneLWLSQ<Impl>::completeStore(int store_idx)
|
OzoneLWLSQ<Impl>::removeStore(int store_idx)
|
||||||
{
|
{
|
||||||
SQHashIt sq_hash_it = SQItHash.find(store_idx);
|
SQHashIt sq_hash_it = SQItHash.find(store_idx);
|
||||||
assert(sq_hash_it != SQItHash.end());
|
assert(sq_hash_it != SQItHash.end());
|
||||||
|
@ -742,8 +761,6 @@ OzoneLWLSQ<Impl>::completeStore(int store_idx)
|
||||||
(*sq_it).completed = true;
|
(*sq_it).completed = true;
|
||||||
DynInstPtr inst = (*sq_it).inst;
|
DynInstPtr inst = (*sq_it).inst;
|
||||||
|
|
||||||
--storesToWB;
|
|
||||||
|
|
||||||
if (isStalled() &&
|
if (isStalled() &&
|
||||||
inst->seqNum == stallingStoreIsn) {
|
inst->seqNum == stallingStoreIsn) {
|
||||||
DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
|
DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
|
||||||
|
@ -761,6 +778,13 @@ OzoneLWLSQ<Impl>::completeStore(int store_idx)
|
||||||
SQItHash.erase(sq_hash_it);
|
SQItHash.erase(sq_hash_it);
|
||||||
SQIndices.push(inst->sqIdx);
|
SQIndices.push(inst->sqIdx);
|
||||||
storeQueue.erase(sq_it);
|
storeQueue.erase(sq_it);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
OzoneLWLSQ<Impl>::completeStore(DynInstPtr &inst)
|
||||||
|
{
|
||||||
|
--storesToWB;
|
||||||
--stores;
|
--stores;
|
||||||
|
|
||||||
inst->setCompleted();
|
inst->setCompleted();
|
||||||
|
@ -839,9 +863,14 @@ OzoneLWLSQ<Impl>::switchOut()
|
||||||
}
|
}
|
||||||
|
|
||||||
// Clear the queue to free up resources
|
// Clear the queue to free up resources
|
||||||
|
assert(stores == 0);
|
||||||
|
assert(storeQueue.empty());
|
||||||
|
assert(loads == 0);
|
||||||
|
assert(loadQueue.empty());
|
||||||
|
assert(storesInFlight == 0);
|
||||||
storeQueue.clear();
|
storeQueue.clear();
|
||||||
loadQueue.clear();
|
loadQueue.clear();
|
||||||
loads = stores = storesToWB = 0;
|
loads = stores = storesToWB = storesInFlight = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
|
|
|
@ -70,10 +70,11 @@ class SimpleParams : public BaseCPU::Params
|
||||||
|
|
||||||
unsigned cachePorts;
|
unsigned cachePorts;
|
||||||
unsigned width;
|
unsigned width;
|
||||||
|
unsigned frontEndLatency;
|
||||||
unsigned frontEndWidth;
|
unsigned frontEndWidth;
|
||||||
|
unsigned backEndLatency;
|
||||||
unsigned backEndWidth;
|
unsigned backEndWidth;
|
||||||
unsigned backEndSquashLatency;
|
unsigned backEndSquashLatency;
|
||||||
unsigned backEndLatency;
|
|
||||||
unsigned maxInstBufferSize;
|
unsigned maxInstBufferSize;
|
||||||
unsigned numPhysicalRegs;
|
unsigned numPhysicalRegs;
|
||||||
unsigned maxOutstandingMemOps;
|
unsigned maxOutstandingMemOps;
|
||||||
|
@ -149,6 +150,7 @@ class SimpleParams : public BaseCPU::Params
|
||||||
//
|
//
|
||||||
unsigned LQEntries;
|
unsigned LQEntries;
|
||||||
unsigned SQEntries;
|
unsigned SQEntries;
|
||||||
|
bool lsqLimits;
|
||||||
|
|
||||||
//
|
//
|
||||||
// Memory dependence
|
// Memory dependence
|
||||||
|
|
Loading…
Reference in a new issue