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forgot to commit miscreg file

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--HG--
extra : convert_revision : c2ede9efbf7b264c32d5565d3f0fc0601c4cd63b
This commit is contained in:
Ali Saidi 2006-12-04 20:29:55 -05:00
parent 8b1bcc3f52
commit 4d57cab49a
1 changed files with 399 additions and 470 deletions
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137
src/arch/sparc/miscregfile.cc
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@ -37,10 +37,6 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#if FULL_SYSTEM
#include "arch/sparc/system.hh"
#endif
using namespace SparcISA;
using namespace std;
@ -283,7 +279,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
{
switch (miscReg) {
// tick and stick are aliased to each other in niagra
case MISCREG_STICK:
case MISCREG_TICK:
case MISCREG_PRIVTICK:
// I'm not sure why legion ignores the lowest two bits, but we'll go
@ -291,10 +286,8 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
// change from curCycle() to instCount() until we're done with legion
DPRINTFN("Instruction Count when STICK read: %#X\n",
tc->getCpuPtr()->instCount());
uint64_t t1 = mbits(tc->getCpuPtr()->instCount() - (tick &
mask(63)),62,2);
uint64_t t2 = mbits(tick,63,63) ;
return t1 | t2;
return mbits(tc->getCpuPtr()->instCount() - (tick &
mask(63)),62,2) | mbits(tick,63,63) ;
case MISCREG_FPRS:
panic("FPU not implemented\n");
case MISCREG_PCR:
@ -303,17 +296,25 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
/** Floating Point Status Register */
case MISCREG_FSR:
panic("Floating Point not implemented\n");
//We'll include this only in FS so we don't need the SparcSystem type around
//in SE.
/*#if FULL_SYSTEM
case MISCREG_STICK:
SparcSystem *sys;
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
#endif*/
case MISCREG_SOFTINT:
case MISCREG_SOFTINT_CLR:
case MISCREG_SOFTINT_SET:
case MISCREG_TICK_CMPR:
case MISCREG_STICK_CMPR:
case MISCREG_HPSTATE:
case MISCREG_HINTP:
case MISCREG_HTSTATE:
case MISCREG_HTBA:
case MISCREG_HVER:
return NWindows | MaxTL << 8 | MaxGL << 16;
case MISCREG_STRAND_STS_REG:
case MISCREG_HSTICK_CMPR:
#if FULL_SYSTEM
return readFSRegWithEffect(miscReg, tc);
#else
panic("Accessing Fullsystem register is SE mode\n");
#endif
}
return readReg(miscReg);
}
@ -522,10 +523,6 @@ void MiscRegFile::setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc)
{
const uint64_t Bit64 = (1ULL << 63);
#if FULL_SYSTEM
uint64_t time;
SparcSystem *sys;
#endif
switch (miscReg) {
case MISCREG_STICK:
case MISCREG_TICK:
@ -551,71 +548,22 @@ void MiscRegFile::setRegWithEffect(int miscReg,
case MISCREG_GL:
tc->changeRegFileContext(CONTEXT_GLOBALS, val);
break;
case MISCREG_SOFTINT:
//We need to inject interrupts, and or notify the interrupt
//object that it needs to use a different interrupt level.
//Any newly appropriate interrupts will happen when the cpu gets
//around to checking for them. This might not be quite what we
//want.
break;
case MISCREG_SOFTINT_CLR:
//Do whatever this is supposed to do...
break;
case MISCREG_SOFTINT_SET:
//Do whatever this is supposed to do...
break;
#if FULL_SYSTEM
case MISCREG_TICK_CMPR:
if (tickCompare == NULL)
tickCompare = new TickCompareEvent(this, tc);
setReg(miscReg, val);
if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
tickCompare->deschedule();
time = (tick_cmpr & mask(63)) - (tick & mask(63));
if (!(tick_cmpr & ~mask(63)) && time > 0)
tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
break;
#endif
case MISCREG_PIL:
//We need to inject interrupts, and or notify the interrupt
//object that it needs to use a different interrupt level.
//Any newly appropriate interrupts will happen when the cpu gets
//around to checking for them. This might not be quite what we
//want.
break;
//We'll include this only in FS so we don't need the SparcSystem type around
//in SE.
#if FULL_SYSTEM
// @todo figure out how we're actualy going to do this. In niagra the
// registers are aliased to the same thing (see tick above)
/*case MISCREG_STICK:
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
stick |= val & Bit64;
break;*/
case MISCREG_SOFTINT:
case MISCREG_TICK_CMPR:
case MISCREG_STICK_CMPR:
if (sTickCompare == NULL)
sTickCompare = new STickCompareEvent(this, tc);
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
sTickCompare->deschedule();
time = (stick_cmpr & mask(63)) - sys->sysTick;
if (!(stick_cmpr & ~mask(63)) && time > 0)
sTickCompare->schedule(time * Clock::Int::ns);
break;
case MISCREG_HPSTATE:
case MISCREG_HINTP:
case MISCREG_HTSTATE:
case MISCREG_HTBA:
case MISCREG_HVER:
case MISCREG_STRAND_STS_REG:
case MISCREG_HSTICK_CMPR:
if (hSTickCompare == NULL)
hSTickCompare = new HSTickCompareEvent(this, tc);
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
hSTickCompare->deschedule();
int64_t time = (hstick_cmpr & mask(63)) - sys->sysTick;
if (!(hstick_cmpr & ~mask(63)) && time > 0)
hSTickCompare->schedule(time * Clock::Int::ns);
break;
#if FULL_SYSTEM
setFSRegWithEffect(miscReg, val, tc);
return;
#else
panic("Accessing Fullsystem register is SE mode\n");
#endif
}
setReg(miscReg, val);
@ -720,24 +668,5 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
UNSERIALIZE_SCALAR(dTlbSfsr);
UNSERIALIZE_SCALAR(dTlbSfar);
UNSERIALIZE_SCALAR(dTlbTagAccess);
UNSERIALIZE_ARRAY(scratchPad,8);}
#if FULL_SYSTEM
void
MiscRegFile::processTickCompare(ThreadContext *tc)
{
panic("tick compare not implemented\n");
UNSERIALIZE_ARRAY(scratchPad,8);
}
void
MiscRegFile::processSTickCompare(ThreadContext *tc)
{
panic("tick compare not implemented\n");
}
void
MiscRegFile::processHSTickCompare(ThreadContext *tc)
{
panic("tick compare not implemented\n");
}
#endif