inorder: redefine DynInst FP result type
Sharing the FP value w/the integer values was giving inconsistent results esp. when their is a 32-bit integer register matched w/a 64-bit float value
This commit is contained in:
parent
db8b1e4b78
commit
4d4c7d79d0
7 changed files with 116 additions and 67 deletions
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@ -195,6 +195,7 @@ InOrderCPU::InOrderCPU(Params *params)
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timeBuffer(2 , 2),
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removeInstsThisCycle(false),
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activityRec(params->name, NumStages, 10, params->activity),
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stCondFails(0),
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#if FULL_SYSTEM
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system(params->system),
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physmem(system->physmem),
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@ -206,6 +207,7 @@ InOrderCPU::InOrderCPU(Params *params)
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switchCount(0),
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deferRegistration(false/*params->deferRegistration*/),
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stageTracing(params->stageTracing),
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lastRunningCycle(0),
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instsPerSwitch(0)
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{
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ThreadID active_threads;
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@ -258,6 +260,9 @@ InOrderCPU::InOrderCPU(Params *params)
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}
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for (ThreadID tid = 0; tid < numThreads; ++tid) {
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pc[tid].set(0);
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lastCommittedPC[tid].set(0);
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#if FULL_SYSTEM
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// SMT is not supported in FS mode yet.
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assert(numThreads == 1);
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@ -1170,12 +1175,18 @@ InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
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FloatReg
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InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
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{
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DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
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tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
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return floatRegs.f[tid][reg_idx];
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}
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FloatRegBits
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InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
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{;
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{
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DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
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tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
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return floatRegs.i[tid][reg_idx];
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}
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@ -1199,6 +1210,11 @@ void
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InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
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{
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floatRegs.f[tid][reg_idx] = val;
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DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
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"%x, %08f\n",
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tid, reg_idx,
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floatRegs.i[tid][reg_idx],
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floatRegs.f[tid][reg_idx]);
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}
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@ -1206,6 +1222,11 @@ void
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InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
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{
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floatRegs.i[tid][reg_idx] = val;
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DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
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"%x, %08f\n",
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tid, reg_idx,
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floatRegs.i[tid][reg_idx],
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floatRegs.f[tid][reg_idx]);
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}
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uint64_t
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@ -1257,6 +1278,11 @@ InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
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MiscReg
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InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
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{
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DPRINTF(InOrderCPU, "MiscReg: %i\n", misc_reg);
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DPRINTF(InOrderCPU, "tid: %i\n", tid);
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DPRINTF(InOrderCPU, "tcBase: %x\n", tcBase(tid));
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DPRINTF(InOrderCPU, "isa-tid: %x\n", &isa[tid]);
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return isa[tid].readMiscReg(misc_reg, tcBase(tid));
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}
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@ -262,17 +262,11 @@ class InOrderCPU : public BaseCPU
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*/
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unsigned fetchPortIdx;
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/** Identifies the resource id that identifies a ITB */
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unsigned itbIdx;
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/** Identifies the resource id that identifies a data
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* access unit.
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*/
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unsigned dataPortIdx;
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/** Identifies the resource id that identifies a DTB */
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unsigned dtbIdx;
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/** The Pipeline Stages for the CPU */
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PipelineStage *pipelineStage[ThePipeline::NumStages];
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@ -69,8 +69,6 @@ InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
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lqIdx(0), sqIdx(0), instListIt(NULL), onInstList(false)
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{
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for(int i = 0; i < MaxInstSrcRegs; i++) {
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instSrc[i].integer = 0;
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instSrc[i].dbl = 0;
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_readySrcRegIdx[i] = false;
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_srcRegIdx[i] = 0;
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}
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@ -124,9 +122,6 @@ InOrderDynInst::initVars()
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nextStage = 0;
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for(int i = 0; i < MaxInstDestRegs; i++)
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instResult[i].val.integer = 0;
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status.reset();
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memAddrReady = false;
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@ -355,39 +350,48 @@ InOrderDynInst::releaseReq(ResourceRequest* req)
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void
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InOrderDynInst::setIntSrc(int idx, uint64_t val)
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{
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i being set "
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] Int being set "
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"to %#x.\n", threadNumber, seqNum, idx, val);
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instSrc[idx].integer = val;
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instSrc[idx].intVal = val;
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}
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/** Records an fp register being set to a value. */
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void
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InOrderDynInst::setFloatSrc(int idx, FloatReg val)
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{
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instSrc[idx].dbl = val;
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instSrc[idx].fpVal.f = val;
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] FP being set "
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"to %x, %08f...%08f\n", threadNumber, seqNum, idx,
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instSrc[idx].fpVal.i, instSrc[idx].fpVal.f, val);
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}
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/** Records an fp register being set to an integer value. */
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void
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InOrderDynInst::setFloatRegBitsSrc(int idx, uint64_t val)
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InOrderDynInst::setFloatRegBitsSrc(int idx, FloatRegBits val)
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{
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instSrc[idx].integer = val;
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instSrc[idx].fpVal.i = val;
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] FPBits being set "
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"to %x, %08f...%x\n", threadNumber, seqNum, idx,
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instSrc[idx].fpVal.i, instSrc[idx].fpVal.f, val);
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}
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/** Reads a integer register. */
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IntReg
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InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid)
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{
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i read as %#x.\n",
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threadNumber, seqNum, idx, instSrc[idx].integer);
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return instSrc[idx].integer;
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] IntVal read as %#x.\n",
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threadNumber, seqNum, idx, instSrc[idx].intVal);
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return instSrc[idx].intVal;
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}
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/** Reads a FP register. */
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FloatReg
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InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx)
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{
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return instSrc[idx].dbl;
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] FPVal being read "
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"as %x, %08f.\n", threadNumber, seqNum, idx,
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instSrc[idx].fpVal.i, instSrc[idx].fpVal.f);
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return instSrc[idx].fpVal.f;
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}
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@ -395,7 +399,10 @@ InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx)
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FloatRegBits
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InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx)
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{
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return instSrc[idx].integer;
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] FPBits being read "
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"as %x, %08f.\n", threadNumber, seqNum, idx,
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instSrc[idx].fpVal.i, instSrc[idx].fpVal.f);
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return instSrc[idx].fpVal.i;
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}
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/** Reads a miscellaneous register. */
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@ -414,8 +421,8 @@ InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
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{
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Misc. Reg Source Value %i"
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" read as %#x.\n", threadNumber, seqNum, idx,
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instSrc[idx].integer);
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return instSrc[idx].integer;
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instSrc[idx].intVal);
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return instSrc[idx].intVal;
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}
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@ -427,7 +434,7 @@ InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
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const MiscReg &val)
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{
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instResult[idx].type = Integer;
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instResult[idx].val.integer = val;
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instResult[idx].res.intVal = val;
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instResult[idx].tick = curTick();
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
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@ -457,7 +464,7 @@ void
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InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
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{
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instResult[idx].type = Integer;
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instResult[idx].val.integer = val;
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instResult[idx].res.intVal = val;
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instResult[idx].tick = curTick();
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Int Reg. %i "
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@ -469,13 +476,13 @@ InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
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void
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InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
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{
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instResult[idx].val.dbl = val;
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instResult[idx].res.fpVal.f = val;
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instResult[idx].type = Float;
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instResult[idx].tick = curTick();
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
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"being set to %#x (result-tick:%i).\n",
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threadNumber, seqNum, idx, val, instResult[idx].tick);
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Result Float Reg. %i "
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"being set to %#x, %08f (result-tick:%i).\n",
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threadNumber, seqNum, idx, val, val, instResult[idx].tick);
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}
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/** Sets a FP register as a integer. */
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@ -484,10 +491,10 @@ InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
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FloatRegBits val)
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{
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instResult[idx].type = Integer;
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instResult[idx].val.integer = val;
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instResult[idx].res.fpVal.i = val;
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instResult[idx].tick = curTick();
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Result Float Reg. Bits %i "
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"being set to %#x (result-tick:%i).\n",
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threadNumber, seqNum, idx, val, instResult[idx].tick);
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}
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@ -89,6 +89,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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// Floating point register type.
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typedef TheISA::FloatReg FloatReg;
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// Floating point register type.
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typedef TheISA::FloatRegBits FloatRegBits;
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// Floating point register type.
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typedef TheISA::MiscReg MiscReg;
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typedef short int PhysRegIndex;
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@ -207,13 +209,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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/** How many source registers are ready. */
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unsigned readyRegs;
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/** An instruction src/dest has to be one of these types */
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union InstValue {
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uint64_t integer;
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double dbl;
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};
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//@TODO: Naming Convention for Enums?
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enum ResultType {
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None,
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Integer,
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@ -221,19 +216,30 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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Double
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};
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/** An instruction src/dest has to be one of these types */
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struct InstValue {
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IntReg intVal;
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union {
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FloatReg f;
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FloatRegBits i;
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} fpVal;
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InstValue()
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{
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intVal = 0;
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fpVal.i = 0;
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}
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};
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/** Result of an instruction execution */
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struct InstResult {
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ResultType type;
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InstValue val;
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InstValue res;
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Tick tick;
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InstResult()
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: type(None), tick(0)
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{
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val.integer = 0;
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val.dbl = 0;
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}
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{ }
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};
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/** The source of the instruction; assumes for now that there's only one
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@ -852,10 +858,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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* source register to a value. */
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void setIntSrc(int idx, uint64_t val);
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void setFloatSrc(int idx, FloatReg val);
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void setFloatRegBitsSrc(int idx, uint64_t val);
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void setFloatRegBitsSrc(int idx, TheISA::FloatRegBits val);
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uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
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uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
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uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; }
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uint64_t readIntSrc(int idx) { return instSrc[idx].intVal; }
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/** These Instructions read a integer/float/misc. source register
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* value in the instruction. The instruction's execute function will
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@ -879,18 +885,17 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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uint64_t readIntResult(int idx)
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{
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return instResult[idx].val.integer;
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return instResult[idx].res.intVal;
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}
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/** Depending on type, return Float or Double */
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double readFloatResult(int idx)
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FloatReg readFloatResult(int idx)
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{
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return instResult[idx].val.dbl;
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return instResult[idx].res.fpVal.f;
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}
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Tick readResultTime(int idx) { return instResult[idx].tick; }
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uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
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uint64_t* getIntResultPtr(int idx) { return &instResult[idx].res.intVal; }
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/** This is the interface that an instruction will use to write
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* it's destination register.
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@ -104,7 +104,7 @@ RegDepMap::insert(DynInstPtr inst)
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inst->flattenDestReg(i, flat_idx);
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if (flat_idx == TheISA::ZeroReg) {
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if (flat_idx == TheISA::ZeroReg && reg_type == InOrderCPU::IntType) {
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DPRINTF(RegDepMap, "[sn:%i]: Ignoring Insert-Dependency tracking for "
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"ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
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flat_idx);
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@ -143,15 +143,18 @@ RegDepMap::remove(DynInstPtr inst)
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for (int i = 0; i < dest_regs; i++) {
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RegIndex flat_idx = inst->flattenedDestRegIdx(i);
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InOrderCPU::RegType reg_type = cpu->getRegType(inst->destRegIdx(i));
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if (flat_idx == TheISA::ZeroReg) {
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// Merge Dyn Inst & CPU Result Types
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if (flat_idx == TheISA::ZeroReg &&
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reg_type == InOrderCPU::IntType) {
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DPRINTF(RegDepMap, "[sn:%i]: Ignoring Remove-Dependency tracking for "
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"ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
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flat_idx);
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continue;
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}
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InOrderCPU::RegType reg_type = cpu->getRegType(inst->destRegIdx(i));
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remove(reg_type, flat_idx, inst);
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}
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}
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@ -174,7 +177,7 @@ RegDepMap::remove(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
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}
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list_it++;
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}
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panic("[sn:%i] Did not find entry for %i ", inst->seqNum, idx);
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panic("[sn:%i] Did not find entry for %i, type:%i\n", inst->seqNum, idx, reg_type);
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}
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void
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@ -142,6 +142,9 @@ ExecutionUnit::execute(int slot_num)
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// Evaluate Branch
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fault = inst->execute();
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// Should unconditional control , pc relative count as an
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// execution??? Probably not.
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executions++;
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if (fault == NoFault) {
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@ -204,11 +207,19 @@ ExecutionUnit::execute(int slot_num)
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if (fault == NoFault) {
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inst->setExecuted();
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result "
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"of execution is 0x%x.\n", inst->readTid(),
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seq_num,
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(inst->resultType(0) == InOrderDynInst::Float) ?
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inst->readFloatResult(0) : inst->readIntResult(0));
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#if TRACING_ON
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for (int didx = 0; didx < inst->numDestRegs(); didx++)
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if (inst->resultType(didx) == InOrderDynInst::Float ||
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inst->resultType(didx) == InOrderDynInst::Double)
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
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"of FP execution is %08f (%x).\n", inst->readTid(),
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seq_num, didx, inst->readFloatResult(didx),
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inst->readIntResult(didx));
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else
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
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"of Int execution is 0x%x.\n", inst->readTid(),
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seq_num, didx, inst->readIntResult(didx));
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#endif
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#if !FULL_SYSTEM
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// The Syscall might change the PC, so conservatively
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@ -181,7 +181,7 @@ UseDefUnit::execute(int slot_idx)
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RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, reg_type, tid);
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inst->flattenSrcReg(ud_idx, flat_idx);
|
||||
|
||||
if (flat_idx == TheISA::ZeroReg) {
|
||||
if (flat_idx == TheISA::ZeroReg && reg_type == InOrderCPU::IntType) {
|
||||
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Ignoring Reading of ISA-ZeroReg "
|
||||
"(Int. Reg %i).\n", tid, inst->seqNum, flat_idx);
|
||||
ud_req->done();
|
||||
|
@ -226,6 +226,9 @@ UseDefUnit::execute(int slot_idx)
|
|||
inst->setFloatSrc(ud_idx,
|
||||
cpu->readFloatReg(flat_idx,
|
||||
inst->readTid()));
|
||||
inst->setFloatRegBitsSrc(ud_idx,
|
||||
cpu->readFloatRegBits(flat_idx,
|
||||
inst->readTid()));
|
||||
floatRegFileReads++;
|
||||
}
|
||||
break;
|
||||
|
@ -238,7 +241,7 @@ UseDefUnit::execute(int slot_idx)
|
|||
tid, seq_num,
|
||||
reg_idx - Ctrl_Base_DepTag, flat_idx,
|
||||
cpu->readMiscReg(flat_idx,
|
||||
inst->readTid()));
|
||||
inst->readTid()));
|
||||
inst->setIntSrc(ud_idx,
|
||||
cpu->readMiscReg(flat_idx,
|
||||
inst->readTid()));
|
||||
|
@ -331,7 +334,7 @@ UseDefUnit::execute(int slot_idx)
|
|||
RegIndex reg_idx = inst->_destRegIdx[ud_idx];
|
||||
RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, reg_type, tid);
|
||||
|
||||
if (flat_idx == TheISA::ZeroReg) {
|
||||
if (flat_idx == TheISA::ZeroReg && reg_type == InOrderCPU::IntType) {
|
||||
DPRINTF(IntRegs, "[tid:%i]: Ignoring Writing of ISA-ZeroReg "
|
||||
"(Int. Reg %i)\n", tid, flat_idx);
|
||||
ud_req->done();
|
||||
|
@ -374,7 +377,7 @@ UseDefUnit::execute(int slot_idx)
|
|||
if (inst->resultType(ud_idx) ==
|
||||
InOrderDynInst::Integer) {
|
||||
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Writing FP-Bits "
|
||||
"Result 0x%x (bits:0x%x) to register "
|
||||
"Result %08f (bits:0x%x) to register "
|
||||
"idx %i (%i).\n",
|
||||
tid, seq_num,
|
||||
inst->readFloatResult(ud_idx),
|
||||
|
@ -388,7 +391,7 @@ UseDefUnit::execute(int slot_idx)
|
|||
} else if (inst->resultType(ud_idx) ==
|
||||
InOrderDynInst::Float) {
|
||||
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Writing Float "
|
||||
"Result 0x%x (bits:0x%x) to register "
|
||||
"Result %08f (bits:0x%x) to register "
|
||||
"idx %i (%i).\n",
|
||||
tid, seq_num, inst->readFloatResult(ud_idx),
|
||||
inst->readIntResult(ud_idx),
|
||||
|
@ -400,7 +403,7 @@ UseDefUnit::execute(int slot_idx)
|
|||
} else if (inst->resultType(ud_idx) ==
|
||||
InOrderDynInst::Double) {
|
||||
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Writing Double "
|
||||
"Result 0x%x (bits:0x%x) to register "
|
||||
"Result %08f (bits:0x%x) to register "
|
||||
"idx %i (%i).\n",
|
||||
tid, seq_num,
|
||||
inst->readFloatResult(ud_idx),
|
||||
|
|
Loading…
Reference in a new issue