Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 1da75335907fee2d1745ec13e515819dfe2aad89
This commit is contained in:
Steve Reinhardt
commit
4d1bcbcd36
15 changed files with 334 additions and 242 deletions
|
|
@ -127,9 +127,13 @@ def print_error(message):
|
|||
|
||||
def handle_statement(parser, container, statement):
|
||||
if statement.is_microop:
|
||||
if statement.mnemonic not in parser.microops.keys():
|
||||
raise Exception, "Unrecognized mnemonic: %s" % statement.mnemonic
|
||||
parser.symbols["__microopClassFromInsideTheAssembler"] = \
|
||||
parser.microops[statement.mnemonic]
|
||||
try:
|
||||
microop = eval('parser.microops[statement.mnemonic](%s)' %
|
||||
statement.params)
|
||||
microop = eval('__microopClassFromInsideTheAssembler(%s)' %
|
||||
statement.params, {}, parser.symbols)
|
||||
except:
|
||||
print_error("Error creating microop object with mnemonic %s." % \
|
||||
statement.mnemonic)
|
||||
|
|
@ -144,8 +148,13 @@ def handle_statement(parser, container, statement):
|
|||
print_error("Error adding microop.")
|
||||
raise
|
||||
elif statement.is_directive:
|
||||
if statement.name not in container.directives.keys():
|
||||
raise Exception, "Unrecognized directive: %s" % statement.name
|
||||
parser.symbols["__directiveFunctionFromInsideTheAssembler"] = \
|
||||
container.directives[statement.name]
|
||||
try:
|
||||
eval('container.directives[statement.name](%s)' % statement.params)
|
||||
eval('__directiveFunctionFromInsideTheAssembler(%s)' %
|
||||
statement.params, {}, parser.symbols)
|
||||
except:
|
||||
print_error("Error executing directive.")
|
||||
print container.directives
|
||||
|
|
@ -213,23 +222,6 @@ def t_params_COLON(t):
|
|||
t.lexer.begin('asm')
|
||||
return t
|
||||
|
||||
# An "ID" in the micro assembler is either a label, directive, or mnemonic
|
||||
# If it's either a directive or a mnemonic, it will be optionally followed by
|
||||
# parameters. If it's a label, the following colon will make the lexer stop
|
||||
# looking for parameters.
|
||||
def t_asm_ID(t):
|
||||
r'[A-Za-z_]\w*'
|
||||
t.type = reserved_map.get(t.value, 'ID')
|
||||
t.lexer.begin('params')
|
||||
return t
|
||||
|
||||
# If there is a label and you're -not- in the assember (which would be caught
|
||||
# above), don't start looking for parameters.
|
||||
def t_ANY_ID(t):
|
||||
r'[A-Za-z_]\w*'
|
||||
t.type = reserved_map.get(t.value, 'ID')
|
||||
return t
|
||||
|
||||
# Parameters are a string of text which don't contain an unescaped statement
|
||||
# statement terminator, ie a newline or semi colon.
|
||||
def t_params_PARAMS(t):
|
||||
|
|
@ -243,6 +235,23 @@ def t_params_PARAMS(t):
|
|||
t.lexer.begin('asm')
|
||||
return t
|
||||
|
||||
# An "ID" in the micro assembler is either a label, directive, or mnemonic
|
||||
# If it's either a directive or a mnemonic, it will be optionally followed by
|
||||
# parameters. If it's a label, the following colon will make the lexer stop
|
||||
# looking for parameters.
|
||||
def t_asm_ID(t):
|
||||
r'[A-Za-z_]\w*'
|
||||
t.type = reserved_map.get(t.value, 'ID')
|
||||
t.lexer.begin('params')
|
||||
return t
|
||||
|
||||
# If there is a label and you're -not- in the assembler (which would be caught
|
||||
# above), don't start looking for parameters.
|
||||
def t_ANY_ID(t):
|
||||
r'[A-Za-z_]\w*'
|
||||
t.type = reserved_map.get(t.value, 'ID')
|
||||
return t
|
||||
|
||||
# Braces enter and exit micro assembly
|
||||
def t_INITIAL_LBRACE(t):
|
||||
r'\{'
|
||||
|
|
@ -477,14 +486,11 @@ class MicroAssembler(object):
|
|||
self.parser.microops = microops
|
||||
self.parser.rom = rom
|
||||
self.parser.rom_macroop_type = rom_macroop_type
|
||||
self.parser.symbols = {}
|
||||
self.symbols = self.parser.symbols
|
||||
|
||||
def assemble(self, asm):
|
||||
self.parser.parse(asm, lexer=self.lexer)
|
||||
# Begin debug printing
|
||||
#for macroop in self.parser.macroops.values():
|
||||
# print macroop
|
||||
#print self.parser.rom
|
||||
# End debug printing
|
||||
macroops = self.parser.macroops
|
||||
self.parser.macroops = {}
|
||||
return macroops
|
||||
|
|
|
|||
|
|
@ -150,4 +150,4 @@ namespace X86ISA
|
|||
};
|
||||
};
|
||||
|
||||
#endif // __ARCH_X86_INTERRUPTS_HH__
|
||||
#endif // __ARCH_X86_INTREGS_HH__
|
||||
|
|
|
|||
|
|
@ -97,7 +97,6 @@ output header {{
|
|||
#include <iostream>
|
||||
|
||||
#include "arch/x86/emulenv.hh"
|
||||
#include "arch/x86/faults.hh"
|
||||
#include "arch/x86/isa_traits.hh"
|
||||
#include "arch/x86/regfile.hh"
|
||||
#include "arch/x86/types.hh"
|
||||
|
|
@ -105,10 +104,12 @@ output header {{
|
|||
#include "cpu/static_inst.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "mem/request.hh" // some constructors use MemReq flags
|
||||
#include "sim/faults.hh"
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
|
||||
#include "arch/x86/faults.hh"
|
||||
#include "arch/x86/segmentregs.hh"
|
||||
#include "base/cprintf.hh"
|
||||
#include "base/loader/symtab.hh"
|
||||
#include "cpu/thread_context.hh" // for Jump::branchTarget()
|
||||
|
|
|
|||
|
|
@ -56,26 +56,22 @@
|
|||
microcode = '''
|
||||
def macroop SUB_R_I
|
||||
{
|
||||
subi "env.reg", "env.reg", "IMMEDIATE"
|
||||
subi reg, reg, imm
|
||||
};
|
||||
|
||||
def macroop SUB_M_I
|
||||
{
|
||||
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
subi "NUM_INTREGS+1", "NUM_INTREGS+1", "IMMEDIATE"
|
||||
st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
ld t1, ds, [scale, index, base], disp
|
||||
subi t1, t1, imm
|
||||
st t1, ds, [scale, index, base], disp
|
||||
};
|
||||
|
||||
def macroop SUB_P_I
|
||||
{
|
||||
rdip "NUM_INTREGS+7"
|
||||
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
subi "NUM_INTREGS+1", "NUM_INTREGS+1", "IMMEDIATE"
|
||||
st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
rdip t7
|
||||
ld t1, ds, [scale, index, base], disp
|
||||
subi t1, t1, imm
|
||||
st t1, ds, [scale, index, base], disp
|
||||
};
|
||||
'''
|
||||
#let {{
|
||||
|
|
|
|||
|
|
@ -56,44 +56,40 @@
|
|||
microcode = '''
|
||||
def macroop TEST_M_R
|
||||
{
|
||||
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
and "NUM_INTREGS", "NUM_INTREGS+1", "env.reg"
|
||||
ld t1, ds, [scale, index, base], disp
|
||||
and t0, t1, reg
|
||||
};
|
||||
|
||||
def macroop TEST_P_R
|
||||
{
|
||||
rdip "NUM_INTREGS+7"
|
||||
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
and "NUM_INTREGS", "NUM_INTREGS+1", "env.reg"
|
||||
rdip t7
|
||||
ld t1, ds, [scale, index, base], disp
|
||||
and t0, t1, reg
|
||||
};
|
||||
|
||||
def macroop TEST_R_R
|
||||
{
|
||||
and "NUM_INTREGS", "env.reg", "env.regm"
|
||||
and t0, reg, regm
|
||||
};
|
||||
|
||||
def macroop TEST_M_I
|
||||
{
|
||||
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
limm "NUM_INTREGS+2", "IMMEDIATE"
|
||||
and "NUM_INTREGS", "NUM_INTREGS+1", "NUM_INTREGS+2"
|
||||
ld t1, ds, [scale, index, base], disp
|
||||
limm t2, imm
|
||||
and t0, t1, t2
|
||||
};
|
||||
|
||||
def macroop TEST_P_I
|
||||
{
|
||||
rdip "NUM_INTREGS+7"
|
||||
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
limm "NUM_INTREGS+2", "IMMEDIATE"
|
||||
and "NUM_INTREGS", "NUM_INTREGS+1", "NUM_INTREGS+2"
|
||||
rdip t7
|
||||
ld t1, ds, [scale, index, base], disp
|
||||
limm t2, imm
|
||||
and t0, t1, t2
|
||||
};
|
||||
|
||||
def macroop TEST_R_I
|
||||
{
|
||||
limm "NUM_INTREGS+1", "IMMEDIATE"
|
||||
and "NUM_INTREGS", "env.reg", "NUM_INTREGS+1"
|
||||
limm t1, imm
|
||||
and t0, reg, t1
|
||||
};
|
||||
'''
|
||||
|
|
|
|||
|
|
@ -56,13 +56,14 @@
|
|||
microcode = '''
|
||||
def macroop CALL_I
|
||||
{
|
||||
.adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
|
||||
# Make the default data size of pops 64 bits in 64 bit mode
|
||||
.adjust_env oszIn64Override
|
||||
|
||||
limm "NUM_INTREGS+2", "IMMEDIATE"
|
||||
rdip "NUM_INTREGS+1"
|
||||
subi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
|
||||
st "NUM_INTREGS+1", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
|
||||
wrip "NUM_INTREGS+1", "NUM_INTREGS+2"
|
||||
limm t2, imm
|
||||
rdip t1
|
||||
subi "INTREG_RSP", "INTREG_RSP", dsz
|
||||
st t1, ss, [0, t0, "INTREG_RSP"]
|
||||
wrip t1, t2
|
||||
};
|
||||
'''
|
||||
#let {{
|
||||
|
|
|
|||
|
|
@ -55,59 +55,55 @@
|
|||
|
||||
microcode = '''
|
||||
def macroop MOV_R_R {
|
||||
mov "env.reg", "env.reg", "env.regm"
|
||||
mov reg, reg, regm
|
||||
};
|
||||
|
||||
def macroop MOV_M_R {
|
||||
st "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
|
||||
st reg, ds, [scale, index, base], disp
|
||||
};
|
||||
|
||||
def macroop MOV_P_R {
|
||||
rdip "NUM_INTREGS+7"
|
||||
st "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
|
||||
rdip t7
|
||||
st reg, ds, [scale, index, base], disp
|
||||
};
|
||||
|
||||
def macroop MOV_R_M {
|
||||
ld "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
|
||||
ld reg, ds, [scale, index, base], disp
|
||||
};
|
||||
|
||||
def macroop MOV_R_P {
|
||||
rdip "NUM_INTREGS+7"
|
||||
ld "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
|
||||
rdip t7
|
||||
ld reg, ds, [scale, index, base], disp
|
||||
};
|
||||
|
||||
def macroop MOV_R_I {
|
||||
limm "env.reg", "IMMEDIATE"
|
||||
limm reg, imm
|
||||
};
|
||||
|
||||
def macroop MOV_M_I {
|
||||
limm "NUM_INTREGS+1", "IMMEDIATE"
|
||||
st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
limm t1, imm
|
||||
st t1, ds, [scale, index, base], disp
|
||||
};
|
||||
|
||||
def macroop MOV_P_I {
|
||||
rdip "NUM_INTREGS+7"
|
||||
limm "NUM_INTREGS+1", "IMMEDIATE"
|
||||
st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
rdip t7
|
||||
limm t1, imm
|
||||
st t1, ds, [scale, index, base], disp
|
||||
};
|
||||
|
||||
def macroop MOVSXD_R_R {
|
||||
sext "env.reg", "env.regm", "env.dataSize"
|
||||
sext reg, regm, dsz
|
||||
};
|
||||
|
||||
def macroop MOVSXD_R_M {
|
||||
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
sext "env.reg", "NUM_INTREGS+1", "env.dataSize"
|
||||
ld t1, ds, [scale, index, base], disp
|
||||
sext reg, t1, dsz
|
||||
};
|
||||
|
||||
def macroop MOVSXD_R_P {
|
||||
rdip "NUM_INTREGS+7"
|
||||
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
sext "env.reg", "NUM_INTREGS+1", "env.dataSize"
|
||||
rdip t7
|
||||
ld t1, ds, [scale, index, base], disp
|
||||
sext reg, t1, dsz
|
||||
};
|
||||
'''
|
||||
#let {{
|
||||
|
|
|
|||
|
|
@ -55,21 +55,19 @@
|
|||
|
||||
microcode = '''
|
||||
def macroop POP_R {
|
||||
|
||||
# Make the default data size of pops 64 bits in 64 bit mode
|
||||
.adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
|
||||
.adjust_env oszIn64Override
|
||||
|
||||
ld "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
|
||||
addi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
|
||||
ld reg, ss, [0, t0, "INTREG_RSP"]
|
||||
addi "INTREG_RSP", "INTREG_RSP", dsz
|
||||
};
|
||||
|
||||
def macroop PUSH_R {
|
||||
|
||||
# Make the default data size of pops 64 bits in 64 bit mode
|
||||
.adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
|
||||
.adjust_env oszIn64Override
|
||||
|
||||
subi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
|
||||
st "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
|
||||
subi "INTREG_RSP", "INTREG_RSP", dsz
|
||||
st reg, ss, [0, t0, "INTREG_RSP"]
|
||||
};
|
||||
'''
|
||||
#let {{
|
||||
|
|
|
|||
|
|
@ -55,11 +55,11 @@
|
|||
|
||||
microcode = '''
|
||||
def macroop LEA_R_M {
|
||||
lea "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
|
||||
lea reg, ds, [scale, index, base], disp
|
||||
};
|
||||
|
||||
def macroop LEA_R_P {
|
||||
rdip "NUM_INTREGS+7"
|
||||
lea "env.reg", 3, ["env.scale", "env.index", "env.base"], "DISPLACEMENT"
|
||||
rdip t7
|
||||
lea reg, ds, [scale, index, base], disp
|
||||
};
|
||||
'''
|
||||
|
|
|
|||
|
|
@ -56,74 +56,64 @@
|
|||
microcode = '''
|
||||
def macroop XOR_R_R
|
||||
{
|
||||
xor "env.reg", "env.reg", "env.regm"
|
||||
xor reg, reg, regm
|
||||
};
|
||||
|
||||
def macroop XOR_R_I
|
||||
{
|
||||
limm "NUM_INTREGS+1", "IMMEDIATE"
|
||||
xor "env.reg", "env.reg", "NUM_INTREGS+1"
|
||||
limm t1, imm
|
||||
xor reg, reg, t1
|
||||
};
|
||||
|
||||
def macroop XOR_M_R
|
||||
{
|
||||
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg"
|
||||
st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
ld t1, ds, [scale, index, base], disp
|
||||
xor t1, t1, reg
|
||||
st t1, ds, [scale, index, base], disp
|
||||
};
|
||||
|
||||
def macroop XOR_P_R
|
||||
{
|
||||
rdip "NUM_INTREGS+7"
|
||||
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg"
|
||||
st "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
rdip t7
|
||||
ld t1, ds, [scale, index, base], disp
|
||||
xor t1, t1, reg
|
||||
st t1, ds, [scale, index, base], disp
|
||||
};
|
||||
|
||||
def macroop XOR_R_M
|
||||
{
|
||||
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
xor "env.reg", "env.reg", "NUM_INTREGS+1"
|
||||
ld t1, ds, [scale, index, base], disp
|
||||
xor reg, reg, t1
|
||||
};
|
||||
|
||||
def macroop XOR_R_P
|
||||
{
|
||||
rdip "NUM_INTREGS+7"
|
||||
ld "NUM_INTREGS+1", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
xor "env.reg", "env.reg", "NUM_INTREGS+1"
|
||||
rdip t7
|
||||
ld t1, ds, [scale, index, base], disp
|
||||
xor reg, reg, t1
|
||||
};
|
||||
|
||||
def macroop AND_R_I
|
||||
{
|
||||
limm "NUM_INTREGS+1", "IMMEDIATE"
|
||||
and "env.reg", "env.reg", "NUM_INTREGS+1"
|
||||
limm t1, imm
|
||||
and reg, reg, t1
|
||||
};
|
||||
|
||||
def macroop AND_M_I
|
||||
{
|
||||
ld "NUM_INTREGS+2", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
limm "NUM_INTREGS+1", "IMMEDIATE"
|
||||
and "NUM_INTREGS+2", "NUM_INTREGS+2", "NUM_INTREGS+1"
|
||||
st "NUM_INTREGS+2", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
ld t2, ds, [scale, index, base], disp
|
||||
limm t1, imm
|
||||
and t2, t2, t1
|
||||
st t2, ds, [scale, index, base], disp
|
||||
};
|
||||
|
||||
def macroop AND_P_I
|
||||
{
|
||||
rdip "NUM_INTREGS+7"
|
||||
ld "NUM_INTREGS+2", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
limm "NUM_INTREGS+1", "IMMEDIATE"
|
||||
and "NUM_INTREGS+2", "NUM_INTREGS+2", "NUM_INTREGS+1"
|
||||
st "NUM_INTREGS+2", 3, ["env.scale", "env.index", "env.base"], \
|
||||
"DISPLACEMENT"
|
||||
rdip t7
|
||||
ld t2, ds, [scale, index, base], disp
|
||||
limm t1, imm
|
||||
and t2, t2, t1
|
||||
st t2, ds, [scale, index, base], disp
|
||||
};
|
||||
'''
|
||||
#let {{
|
||||
|
|
|
|||
|
|
@ -72,5 +72,33 @@ let {{
|
|||
from micro_asm import MicroAssembler, Rom_Macroop, Rom
|
||||
mainRom = Rom('main ROM')
|
||||
assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
|
||||
# Add in symbols for the microcode registers
|
||||
for num in range(15):
|
||||
assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
|
||||
# Add in symbols for the segment descriptor registers
|
||||
for letter in ("C", "D", "E", "F", "G", "S"):
|
||||
assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
|
||||
# Miscellaneous symbols
|
||||
symbols = {
|
||||
"reg" : "env.reg",
|
||||
"regm" : "env.regm",
|
||||
"imm" : "IMMEDIATE",
|
||||
"disp" : "DISPLACEMENT",
|
||||
"scale" : "env.scale",
|
||||
"index" : "env.index",
|
||||
"base" : "env.base",
|
||||
"dsz" : "env.dataSize",
|
||||
"osz" : "env.operandSize",
|
||||
"ssz" : "env.stackSize"
|
||||
}
|
||||
assembler.symbols.update(symbols)
|
||||
|
||||
# Code literal which forces a default 64 bit operand size in 64 bit mode.
|
||||
assembler.symbols["oszIn64Override"] = '''
|
||||
if (machInst.mode.submode == SixtyFourBitMode &&
|
||||
env.dataSize == 4)
|
||||
env.dataSize = 8;
|
||||
'''
|
||||
|
||||
macroopDict = assembler.assemble(microcode)
|
||||
}};
|
||||
|
|
|
|||
|
|
@ -162,6 +162,7 @@ def template MicroRegOpExecute {{
|
|||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(code)s;
|
||||
%(flag_code)s;
|
||||
|
||||
//Write the resulting state to the execution context
|
||||
if(fault == NoFault)
|
||||
|
|
@ -181,6 +182,7 @@ def template MicroRegOpImmExecute {{
|
|||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(code)s;
|
||||
%(flag_code)s;
|
||||
|
||||
//Write the resulting state to the execution context
|
||||
if(fault == NoFault)
|
||||
|
|
@ -304,11 +306,11 @@ def template MicroRegOpImmConstructor {{
|
|||
|
||||
let {{
|
||||
class RegOp(X86Microop):
|
||||
def __init__(self, dest, src1, src2):
|
||||
def __init__(self, dest, src1, src2, setStatus):
|
||||
self.dest = dest
|
||||
self.src1 = src1
|
||||
self.src2 = src2
|
||||
self.setStatus = False
|
||||
self.setStatus = setStatus
|
||||
self.dataSize = "env.dataSize"
|
||||
self.ext = 0
|
||||
|
||||
|
|
@ -326,11 +328,11 @@ let {{
|
|||
return allocator
|
||||
|
||||
class RegOpImm(X86Microop):
|
||||
def __init__(self, dest, src1, imm8):
|
||||
def __init__(self, dest, src1, imm8, setStatus):
|
||||
self.dest = dest
|
||||
self.src1 = src1
|
||||
self.imm8 = imm8
|
||||
self.setStatus = False
|
||||
self.setStatus = setStatus
|
||||
self.dataSize = "env.dataSize"
|
||||
self.ext = 0
|
||||
|
||||
|
|
@ -356,20 +358,22 @@ let {{
|
|||
decoder_output = ""
|
||||
exec_output = ""
|
||||
|
||||
def setUpMicroRegOp(name, Name, base, code, child):
|
||||
def setUpMicroRegOp(name, Name, base, code, child, flagCode):
|
||||
global header_output
|
||||
global decoder_output
|
||||
global exec_output
|
||||
global microopClasses
|
||||
|
||||
iop = InstObjParams(name, Name, base, {"code" : code})
|
||||
iop = InstObjParams(name, Name, base,
|
||||
{"code" : code,
|
||||
"flag_code" : flagCode})
|
||||
header_output += MicroRegOpDeclare.subst(iop)
|
||||
decoder_output += MicroRegOpConstructor.subst(iop)
|
||||
exec_output += MicroRegOpExecute.subst(iop)
|
||||
|
||||
microopClasses[name] = child
|
||||
|
||||
def defineMicroRegOp(mnemonic, code):
|
||||
def defineMicroRegOp(mnemonic, code, flagCode):
|
||||
Name = mnemonic
|
||||
name = mnemonic.lower()
|
||||
|
||||
|
|
@ -382,31 +386,31 @@ let {{
|
|||
|
||||
# Build the all register version of this micro op
|
||||
class RegOpChild(RegOp):
|
||||
def __init__(self, dest, src1, src2):
|
||||
super(RegOpChild, self).__init__(dest, src1, src2)
|
||||
def __init__(self, dest, src1, src2, setStatus=False):
|
||||
super(RegOpChild, self).__init__(dest, src1, src2, setStatus)
|
||||
self.className = Name
|
||||
self.mnemonic = name
|
||||
|
||||
setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild);
|
||||
setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, flagCode);
|
||||
|
||||
# Build the immediate version of this micro op
|
||||
class RegOpChildImm(RegOpImm):
|
||||
def __init__(self, dest, src1, src2):
|
||||
super(RegOpChildImm, self).__init__(dest, src1, src2)
|
||||
def __init__(self, dest, src1, src2, setStatus=False):
|
||||
super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus)
|
||||
self.className = Name + "Imm"
|
||||
self.mnemonic = name + "i"
|
||||
|
||||
setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm);
|
||||
setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, flagCode);
|
||||
|
||||
defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF
|
||||
defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
|
||||
defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF
|
||||
defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF
|
||||
defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
|
||||
defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF
|
||||
defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
|
||||
defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg
|
||||
defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)')
|
||||
defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
|
||||
defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
|
||||
defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF
|
||||
defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF
|
||||
defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "")
|
||||
defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF
|
||||
defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "")
|
||||
defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg
|
||||
defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "")
|
||||
|
||||
# This has it's own function because Wr ops have implicit destinations
|
||||
def defineMicroRegOpWr(mnemonic, code):
|
||||
|
|
@ -423,20 +427,20 @@ let {{
|
|||
# Build the all register version of this micro op
|
||||
class RegOpChild(RegOp):
|
||||
def __init__(self, src1, src2):
|
||||
super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2)
|
||||
super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False)
|
||||
self.className = Name
|
||||
self.mnemonic = name
|
||||
|
||||
setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild);
|
||||
setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, "");
|
||||
|
||||
# Build the immediate version of this micro op
|
||||
class RegOpChildImm(RegOpImm):
|
||||
def __init__(self, src1, src2):
|
||||
super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2)
|
||||
super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False)
|
||||
self.className = Name + "Imm"
|
||||
self.mnemonic = name + "i"
|
||||
|
||||
setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm);
|
||||
setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, "");
|
||||
|
||||
defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2')
|
||||
|
||||
|
|
@ -447,11 +451,11 @@ let {{
|
|||
|
||||
class RegOpChild(RegOp):
|
||||
def __init__(self, dest, src1 = "NUM_INTREGS"):
|
||||
super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS")
|
||||
super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False)
|
||||
self.className = Name
|
||||
self.mnemonic = name
|
||||
|
||||
setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild);
|
||||
setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild, "");
|
||||
|
||||
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
|
||||
|
||||
|
|
@ -461,11 +465,11 @@ let {{
|
|||
|
||||
class RegOpChild(RegOpImm):
|
||||
def __init__(self, dest, src1, src2):
|
||||
super(RegOpChild, self).__init__(dest, src1, src2)
|
||||
super(RegOpChild, self).__init__(dest, src1, src2, False)
|
||||
self.className = Name
|
||||
self.mnemonic = name
|
||||
|
||||
setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild);
|
||||
setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild, "");
|
||||
|
||||
defineMicroRegOpImm('Sext', '''
|
||||
IntReg val = SrcReg1;
|
||||
|
|
|
|||
76
src/arch/x86/segmentregs.hh
Normal file
76
src/arch/x86/segmentregs.hh
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Copyright (c) 2007 The Hewlett-Packard Development Company
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use of this software in source and binary forms,
|
||||
* with or without modification, are permitted provided that the
|
||||
* following conditions are met:
|
||||
*
|
||||
* The software must be used only for Non-Commercial Use which means any
|
||||
* use which is NOT directed to receiving any direct monetary
|
||||
* compensation for, or commercial advantage from such use. Illustrative
|
||||
* examples of non-commercial use are academic research, personal study,
|
||||
* teaching, education and corporate research & development.
|
||||
* Illustrative examples of commercial use are distributing products for
|
||||
* commercial advantage and providing services using the software for
|
||||
* commercial advantage.
|
||||
*
|
||||
* If you wish to use this software or functionality therein that may be
|
||||
* covered by patents for commercial use, please contact:
|
||||
* Director of Intellectual Property Licensing
|
||||
* Office of Strategy and Technology
|
||||
* Hewlett-Packard Company
|
||||
* 1501 Page Mill Road
|
||||
* Palo Alto, California 94304
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer. Redistributions
|
||||
* in binary form must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution. Neither the name of
|
||||
* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission. No right of
|
||||
* sublicense is granted herewith. Derivatives of the software and
|
||||
* output created using the software may be prepared, but only for
|
||||
* Non-Commercial Uses. Derivatives of the software may be shared with
|
||||
* others provided: (i) the others agree to abide by the list of
|
||||
* conditions herein which includes the Non-Commercial Use restrictions;
|
||||
* and (ii) such Derivatives of the software include the above copyright
|
||||
* notice to acknowledge the contribution from this software where
|
||||
* applicable, this list of conditions and the disclaimer below.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_X86_SEGMENTREGS_HH__
|
||||
#define __ARCH_X86_SEGMENTREGS_HH__
|
||||
|
||||
namespace X86ISA
|
||||
{
|
||||
enum SegmentRegIndex
|
||||
{
|
||||
SEGMENT_REG_ES,
|
||||
SEGMENT_REG_CS,
|
||||
SEGMENT_REG_SS,
|
||||
SEGMENT_REG_DS,
|
||||
SEGMENT_REG_FS,
|
||||
SEGMENT_REG_GS,
|
||||
|
||||
NUM_SEGMENTREGS
|
||||
};
|
||||
};
|
||||
|
||||
#endif // __ARCH_X86_SEGMENTREGS_HH__
|
||||
|
|
@ -1,23 +1,23 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 110028 # Simulator instruction rate (inst/s)
|
||||
host_seconds 573.73 # Real time elapsed on the host
|
||||
host_tick_rate 3259967057 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1418499 # Simulator instruction rate (inst/s)
|
||||
host_seconds 44.50 # Real time elapsed on the host
|
||||
host_tick_rate 42028043491 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 63125943 # Number of instructions simulated
|
||||
sim_seconds 1.870335 # Number of seconds simulated
|
||||
sim_ticks 1870335097000 # Number of ticks simulated
|
||||
sim_ticks 1870335101500 # Number of ticks simulated
|
||||
system.cpu0.dcache.ReadReq_accesses 9163941 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_hits 7464208 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_miss_rate 0.185481 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_misses 1699733 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_hits 7464198 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_miss_rate 0.185482 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_misses 1699743 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_accesses 5933396 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_hits 5646723 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits 5646722 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_miss_rate 0.048315 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.WriteReq_misses 286673 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses 286674 # number of WriteReq misses
|
||||
system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_refs 6.625609 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.avg_refs 6.625567 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -26,10 +26,10 @@ system.cpu0.dcache.cache_copies 0 # nu
|
|||
system.cpu0.dcache.demand_accesses 15097337 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_hits 13110931 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits 13110920 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_rate 0.131573 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_misses 1986406 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_miss_rate 0.131574 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_misses 1986417 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
||||
|
|
@ -41,10 +41,10 @@ system.cpu0.dcache.overall_accesses 15097337 # nu
|
|||
system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_hits 13110931 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits 13110920 # number of overall hits
|
||||
system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_rate 0.131573 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_misses 1986406 # number of overall misses
|
||||
system.cpu0.dcache.overall_miss_rate 0.131574 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_misses 1986417 # number of overall misses
|
||||
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
||||
|
|
@ -61,7 +61,7 @@ system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
|
||||
system.cpu0.dcache.protocol.read_invalid 1699733 # read misses to invalid blocks
|
||||
system.cpu0.dcache.protocol.read_invalid 1699743 # read misses to invalid blocks
|
||||
system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
|
||||
system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
|
||||
system.cpu0.dcache.protocol.snoop_inv_modified 2 # Invalidate snoops on modified blocks
|
||||
|
|
@ -69,7 +69,7 @@ system.cpu0.dcache.protocol.snoop_inv_owned 0 #
|
|||
system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
|
||||
system.cpu0.dcache.protocol.snoop_read_exclusive 689 # read snoops on exclusive blocks
|
||||
system.cpu0.dcache.protocol.snoop_read_modified 4128 # read snoops on modified blocks
|
||||
system.cpu0.dcache.protocol.snoop_read_owned 122 # read snoops on owned blocks
|
||||
system.cpu0.dcache.protocol.snoop_read_owned 121 # read snoops on owned blocks
|
||||
system.cpu0.dcache.protocol.snoop_read_shared 2691 # read snoops on shared blocks
|
||||
system.cpu0.dcache.protocol.snoop_readex_exclusive 241 # readEx snoops on exclusive blocks
|
||||
system.cpu0.dcache.protocol.snoop_readex_modified 227 # readEx snoops on modified blocks
|
||||
|
|
@ -83,14 +83,14 @@ system.cpu0.dcache.protocol.snoop_writeinv_modified 0
|
|||
system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
|
||||
system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
|
||||
system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
|
||||
system.cpu0.dcache.protocol.write_invalid 282337 # write misses to invalid blocks
|
||||
system.cpu0.dcache.protocol.write_invalid 282338 # write misses to invalid blocks
|
||||
system.cpu0.dcache.protocol.write_owned 2517 # write misses to owned blocks
|
||||
system.cpu0.dcache.protocol.write_shared 1819 # write misses to shared blocks
|
||||
system.cpu0.dcache.replacements 1978969 # number of replacements
|
||||
system.cpu0.dcache.sampled_refs 1979481 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.replacements 1978980 # number of replacements
|
||||
system.cpu0.dcache.sampled_refs 1979492 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu0.dcache.tagsinuse 504.827576 # Cycle average of tags in use
|
||||
system.cpu0.dcache.total_refs 13115267 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.total_refs 13115256 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu0.dtb.accesses 698037 # DTB accesses
|
||||
|
|
@ -161,7 +161,7 @@ system.cpu0.icache.protocol.snoop_inv_invalid 0
|
|||
system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
|
||||
system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
|
||||
system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
|
||||
system.cpu0.icache.protocol.snoop_read_exclusive 25821 # read snoops on exclusive blocks
|
||||
system.cpu0.icache.protocol.snoop_read_exclusive 25832 # read snoops on exclusive blocks
|
||||
system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks
|
||||
system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks
|
||||
system.cpu0.icache.protocol.snoop_read_shared 13268 # read snoops on shared blocks
|
||||
|
|
@ -225,8 +225,8 @@ system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # nu
|
|||
system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_ticks 1870334889500 # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks_0 1853125118000 99.08% 99.08% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks 1870334894000 # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks_0 1853125122500 99.08% 99.08% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl
|
||||
|
|
@ -246,7 +246,7 @@ system.cpu0.kern.mode_switch_good <err: div-0> # fr
|
|||
system.cpu0.kern.mode_switch_good_kernel 0.162906 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_ticks_kernel 1869377889500 99.95% 99.95% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks_kernel 1869377894000 99.95% 99.95% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks_user 956999000 0.05% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.swap_context 3762 # number of times the context was actually changed
|
||||
|
|
@ -348,7 +348,7 @@ system.cpu1.dcache.protocol.snoop_inv_shared 0
|
|||
system.cpu1.dcache.protocol.snoop_read_exclusive 939 # read snoops on exclusive blocks
|
||||
system.cpu1.dcache.protocol.snoop_read_modified 2438 # read snoops on modified blocks
|
||||
system.cpu1.dcache.protocol.snoop_read_owned 337 # read snoops on owned blocks
|
||||
system.cpu1.dcache.protocol.snoop_read_shared 61769 # read snoops on shared blocks
|
||||
system.cpu1.dcache.protocol.snoop_read_shared 61772 # read snoops on shared blocks
|
||||
system.cpu1.dcache.protocol.snoop_readex_exclusive 103 # readEx snoops on exclusive blocks
|
||||
system.cpu1.dcache.protocol.snoop_readex_modified 275 # readEx snoops on modified blocks
|
||||
system.cpu1.dcache.protocol.snoop_readex_owned 44 # readEx snoops on owned blocks
|
||||
|
|
@ -369,7 +369,7 @@ system.cpu1.dcache.sampled_refs 62660 # Sa
|
|||
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.warmup_cycle 1851266669500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.warmup_cycle 1851266680500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu1.dtb.accesses 323622 # DTB accesses
|
||||
system.cpu1.dtb.acv 116 # DTB access violations
|
||||
|
|
@ -439,7 +439,7 @@ system.cpu1.icache.protocol.snoop_inv_invalid 0
|
|||
system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
|
||||
system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
|
||||
system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
|
||||
system.cpu1.icache.protocol.snoop_read_exclusive 17328 # read snoops on exclusive blocks
|
||||
system.cpu1.icache.protocol.snoop_read_exclusive 17317 # read snoops on exclusive blocks
|
||||
system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks
|
||||
system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks
|
||||
system.cpu1.icache.protocol.snoop_read_shared 199395 # read snoops on shared blocks
|
||||
|
|
@ -463,7 +463,7 @@ system.cpu1.icache.sampled_refs 103609 # Sa
|
|||
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu1.icache.tagsinuse 427.126314 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.warmup_cycle 1868932665500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.warmup_cycle 1868932669000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.writebacks 0 # number of writebacks
|
||||
system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
|
||||
system.cpu1.itb.accesses 1469938 # ITB accesses
|
||||
|
|
@ -501,8 +501,8 @@ system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # nu
|
|||
system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_ticks 1870124001500 # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks_0 1859122583000 99.41% 99.41% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks 1870124006000 # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks_0 1859122587500 99.41% 99.41% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl
|
||||
|
|
@ -520,9 +520,9 @@ system.cpu1.kern.mode_switch_good 1.608089 # fr
|
|||
system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_ticks_kernel 1373909500 0.07% 0.07% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks_kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks_idle 1868002152500 99.90% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks_idle 1868002156500 99.90% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.swap_context 471 # number of times the context was actually changed
|
||||
system.cpu1.kern.syscall 100 # number of syscalls executed
|
||||
system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed
|
||||
|
|
@ -558,30 +558,30 @@ system.disk2.dma_read_txs 0 # Nu
|
|||
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
||||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.l2c.ReadExReq_accesses 306245 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_hits 181107 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_miss_rate 0.408621 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_hits 181108 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_miss_rate 0.408619 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_misses 125138 # number of ReadExReq misses
|
||||
system.l2c.ReadReq_accesses 2724155 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_hits 1782852 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_rate 0.345539 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_accesses 2724166 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_hits 1782863 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_rate 0.345538 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_misses 941303 # number of ReadReq misses
|
||||
system.l2c.Writeback_accesses 427632 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_hits 427632 # number of Writeback hits
|
||||
system.l2c.Writeback_accesses 427634 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_hits 427634 # number of Writeback hits
|
||||
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.l2c.avg_refs 2.242866 # Average number of references to valid blocks.
|
||||
system.l2c.avg_refs 2.242879 # Average number of references to valid blocks.
|
||||
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.demand_accesses 2724155 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses 2724166 # number of demand (read+write) accesses
|
||||
system.l2c.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
||||
system.l2c.demand_hits 1782852 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits 1782863 # number of demand (read+write) hits
|
||||
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_rate 0.345539 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate 0.345538 # miss rate for demand accesses
|
||||
system.l2c.demand_misses 941303 # number of demand (read+write) misses
|
||||
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
|
|
@ -590,13 +590,13 @@ system.l2c.demand_mshr_misses 0 # nu
|
|||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_accesses 3151787 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses 3151800 # number of overall (read+write) accesses
|
||||
system.l2c.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.l2c.overall_hits 2210484 # number of overall hits
|
||||
system.l2c.overall_hits 2210497 # number of overall hits
|
||||
system.l2c.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.l2c.overall_miss_rate 0.298657 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate 0.298656 # miss rate for overall accesses
|
||||
system.l2c.overall_misses 941303 # number of overall misses
|
||||
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
|
|
@ -616,8 +616,8 @@ system.l2c.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.l2c.replacements 1000779 # number of replacements
|
||||
system.l2c.sampled_refs 1066159 # Sample count of references to valid blocks.
|
||||
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.l2c.tagsinuse 65517.575355 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2391252 # Total number of references to valid blocks.
|
||||
system.l2c.tagsinuse 65517.575356 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2391266 # Total number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 618103500 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.writebacks 0 # number of writebacks
|
||||
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
|
||||
|
|
|
|||
|
|
@ -1,23 +1,23 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 109117 # Simulator instruction rate (inst/s)
|
||||
host_seconds 549.94 # Real time elapsed on the host
|
||||
host_tick_rate 3324672454 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1403977 # Simulator instruction rate (inst/s)
|
||||
host_seconds 42.74 # Real time elapsed on the host
|
||||
host_tick_rate 42777462102 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 60007317 # Number of instructions simulated
|
||||
sim_seconds 1.828355 # Number of seconds simulated
|
||||
sim_ticks 1828355481500 # Number of ticks simulated
|
||||
sim_ticks 1828355486000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 9723333 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_hits 7984499 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits 7984498 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.178831 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1738834 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses 1738835 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_accesses 6349447 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_hits 6045093 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.047934 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 304354 # number of WriteReq misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 6.866570 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 6.866566 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -26,10 +26,10 @@ system.cpu.dcache.cache_copies 0 # nu
|
|||
system.cpu.dcache.demand_accesses 16072780 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 14029592 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits 14029591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.127121 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2043188 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses 2043189 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
||||
|
|
@ -41,10 +41,10 @@ system.cpu.dcache.overall_accesses 16072780 # nu
|
|||
system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 14029592 # number of overall hits
|
||||
system.cpu.dcache.overall_hits 14029591 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.127121 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2043188 # number of overall misses
|
||||
system.cpu.dcache.overall_misses 2043189 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
||||
|
|
@ -61,7 +61,7 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
|
||||
system.cpu.dcache.protocol.read_invalid 1738834 # read misses to invalid blocks
|
||||
system.cpu.dcache.protocol.read_invalid 1738835 # read misses to invalid blocks
|
||||
system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
|
||||
system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
|
||||
system.cpu.dcache.protocol.snoop_inv_modified 1 # Invalidate snoops on modified blocks
|
||||
|
|
@ -86,11 +86,11 @@ system.cpu.dcache.protocol.swpf_invalid 0 # so
|
|||
system.cpu.dcache.protocol.write_invalid 304342 # write misses to invalid blocks
|
||||
system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks
|
||||
system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks
|
||||
system.cpu.dcache.replacements 2042663 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2043175 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 2042664 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2043176 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14029604 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.total_refs 14029603 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.dtb.accesses 1020787 # DTB accesses
|
||||
|
|
@ -222,8 +222,8 @@ system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # nu
|
|||
system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks 1828355274000 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_0 1811087543000 99.06% 99.06% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks 1828355278500 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_0 1811087547500 99.06% 99.06% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl
|
||||
|
|
@ -243,7 +243,7 @@ system.cpu.kern.mode_switch_good_user 1 # fr
|
|||
system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks_idle 1800056177500 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks_idle 1800056182000 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
||||
system.cpu.kern.syscall 326 # number of syscalls executed
|
||||
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
|
||||
|
|
@ -296,24 +296,24 @@ system.l2c.ReadExReq_accesses 304342 # nu
|
|||
system.l2c.ReadExReq_hits 187346 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_miss_rate 0.384423 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_misses 116996 # number of ReadExReq misses
|
||||
system.l2c.ReadReq_accesses 2658871 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_hits 1717827 # number of ReadReq hits
|
||||
system.l2c.ReadReq_accesses 2658872 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_hits 1717828 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_rate 0.353926 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_misses 941044 # number of ReadReq misses
|
||||
system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_hits 428885 # number of Writeback hits
|
||||
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.l2c.avg_refs 2.205900 # Average number of references to valid blocks.
|
||||
system.l2c.avg_refs 2.205901 # Average number of references to valid blocks.
|
||||
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.demand_accesses 2658871 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses 2658872 # number of demand (read+write) accesses
|
||||
system.l2c.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
||||
system.l2c.demand_hits 1717827 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits 1717828 # number of demand (read+write) hits
|
||||
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_rate 0.353926 # miss rate for demand accesses
|
||||
system.l2c.demand_misses 941044 # number of demand (read+write) misses
|
||||
|
|
@ -324,11 +324,11 @@ system.l2c.demand_mshr_misses 0 # nu
|
|||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_accesses 3087756 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses 3087757 # number of overall (read+write) accesses
|
||||
system.l2c.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.l2c.overall_hits 2146712 # number of overall hits
|
||||
system.l2c.overall_hits 2146713 # number of overall hits
|
||||
system.l2c.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.l2c.overall_miss_rate 0.304766 # miss rate for overall accesses
|
||||
system.l2c.overall_misses 941044 # number of overall misses
|
||||
|
|
@ -351,7 +351,7 @@ system.l2c.replacements 992432 # nu
|
|||
system.l2c.sampled_refs 1057820 # Sample count of references to valid blocks.
|
||||
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.l2c.tagsinuse 65517.661064 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2333445 # Total number of references to valid blocks.
|
||||
system.l2c.total_refs 2333446 # Total number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.writebacks 0 # number of writebacks
|
||||
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
|
||||
|
|
|
|||
Loading…
Reference in a new issue