ARM: Implement the Instruction Set Attribute Registers (ISAR).

The ISAR registers describe which features the processor supports.
Transcribe the values listed in section B5.2.5 of the ARM ARM
into the registers as read-only values
This commit is contained in:
Ali Saidi 2011-03-17 19:20:20 -05:00
parent 5480ec798a
commit 4c7a7796ad
2 changed files with 18 additions and 9 deletions

View file

@ -143,6 +143,16 @@ ISA::clear()
miscRegs[MISCREG_CPACR] = 0; miscRegs[MISCREG_CPACR] = 0;
miscRegs[MISCREG_FPSID] = 0x410430A0; miscRegs[MISCREG_FPSID] = 0x410430A0;
// See section B4.1.84 of ARM ARM
// All values are latest for ARMv7-A profile
miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
//XXX We need to initialize the rest of the state. //XXX We need to initialize the rest of the state.
} }

View file

@ -165,6 +165,12 @@ namespace ArmISA
MISCREG_PMUSERENR, MISCREG_PMUSERENR,
MISCREG_PMINTENSET, MISCREG_PMINTENSET,
MISCREG_PMINTENCLR, MISCREG_PMINTENCLR,
MISCREG_ID_ISAR0,
MISCREG_ID_ISAR1,
MISCREG_ID_ISAR2,
MISCREG_ID_ISAR3,
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
MISCREG_CP15_UNIMP_START, MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
MISCREG_ID_PFR1, MISCREG_ID_PFR1,
@ -173,12 +179,6 @@ namespace ArmISA
MISCREG_ID_MMFR1, MISCREG_ID_MMFR1,
MISCREG_ID_MMFR2, MISCREG_ID_MMFR2,
MISCREG_ID_MMFR3, MISCREG_ID_MMFR3,
MISCREG_ID_ISAR0,
MISCREG_ID_ISAR1,
MISCREG_ID_ISAR2,
MISCREG_ID_ISAR3,
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
MISCREG_AIDR, MISCREG_AIDR,
MISCREG_ADFSR, MISCREG_ADFSR,
MISCREG_AIFSR, MISCREG_AIFSR,
@ -233,13 +233,12 @@ namespace ArmISA
"pmswinc", "pmselr", "pmceid0", "pmswinc", "pmselr", "pmceid0",
"pmceid1", "pmc_other", "pmxevcntr", "pmceid1", "pmc_other", "pmxevcntr",
"pmuserenr", "pmintenset", "pmintenclr", "pmuserenr", "pmintenset", "pmintenclr",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
// Unimplemented below // Unimplemented below
"tcmtr", "tcmtr",
"id_pfr1", "id_dfr0", "id_afr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr1", "id_mmfr2", "id_mmfr3", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", "aidr", "adfsr", "aifsr",
"aidr",
"adfsr", "aifsr",
"dcimvac", "dcisw", "mccsw", "dcimvac", "dcisw", "mccsw",
"dccmvau", "dccmvau",
"nsacr", "nsacr",