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stats: Update MinorCPU regressions after accounting fix

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This commit is contained in:
Andreas Hansson 2015-05-26 03:21:39 -04:00
parent cea1d14a93
commit 4bc7dfb697
21 changed files with 13400 additions and 13419 deletions
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tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
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tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.061594 # Number of seconds simulated
sim_ticks 61594138500 # Number of ticks simulated
final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.061296 # Number of seconds simulated
sim_ticks 61295518500 # Number of ticks simulated
final_tick 61295518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 265976 # Simulator instruction rate (inst/s)
host_op_rate 267300 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 180817037 # Simulator tick rate (ticks/s)
host_inst_rate 265745 # Simulator instruction rate (inst/s)
host_op_rate 267069 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 179784475 # Simulator tick rate (ticks/s)
host_mem_usage 446692 # Number of bytes of host memory used
host_seconds 340.64 # Real time elapsed on the host
host_seconds 340.94 # Real time elapsed on the host
sim_insts 90602850 # Number of instructions simulated
sim_ops 91054081 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49536 # Nu
system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 804232 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 15378087 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16182319 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 804232 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 804232 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 804232 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 15378087 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 16182319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 808150 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 15453006 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16261156 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 808150 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 808150 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 808150 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 15453006 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 16261156 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15574 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 61594044000 # Total gap between requests
system.physmem.totGap 61295424000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 646.025974 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 441.784218 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 399.527843 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 247 16.04% 16.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 180 11.69% 27.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 88 5.71% 33.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 68 4.42% 37.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 78 5.06% 42.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 95 6.17% 49.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 49 3.18% 52.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 35 2.27% 54.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 700 45.45% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation
system.physmem.totQLat 76216750 # Total ticks spent queuing
system.physmem.totMemAccLat 368229250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 651.693517 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 447.533847 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 399.021267 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 238 15.59% 15.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 181 11.85% 27.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 84 5.50% 32.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 68 4.45% 37.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 71 4.65% 42.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 87 5.70% 47.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 52 3.41% 51.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 56 3.67% 54.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 690 45.19% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation
system.physmem.totQLat 75432750 # Total ticks spent queuing
system.physmem.totMemAccLat 367445250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
system.physmem.avgQLat 4893.85 # Average queueing delay per DRAM burst
system.physmem.avgQLat 4843.51 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 23643.85 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgMemAccLat 23593.51 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 16.26 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s
system.physmem.avgRdBWSys 16.26 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.13 # Data bus utilization in percentage
@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 14024 # Number of row buffer hits during reads
system.physmem.readRowHits 14042 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads
system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 3954927.70 # Average gap between requests
system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6327720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3452625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 63655800 # Energy for read commands per rank (pJ)
system.physmem.avgGap 3935753.44 # Average gap between requests
system.physmem.pageHitRate 90.16 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2561139675 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 34707076500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 41364361920 # Total energy per rank (pJ)
system.physmem_0.averagePower 671.614039 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 57728641000 # Time in different power states
system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states
system.physmem_0.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2494246185 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 34588236750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 41159350290 # Total energy per rank (pJ)
system.physmem_0.averagePower 671.511167 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 57530940500 # Time in different power states
system.physmem_0.memoryStateTime::REF 2046720000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1804854500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1716061500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 5299560 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2570808870 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 34698594750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 41357767005 # Total energy per rank (pJ)
system.physmem_1.averagePower 671.506960 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 57715756250 # Time in different power states
system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states
system.physmem_1.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2575259145 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 34517172750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 41161458375 # Total energy per rank (pJ)
system.physmem_1.averagePower 671.545560 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 57412676250 # Time in different power states
system.physmem_1.memoryStateTime::REF 2046720000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1818578750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1834237500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 20791997 # Number of BP lookups
system.cpu.branchPred.condPredicted 17093861 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 766355 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8982065 # Number of BTB lookups
system.cpu.branchPred.BTBHits 8866075 # Number of BTB hits
system.cpu.branchPred.lookups 20766617 # Number of BP lookups
system.cpu.branchPred.condPredicted 17069689 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 765538 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8958723 # Number of BTB lookups
system.cpu.branchPred.BTBHits 8857106 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 98.708649 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 62635 # Number of times the RAS was used to get a target.
system.cpu.branchPred.BTBHitPct 98.865720 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 62714 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@ -377,67 +377,67 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 123188277 # number of cpu cycles simulated
system.cpu.numCycles 122591037 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602850 # Number of instructions committed
system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2070154 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 2197459 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.359651 # CPI: cycles per instruction
system.cpu.ipc 0.735483 # IPC: instructions per cycle
system.cpu.tickCycles 109833647 # Number of cycles that the object actually ticked
system.cpu.idleCycles 13354630 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 946088 # number of replacements
system.cpu.dcache.tags.tagsinuse 3616.165317 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26267708 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 950184 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.644865 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 20660513250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.165317 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.882853 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.882853 # Average percentage of cache occupancy
system.cpu.cpi 1.353059 # CPI: cycles per instruction
system.cpu.ipc 0.739066 # IPC: instructions per cycle
system.cpu.tickCycles 109335027 # Number of cycles that the object actually ticked
system.cpu.idleCycles 13256010 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 946108 # number of replacements
system.cpu.dcache.tags.tagsinuse 3616.919530 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26267744 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 950204 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.644321 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 20526719250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.919530 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.883037 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.883037 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55463792 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55463792 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21598607 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21598607 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660819 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4660819 # number of WriteReq hits
system.cpu.dcache.tags.tag_accesses 55463926 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55463926 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21598657 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21598657 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660805 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4660805 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26259426 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26259426 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26259934 # number of overall hits
system.cpu.dcache.overall_hits::total 26259934 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 914930 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 914930 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 74162 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 74162 # number of WriteReq misses
system.cpu.dcache.demand_hits::cpu.data 26259462 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26259462 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26259970 # number of overall hits
system.cpu.dcache.overall_hits::total 26259970 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 914937 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 914937 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 74176 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 74176 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 989092 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 989092 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 989096 # number of overall misses
system.cpu.dcache.overall_misses::total 989096 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918229494 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11918229494 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2567046500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2567046500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14485275994 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14485275994 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14485275994 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14485275994 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22513537 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22513537 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_misses::cpu.data 989113 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 989113 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 989117 # number of overall misses
system.cpu.dcache.overall_misses::total 989117 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11917910744 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11917910744 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566961500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2566961500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14484872244 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14484872244 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14484872244 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14484872244 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22513594 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22513594 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
@ -446,28 +446,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27248518 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27248518 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27249030 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27249030 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 27248575 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27248575 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27249087 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27249087 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015663 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015663 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015666 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015666 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.036298 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036298 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.383979 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.383979 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34614.040883 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34614.040883 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14645.023915 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14645.023915 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.964689 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14644.964689 # average overall miss latency
system.cpu.dcache.demand_miss_rate::cpu.data 0.036300 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036300 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.935932 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.935932 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34606.361896 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34606.361896 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.304790 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14644.304790 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.245569 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14644.245569 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -476,109 +476,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 943266 # number of writebacks
system.cpu.dcache.writebacks::total 943266 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11513 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 11513 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27398 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 27398 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 38911 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 38911 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 38911 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 38911 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903417 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 903417 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses
system.cpu.dcache.writebacks::writebacks 943289 # number of writebacks
system.cpu.dcache.writebacks::total 943289 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11503 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 11503 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27409 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 27409 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 38912 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 38912 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 38912 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 38912 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903434 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 903434 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46767 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 950181 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 950181 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 950184 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 950184 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412913006 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412913006 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464006500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464006500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_misses::cpu.data 950201 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 950201 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 950204 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 950204 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412555256 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412555256 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464079000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464079000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876919506 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11876919506 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877075006 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11877075006 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876634256 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11876634256 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11876789756 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11876789756 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034870 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034870 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.142419 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.142419 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31306.271919 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31306.271919 # average WriteReq mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11525.529542 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11525.529542 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31305.813929 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31305.813929 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.639022 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.639022 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.763210 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.763210 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.075728 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.075728 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.199915 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.199915 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 4 # number of replacements
system.cpu.icache.tags.tagsinuse 690.351832 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27857021 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 690.424253 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27792420 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 34734.440150 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 34653.890274 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 690.351832 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.337086 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.337086 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 690.424253 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.337121 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.337121 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 55716448 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55716448 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 27857021 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27857021 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27857021 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27857021 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27857021 # number of overall hits
system.cpu.icache.overall_hits::total 27857021 # number of overall hits
system.cpu.icache.tags.tag_accesses 55587246 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55587246 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 27792420 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27792420 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27792420 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27792420 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27792420 # number of overall hits
system.cpu.icache.overall_hits::total 27792420 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
system.cpu.icache.overall_misses::total 802 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60516997 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 60516997 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 60516997 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 60516997 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 60516997 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 60516997 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27857823 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27857823 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27857823 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27857823 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27857823 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27857823 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60382998 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 60382998 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 60382998 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 60382998 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 60382998 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 60382998 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27793222 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27793222 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27793222 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27793222 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27793222 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27793222 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75457.602244 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 75457.602244 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 75457.602244 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 75457.602244 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75290.521197 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 75290.521197 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 75290.521197 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 75290.521197 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -593,117 +593,117 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58977003 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 58977003 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58977003 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 58977003 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58977003 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 58977003 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58841002 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 58841002 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58841002 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 58841002 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58841002 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 58841002 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73537.410224 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73537.410224 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73367.832918 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73367.832918 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73367.832918 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 73367.832918 # average overall mshr miss latency
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.450791 # Average occupied blocks per requestor
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 904222 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 904222 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 943266 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadReq 904239 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 943289 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843634 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2845238 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843697 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2845301 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121180800 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183552 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 121234880 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 1894295 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1894252 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1894295 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 1894295 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1890436500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1371497 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 1372498 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1428656494 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 1428685244 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
system.membus.trans_dist::ReadReq 1030 # Transaction distribution
system.membus.trans_dist::ReadResp 1030 # Transaction distribution
@ -814,9 +814,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15574 # Request fanout histogram
system.membus.reqLayer0.occupancy 21629000 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 21690500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 82142750 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 82133750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

1074
tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
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1047
tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
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tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
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@ -1,42 +1,42 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.226866 # Number of seconds simulated
sim_ticks 226865901500 # Number of ticks simulated
final_tick 226865901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.226051 # Number of seconds simulated
sim_ticks 226051212500 # Number of ticks simulated
final_tick 226051212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 324605 # Simulator instruction rate (inst/s)
host_op_rate 324605 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 184721178 # Simulator tick rate (ticks/s)
host_mem_usage 301676 # Number of bytes of host memory used
host_seconds 1228.15 # Real time elapsed on the host
host_inst_rate 313509 # Simulator instruction rate (inst/s)
host_op_rate 313509 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 177766322 # Simulator tick rate (ticks/s)
host_mem_usage 302576 # Number of bytes of host memory used
host_seconds 1271.62 # Real time elapsed on the host
sim_insts 398664665 # Number of instructions simulated
sim_ops 398664665 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 249344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory
system.physmem.bytes_read::total 503872 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory
system.physmem.bytes_read::total 503936 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 249344 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 249344 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3896 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1098799 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1122214 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2221012 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1098799 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1098799 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1098799 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1122214 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2221012 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7873 # Number of read requests accepted
system.physmem.num_reads::total 7874 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1103042 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1126258 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2229300 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1103042 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1103042 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1103042 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1126258 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2229300 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7874 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.readBursts 7874 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 503872 # Total number of bytes read from DRAM
system.physmem.bytesReadDRAM 503936 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 503872 # Total read bytes from the system interface side
system.physmem.bytesReadSys 503936 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@ -49,7 +49,7 @@ system.physmem.perBankRdBursts::4 475 # Pe
system.physmem.perBankRdBursts::5 478 # Per bank write bursts
system.physmem.perBankRdBursts::6 563 # Per bank write bursts
system.physmem.perBankRdBursts::7 560 # Per bank write bursts
system.physmem.perBankRdBursts::8 469 # Per bank write bursts
system.physmem.perBankRdBursts::8 470 # Per bank write bursts
system.physmem.perBankRdBursts::9 437 # Per bank write bursts
system.physmem.perBankRdBursts::10 354 # Per bank write bursts
system.physmem.perBankRdBursts::11 323 # Per bank write bursts
@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 226865813000 # Total gap between requests
system.physmem.totGap 226051111000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 7873 # Read request sizes (log2)
system.physmem.readPktSize::6 7874 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 6818 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 974 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 82 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1561 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 321.065983 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 192.383190 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 328.308816 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 550 35.23% 35.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 344 22.04% 57.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 200 12.81% 70.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 103 6.60% 76.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 61 3.91% 80.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 52 3.33% 83.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 34 2.18% 86.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 30 1.92% 88.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 187 11.98% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1561 # Bytes accessed per row activation
system.physmem.totQLat 54380250 # Total ticks spent queuing
system.physmem.totMemAccLat 201999000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6907.18 # Average queueing delay per DRAM burst
system.physmem.bytesPerActivate::samples 1564 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 321.964194 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 193.457187 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 327.645688 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 541 34.59% 34.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 357 22.83% 57.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 194 12.40% 69.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 101 6.46% 76.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 65 4.16% 80.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 55 3.52% 83.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 35 2.24% 86.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 34 2.17% 88.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 182 11.64% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1564 # Bytes accessed per row activation
system.physmem.totQLat 54215500 # Total ticks spent queuing
system.physmem.totMemAccLat 201853000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 39370000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6885.38 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25657.18 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgMemAccLat 25635.38 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.23 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.02 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 6303 # Number of row buffer hits during reads
system.physmem.readRowHits 6308 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads
system.physmem.readRowHitRate 80.11 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 28815675.47 # Average gap between requests
system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6902280 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3766125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 34164000 # Energy for read commands per rank (pJ)
system.physmem.avgGap 28708548.51 # Average gap between requests
system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6872040 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3749625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 5855918085 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 130979493750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 151697648400 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.682686 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 217896983750 # Time in different power states
system.physmem_0.memoryStateTime::REF 7575360000 # Time in different power states
system.physmem_0.refreshEnergy 14764513920 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 5850636750 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 130498264500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 151158364635 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.692398 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 217093450250 # Time in different power states
system.physmem_0.memoryStateTime::REF 7548320000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1391017250 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1408913500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 26910000 # Energy for read commands per rank (pJ)
system.physmem_1.actEnergy 4951800 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2701875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 27042600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 5585732100 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 131216499000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 151654105455 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.490749 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 218290626750 # Time in different power states
system.physmem_1.memoryStateTime::REF 7575360000 # Time in different power states
system.physmem_1.refreshEnergy 14764513920 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 5592917520 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 130724334000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 151116461715 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.507029 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 217471574500 # Time in different power states
system.physmem_1.memoryStateTime::REF 7548320000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 994701750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1030789250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 46273750 # Number of BP lookups
system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 25595406 # Number of BTB lookups
system.cpu.branchPred.BTBHits 21359943 # Number of BTB hits
system.cpu.branchPred.lookups 46270925 # Number of BP lookups
system.cpu.branchPred.condPredicted 26727379 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1017826 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 25620092 # Number of BTB lookups
system.cpu.branchPred.BTBHits 21360644 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 83.452253 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 8341648 # Number of times the RAS was used to get a target.
system.cpu.branchPred.BTBHitPct 83.374580 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 8341960 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 95585469 # DTB read hits
system.cpu.dtb.read_misses 115 # DTB read misses
system.cpu.dtb.read_hits 95612151 # DTB read hits
system.cpu.dtb.read_misses 116 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 95585584 # DTB read accesses
system.cpu.dtb.write_hits 73606437 # DTB write hits
system.cpu.dtb.write_misses 857 # DTB write misses
system.cpu.dtb.read_accesses 95612267 # DTB read accesses
system.cpu.dtb.write_hits 73605971 # DTB write hits
system.cpu.dtb.write_misses 858 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73607294 # DTB write accesses
system.cpu.dtb.data_hits 169191906 # DTB hits
system.cpu.dtb.data_misses 972 # DTB misses
system.cpu.dtb.write_accesses 73606829 # DTB write accesses
system.cpu.dtb.data_hits 169218122 # DTB hits
system.cpu.dtb.data_misses 974 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 169192878 # DTB accesses
system.cpu.itb.fetch_hits 98781212 # ITB hits
system.cpu.itb.fetch_misses 1236 # ITB misses
system.cpu.dtb.data_accesses 169219096 # DTB accesses
system.cpu.itb.fetch_hits 98739643 # ITB hits
system.cpu.itb.fetch_misses 1232 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 98782448 # ITB accesses
system.cpu.itb.fetch_accesses 98740875 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -293,67 +293,67 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 453731803 # number of cpu cycles simulated
system.cpu.numCycles 452102425 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664665 # Number of instructions committed
system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed
system.cpu.discardedOps 4467789 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 4488157 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.138129 # CPI: cycles per instruction
system.cpu.ipc 0.878635 # IPC: instructions per cycle
system.cpu.tickCycles 450174138 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3557665 # Total number of cycles that the object has spent stopped
system.cpu.cpi 1.134042 # CPI: cycles per instruction
system.cpu.ipc 0.881802 # IPC: instructions per cycle
system.cpu.tickCycles 448265843 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3836582 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 771 # number of replacements
system.cpu.dcache.tags.tagsinuse 3291.677539 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168028622 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 3291.681680 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168032891 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40343.006483 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40344.031453 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.677539 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.803632 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.803632 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.681680 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.803633 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.803633 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 94513824 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94513824 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73514798 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73514798 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 168028622 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168028622 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168028622 # number of overall hits
system.cpu.dcache.overall_hits::total 168028622 # number of overall hits
system.cpu.dcache.tags.tag_accesses 336084169 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336084169 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 94518092 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94518092 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73514799 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 168032891 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168032891 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168032891 # number of overall hits
system.cpu.dcache.overall_hits::total 168032891 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5932 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5932 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 7112 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7112 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7112 # number of overall misses
system.cpu.dcache.overall_misses::total 7112 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88706750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 88706750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 435640500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 435640500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 524347250 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 524347250 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 524347250 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 524347250 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94515004 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_misses::cpu.data 5931 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5931 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 7111 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7111 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7111 # number of overall misses
system.cpu.dcache.overall_misses::total 7111 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88098000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 88098000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 432683750 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 432683750 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 520781750 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 520781750 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 520781750 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 520781750 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94519272 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94519272 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168035734 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168035734 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168035734 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168035734 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 168040002 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168040002 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168040002 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168040002 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000012 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses
@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75175.211864 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 75175.211864 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73439.059339 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73439.059339 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73727.116142 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73727.116142 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74659.322034 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 74659.322034 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72952.916877 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 72952.916877 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73236.077907 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73236.077907 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73236.077907 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73236.077907 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -382,12 +382,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu
system.cpu.dcache.writebacks::total 654 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2736 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2736 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2947 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2947 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2947 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2947 # number of overall MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2735 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2735 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2946 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2946 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2946 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2946 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses
@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70790750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 70790750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 240139250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 240139250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310930000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 310930000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310930000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 310930000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 69978250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 69978250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 238524000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 238524000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308502250 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 308502250 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308502250 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 308502250 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73055.469556 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73055.469556 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75137.437422 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75137.437422 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72216.976264 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72216.976264 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74632.040050 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74632.040050 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74070.168067 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74070.168067 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74070.168067 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74070.168067 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 3196 # number of replacements
system.cpu.icache.tags.tagsinuse 1918.668562 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 98776038 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 5174 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 19090.846154 # Average number of references to valid blocks.
system.cpu.icache.tags.replacements 3197 # number of replacements
system.cpu.icache.tags.tagsinuse 1918.668517 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 98734468 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 5175 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 19079.124251 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668562 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668517 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.936850 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.936850 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 197567598 # Number of tag accesses
system.cpu.icache.tags.data_accesses 197567598 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 98776038 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 98776038 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 98776038 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 98776038 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 98776038 # number of overall hits
system.cpu.icache.overall_hits::total 98776038 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5174 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5174 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5174 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5174 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5174 # number of overall misses
system.cpu.icache.overall_misses::total 5174 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 320697250 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 320697250 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 320697250 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 320697250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 320697250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 320697250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 98781212 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 98781212 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 98781212 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 98781212 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 98781212 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 98781212 # number of overall (read+write) accesses
system.cpu.icache.tags.tag_accesses 197484461 # Number of tag accesses
system.cpu.icache.tags.data_accesses 197484461 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 98734468 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 98734468 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 98734468 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 98734468 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 98734468 # number of overall hits
system.cpu.icache.overall_hits::total 98734468 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5175 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5175 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5175 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5175 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5175 # number of overall misses
system.cpu.icache.overall_misses::total 5175 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 322926000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 322926000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 322926000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 322926000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 322926000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 322926000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 98739643 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.demand_mshr_miss_latency::total 498705750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 246135500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 252570250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 498705750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771247 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for overall accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.843041 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62625.609756 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68716.706302 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.242399 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62865.556264 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62865.556264 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843041 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63176.463039 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67750.594530 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63988.547604 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62350.015939 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62350.015939 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63176.463039 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63491.767220 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63335.756922 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63176.463039 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63491.767220 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63335.756922 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadReq 6142 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 6142 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10348 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10350 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 19332 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331136 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 19334 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331200 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 639552 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 639616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 9993 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 9994 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 9993 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 9994 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 9994 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5651000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 8584250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 8587500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 7034000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 7035750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadReq 4736 # Transaction distribution
system.membus.trans_dist::ReadResp 4736 # Transaction distribution
system.membus.trans_dist::ReadReq 4737 # Transaction distribution
system.membus.trans_dist::ReadResp 4737 # Transaction distribution
system.membus.trans_dist::ReadExReq 3137 # Transaction distribution
system.membus.trans_dist::ReadExResp 3137 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15746 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15746 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503872 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 503872 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15748 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15748 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503936 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 503936 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 7873 # Request fanout histogram
system.membus.snoop_fanout::samples 7874 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 7873 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 7874 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7873 # Request fanout histogram
system.membus.reqLayer0.occupancy 9289000 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 7874 # Request fanout histogram
system.membus.reqLayer0.occupancy 9179500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 41806250 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 41811750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

696
tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
View file

@ -1,42 +1,42 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.216744 # Number of seconds simulated
sim_ticks 216744260000 # Number of ticks simulated
final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.216140 # Number of seconds simulated
sim_ticks 216139917000 # Number of ticks simulated
final_tick 216139917000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 172626 # Simulator instruction rate (inst/s)
host_op_rate 207257 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 137034779 # Simulator tick rate (ticks/s)
host_mem_usage 322768 # Number of bytes of host memory used
host_seconds 1581.67 # Real time elapsed on the host
host_inst_rate 173188 # Simulator instruction rate (inst/s)
host_op_rate 207931 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 137097336 # Simulator tick rate (ticks/s)
host_mem_usage 323040 # Number of bytes of host memory used
host_seconds 1576.54 # Real time elapsed on the host
sim_insts 273037857 # Number of instructions simulated
sim_ops 327812214 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 218944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory
system.physmem.bytes_read::total 485312 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 218944 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 218944 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3421 # Number of read requests responded to by this memory
system.physmem.bytes_read::total 485504 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1010149 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1228951 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2239100 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1010149 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1010149 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1010149 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1228951 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2239100 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7583 # Number of read requests accepted
system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1013862 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1232387 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2246249 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1013862 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1013862 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1013862 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1232387 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2246249 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7586 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM
system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side
system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@ -46,7 +46,7 @@ system.physmem.perBankRdBursts::1 843 # Pe
system.physmem.perBankRdBursts::2 628 # Per bank write bursts
system.physmem.perBankRdBursts::3 541 # Per bank write bursts
system.physmem.perBankRdBursts::4 466 # Per bank write bursts
system.physmem.perBankRdBursts::5 348 # Per bank write bursts
system.physmem.perBankRdBursts::5 349 # Per bank write bursts
system.physmem.perBankRdBursts::6 173 # Per bank write bursts
system.physmem.perBankRdBursts::7 228 # Per bank write bursts
system.physmem.perBankRdBursts::8 209 # Per bank write bursts
@ -55,8 +55,8 @@ system.physmem.perBankRdBursts::10 342 # Pe
system.physmem.perBankRdBursts::11 428 # Per bank write bursts
system.physmem.perBankRdBursts::12 553 # Per bank write bursts
system.physmem.perBankRdBursts::13 706 # Per bank write bursts
system.physmem.perBankRdBursts::14 637 # Per bank write bursts
system.physmem.perBankRdBursts::15 540 # Per bank write bursts
system.physmem.perBankRdBursts::14 638 # Per bank write bursts
system.physmem.perBankRdBursts::15 541 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 216744023500 # Total gap between requests
system.physmem.totGap 216139680500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 7583 # Read request sizes (log2)
system.physmem.readPktSize::6 7586 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 6624 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 901 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 318.314681 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 188.160813 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 331.826555 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 551 36.27% 36.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 356 23.44% 59.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 165 10.86% 70.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 80 5.27% 75.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 68 4.48% 80.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 50 3.29% 83.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 36 2.37% 85.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 26 1.71% 87.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 187 12.31% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation
system.physmem.totQLat 54921500 # Total ticks spent queuing
system.physmem.totMemAccLat 197102750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7242.71 # Average queueing delay per DRAM burst
system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 318.319107 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 188.795582 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 330.243204 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 551 36.18% 36.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 346 22.72% 58.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 176 11.56% 70.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 81 5.32% 75.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 75 4.92% 80.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 50 3.28% 83.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 32 2.10% 86.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 28 1.84% 87.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 184 12.08% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation
system.physmem.totQLat 53007250 # Total ticks spent queuing
system.physmem.totMemAccLat 195244750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6987.51 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25992.71 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgMemAccLat 25737.51 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 6057 # Number of row buffer hits during reads
system.physmem.readRowHits 6060 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 28582885.86 # Average gap between requests
system.physmem.avgGap 28491916.75 # Average gap between requests
system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ)
system.physmem_0.actEnergy 5004720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2730750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 30022200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 5639665500 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 125095914000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 144929531385 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.684406 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 208108813000 # Time in different power states
system.physmem_0.memoryStateTime::REF 7237360000 # Time in different power states
system.physmem_0.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 5648540400 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 124728404250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 144531819360 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.699173 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 207494790250 # Time in different power states
system.physmem_0.memoryStateTime::REF 7217340000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1394961500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1426657250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 6433560 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3510375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 28984800 # Energy for read commands per rank (pJ)
system.physmem_1.actEnergy 6509160 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3551625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 29062800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 5856004440 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 124906143000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 144957352335 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.812768 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 207790968250 # Time in different power states
system.physmem_1.memoryStateTime::REF 7237360000 # Time in different power states
system.physmem_1.refreshEnergy 14117117040 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 5781551040 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 124611728250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 144549519915 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.781068 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 207298156250 # Time in different power states
system.physmem_1.memoryStateTime::REF 7217340000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1713539250 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1623563250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 33185861 # Number of BP lookups
system.cpu.branchPred.condPredicted 17151464 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1557357 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 17401044 # Number of BTB lookups
system.cpu.branchPred.BTBHits 15621725 # Number of BTB hits
system.cpu.branchPred.lookups 33139216 # Number of BP lookups
system.cpu.branchPred.condPredicted 17107199 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1560655 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 17520877 # Number of BTB lookups
system.cpu.branchPred.BTBHits 15610870 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 89.774642 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 6610647 # Number of times the RAS was used to get a target.
system.cpu.branchPred.BTBHitPct 89.098679 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 6611023 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@ -377,81 +377,81 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 433488520 # number of cpu cycles simulated
system.cpu.numCycles 432279834 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 273037857 # Number of instructions committed
system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed
system.cpu.discardedOps 4013329 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 4207498 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.587650 # CPI: cycles per instruction
system.cpu.ipc 0.629862 # IPC: instructions per cycle
system.cpu.tickCycles 429966989 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3521531 # Total number of cycles that the object has spent stopped
system.cpu.cpi 1.583223 # CPI: cycles per instruction
system.cpu.ipc 0.631623 # IPC: instructions per cycle
system.cpu.tickCycles 428628441 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3651393 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1354 # number of replacements
system.cpu.dcache.tags.tagsinuse 3085.753926 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168769445 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 3085.737950 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168771151 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37412.867435 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37413.245622 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.753926 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.753358 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.753358 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.737950 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.753354 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.753354 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 337557971 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 337557971 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86636657 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86636657 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 63541 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 63541 # number of SoftPFReq hits
system.cpu.dcache.tags.tag_accesses 337561379 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 337561379 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86638362 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86638362 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82047459 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82047459 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168684114 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168684114 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168747655 # number of overall hits
system.cpu.dcache.overall_hits::total 168747655 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 168685821 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168685821 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168749361 # number of overall hits
system.cpu.dcache.overall_hits::total 168749361 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5218 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5218 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 7279 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7279 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7285 # number of overall misses
system.cpu.dcache.overall_misses::total 7285 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 137443456 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 137443456 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 400907250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 400907250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 538350706 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 538350706 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 538350706 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 538350706 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86638716 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86638716 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_misses::cpu.data 7277 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7277 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7283 # number of overall misses
system.cpu.dcache.overall_misses::total 7283 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 136967456 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 136967456 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 400451000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 400451000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 537418456 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 537418456 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 537418456 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 537418456 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86640421 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86640421 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 63547 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 63547 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168691393 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168691393 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168754940 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168754940 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 168693098 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168693098 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168756644 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168756644 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66752.528412 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66752.528412 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76802.155172 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 76802.155172 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73959.432065 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73959.432065 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73898.518325 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73898.518325 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66521.348227 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66521.348227 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76744.154849 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 76744.154849 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73851.649856 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73851.649856 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73790.808183 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73790.808183 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu
system.cpu.dcache.writebacks::total 1010 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2772 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2772 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2772 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2772 # number of overall MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2348 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2348 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2770 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2770 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2770 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2770 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses
@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4507
system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109995542 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109995542 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220772750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 220772750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108888792 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 108888792 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220256750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 220256750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330768292 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 330768292 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 331089042 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 331089042 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329145542 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 329145542 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329466292 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 329466292 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67193.367135 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67193.367135 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76924.303136 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76924.303136 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66517.282834 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66517.282834 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76744.512195 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76744.512195 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73389.902818 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73389.902818 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73395.930392 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73395.930392 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73029.851786 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73029.851786 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73036.198626 # average overall mshr miss latency
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system.cpu.icache.tags.sampled_refs 38865 # Sample count of references to valid blocks.
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system.cpu.icache.tags.occ_blocks::cpu.inst 1924.841098 # Average occupied blocks per requestor
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system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 18734.375753 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18734.375753 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18734.375753 # average overall miss latency
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@ -591,123 +591,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17197.068183 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088149 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.822669 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.117861 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.117906 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088095 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088149 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.175871 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088095 # miss rate for overall accesses
system.cpu.l2cache.demand_miss_rate::total 0.175900 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088149 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.175871 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75265.483494 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78229.814815 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76103.917871 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76278.819201 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76278.819201 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75265.483494 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76169.365412 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75265.483494 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76169.365412 # average overall miss latency
system.cpu.l2cache.overall_miss_rate::total 0.175900 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75132.589025 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77410 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75776.329564 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76098.020322 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76098.020322 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75132.589025 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76519.326832 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75896.657929 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75132.589025 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76519.326832 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75896.657929 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -725,102 +725,102 @@ system.cpu.l2cache.demand_mshr_hits::total 44 #
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3421 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3424 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1308 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4729 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4732 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3421 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3421 # number of overall MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214664750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86513250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301178000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181997750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181997750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214664750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 268511000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 483175750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214664750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 268511000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 483175750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214398750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85427750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 299826500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181482250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181482250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214398750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266910000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 481308750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214398750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266910000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 481308750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116774 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116819 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.174856 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for overall accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.174885 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088098 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.174856 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62749.123063 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66141.628440 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63687.460351 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63769.358795 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63769.358795 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::total 0.174885 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62616.457360 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65311.735474 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63361.475063 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63588.735109 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63588.735109 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62616.457360 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64130.225853 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63446.974690 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 40497 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 40496 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadReq 40507 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 40506 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77711 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77731 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 87743 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486720 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 87763 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487360 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2840704 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 44387 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 44377 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 44387 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 44387 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 23203500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 59005248 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 59023248 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 7574708 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadReq 4729 # Transaction distribution
system.membus.trans_dist::ReadResp 4729 # Transaction distribution
system.membus.trans_dist::ReadReq 4732 # Transaction distribution
system.membus.trans_dist::ReadResp 4732 # Transaction distribution
system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
system.membus.trans_dist::ReadExResp 2854 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 7583 # Request fanout histogram
system.membus.snoop_fanout::samples 7586 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7583 # Request fanout histogram
system.membus.reqLayer0.occupancy 8950500 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 7586 # Request fanout histogram
system.membus.reqLayer0.occupancy 8848500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 40258250 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 40266750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.052202 # Number of seconds simulated
sim_ticks 52201532500 # Number of ticks simulated
final_tick 52201532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.052048 # Number of seconds simulated
sim_ticks 52048460500 # Number of ticks simulated
final_tick 52048460500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 357575 # Simulator instruction rate (inst/s)
host_op_rate 357575 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 203104604 # Simulator tick rate (ticks/s)
host_mem_usage 300132 # Number of bytes of host memory used
host_seconds 257.02 # Real time elapsed on the host
host_inst_rate 350030 # Simulator instruction rate (inst/s)
host_op_rate 350030 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 198236020 # Simulator tick rate (ticks/s)
host_mem_usage 300292 # Number of bytes of host memory used
host_seconds 262.56 # Real time elapsed on the host
sim_insts 91903089 # Number of instructions simulated
sim_ops 91903089 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 202688 # Nu
system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 3882798 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2637164 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6519962 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3882798 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3882798 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 3882798 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2637164 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6519962 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 3894217 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2644920 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6539137 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3894217 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3894217 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 3894217 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2644920 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6539137 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 5318 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 5318 # Number of DRAM read bursts, including those serviced by the write queue
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 52201444000 # Total gap between requests
system.physmem.totGap 52048372000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 4919 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 4920 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 983 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 345.912513 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 209.979760 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 330.521018 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 325 33.06% 33.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 203 20.65% 53.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 90 9.16% 62.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 89 9.05% 71.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 77 7.83% 79.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 32 3.26% 83.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 28 2.85% 85.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 23 2.34% 88.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 116 11.80% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 983 # Bytes accessed per row activation
system.physmem.totQLat 33415750 # Total ticks spent queuing
system.physmem.totMemAccLat 133128250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.bytesPerActivate::samples 976 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 347.672131 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 215.149483 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 325.651264 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 303 31.05% 31.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 210 21.52% 52.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 100 10.25% 62.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 92 9.43% 72.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 71 7.27% 79.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 39 4.00% 83.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 30 3.07% 86.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 19 1.95% 88.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 112 11.48% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 976 # Bytes accessed per row activation
system.physmem.totQLat 32254250 # Total ticks spent queuing
system.physmem.totMemAccLat 131966750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6283.52 # Average queueing delay per DRAM burst
system.physmem.avgQLat 6065.11 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25033.52 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 6.52 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgMemAccLat 24815.11 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 6.54 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 6.52 # Average system read bandwidth in MiByte/s
system.physmem.avgRdBWSys 6.54 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.05 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 4331 # Number of row buffer hits during reads
system.physmem.readRowHits 4336 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads
system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 9815991.73 # Average gap between requests
system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3500280 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1909875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 19975800 # Energy for read commands per rank (pJ)
system.physmem.avgGap 9787207.97 # Average gap between requests
system.physmem.pageHitRate 81.53 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3515400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1918125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 19851000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1770933285 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29766117750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34971823230 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.967540 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49515286750 # Time in different power states
system.physmem_0.memoryStateTime::REF 1743040000 # Time in different power states
system.physmem_0.refreshEnergy 3399215040 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1773582930 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29670358500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34868440995 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.985765 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49355972750 # Time in different power states
system.physmem_0.memoryStateTime::REF 1737840000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 940967000 # Time in different power states
system.physmem_0.memoryStateTime::ACT 949756000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3908520 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2132625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 21301800 # Energy for read commands per rank (pJ)
system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1804216725 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29736921750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34977867660 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.083336 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49466733750 # Time in different power states
system.physmem_1.memoryStateTime::REF 1743040000 # Time in different power states
system.physmem_1.refreshEnergy 3399215040 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1774901340 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29669193750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34870438740 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.024328 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49353927250 # Time in different power states
system.physmem_1.memoryStateTime::REF 1737840000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 989849750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 951967750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 11476351 # Number of BP lookups
system.cpu.branchPred.condPredicted 8235351 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 785844 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 6672655 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5371510 # Number of BTB hits
system.cpu.branchPred.lookups 11467285 # Number of BP lookups
system.cpu.branchPred.condPredicted 8228909 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 787075 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 6498554 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5367359 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 80.500341 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1176738 # Number of times the RAS was used to get a target.
system.cpu.branchPred.BTBHitPct 82.593128 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1175694 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20396755 # DTB read hits
system.cpu.dtb.read_misses 47141 # DTB read misses
system.cpu.dtb.read_hits 20428735 # DTB read hits
system.cpu.dtb.read_misses 47112 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20443896 # DTB read accesses
system.cpu.dtb.write_hits 6580249 # DTB write hits
system.cpu.dtb.write_misses 266 # DTB write misses
system.cpu.dtb.read_accesses 20475847 # DTB read accesses
system.cpu.dtb.write_hits 6580361 # DTB write hits
system.cpu.dtb.write_misses 271 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6580515 # DTB write accesses
system.cpu.dtb.data_hits 26977004 # DTB hits
system.cpu.dtb.data_misses 47407 # DTB misses
system.cpu.dtb.write_accesses 6580632 # DTB write accesses
system.cpu.dtb.data_hits 27009096 # DTB hits
system.cpu.dtb.data_misses 47383 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 27024411 # DTB accesses
system.cpu.itb.fetch_hits 23068140 # ITB hits
system.cpu.dtb.data_accesses 27056479 # DTB accesses
system.cpu.itb.fetch_hits 23055300 # ITB hits
system.cpu.itb.fetch_misses 88 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 23068228 # ITB accesses
system.cpu.itb.fetch_accesses 23055388 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 104403065 # number of cpu cycles simulated
system.cpu.numCycles 104096921 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 91903089 # Number of instructions committed
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2153944 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 2232007 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.136013 # CPI: cycles per instruction
system.cpu.ipc 0.880272 # IPC: instructions per cycle
system.cpu.tickCycles 102681380 # Number of cycles that the object actually ticked
system.cpu.idleCycles 1721685 # Total number of cycles that the object has spent stopped
system.cpu.cpi 1.132681 # CPI: cycles per instruction
system.cpu.ipc 0.882861 # IPC: instructions per cycle
system.cpu.tickCycles 102361178 # Number of cycles that the object actually ticked
system.cpu.idleCycles 1735743 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 157 # number of replacements
system.cpu.dcache.tags.tagsinuse 1448.443915 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26568135 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 1448.464460 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26584631 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11913.961883 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11921.359193 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1448.443915 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.353624 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.353624 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 1448.464460 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.353629 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.353629 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
@ -320,56 +320,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 53145360 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 53145360 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 20069943 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20069943 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6498192 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 26568135 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26568135 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26568135 # number of overall hits
system.cpu.dcache.overall_hits::total 26568135 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 519 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2911 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2911 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3430 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses
system.cpu.dcache.overall_misses::total 3430 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 40365000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 216719250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 216719250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 257084250 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 257084250 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 257084250 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 257084250 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20070462 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20070462 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.tags.tag_accesses 53178348 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 53178348 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 20086436 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20086436 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6498195 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 26584631 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26584631 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26584631 # number of overall hits
system.cpu.dcache.overall_hits::total 26584631 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 520 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 520 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2908 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2908 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3428 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3428 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3428 # number of overall misses
system.cpu.dcache.overall_misses::total 3428 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 41644750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 41644750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 214147250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 214147250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 255792000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 255792000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 255792000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 255792000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20086956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20086956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 26571565 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 26571565 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 26571565 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 26571565 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 26588059 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 26588059 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 26588059 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 26588059 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77774.566474 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 77774.566474 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74448.385435 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 74448.385435 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 74951.676385 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 74951.676385 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80086.057692 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 80086.057692 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73640.732462 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73640.732462 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74618.436406 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 74618.436406 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74618.436406 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 74618.436406 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -380,14 +380,14 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 34 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 34 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1166 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1166 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1200 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1200 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 35 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 1163 # number of WriteReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 1198 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1198 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1198 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses
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@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230
system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 37010250 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 130741250 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 167751500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167751500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 167751500 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 38003250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129542250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 129542250 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 167545500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167545500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 167545500 # number of overall MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses
@ -412,24 +412,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76309.793814 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74923.352436 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74923.352436 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78357.216495 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78357.216495 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74236.246418 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74236.246418 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75132.511211 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75132.511211 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75132.511211 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75132.511211 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 13871 # number of replacements
system.cpu.icache.tags.tagsinuse 1640.396029 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 23052304 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15835 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1455.781749 # Average number of references to valid blocks.
system.cpu.icache.tags.replacements 13853 # number of replacements
system.cpu.icache.tags.tagsinuse 1640.586076 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 23039482 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15817 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1456.627806 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.396029 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::total 0.800975 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.586076 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::total 0.801067 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
@ -437,44 +437,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 669
system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 46152115 # Number of tag accesses
system.cpu.icache.tags.data_accesses 46152115 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 23052304 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 23052304 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::total 23052304 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15836 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15836 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 15836 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 15836 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 409644000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 409644000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::total 409644000 # number of overall miss cycles
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system.cpu.icache.overall_accesses::total 23068140 # number of overall (read+write) accesses
system.cpu.icache.tags.tag_accesses 46126417 # Number of tag accesses
system.cpu.icache.tags.data_accesses 46126417 # Number of data accesses
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system.cpu.icache.ReadReq_hits::total 23039482 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency::total 408417500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 408417500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 408417500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 408417500 # number of overall miss cycles
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25867.895933 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::total 25867.895933 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 25867.895933 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25819.793906 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 25819.793906 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25819.793906 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 25819.793906 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25819.793906 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 25819.793906 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -483,44 +483,44 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15836 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::total 15836 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15836 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15836 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 384517500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 384517500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 384517500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 384517500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 384517500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 384517500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15818 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15818 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15818 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15818 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15818 # number of overall MSHR misses
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 383318000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 383318000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 383318000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24281.226320 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24281.226320 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24233.025667 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24233.025667 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24233.025667 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 24233.025667 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24233.025667 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 24233.025667 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2479.394298 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 12735 # Total number of references to valid blocks.
system.cpu.l2cache.tags.tagsinuse 2479.864899 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 12717 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3665 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 3.469850 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.occ_blocks::writebacks 17.779390 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.640552 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 360.974356 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::writebacks 17.782834 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.110753 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 360.971312 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064106 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3665 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
@ -528,21 +528,21 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 768
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 182 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2506 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111847 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 150786 # Number of tag accesses
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system.cpu.l2cache.ReadReq_hits::cpu.inst 12650 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 12721 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 12703 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12668 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.inst 12668 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.inst 12650 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
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system.cpu.l2cache.overall_hits::total 12729 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.data 432 # number of ReadReq misses
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@ -554,52 +554,52 @@ system.cpu.l2cache.demand_misses::total 5318 # nu
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128723250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 128723250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 235668000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 164686000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 400354000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 235668000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 164686000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 400354000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15835 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234675500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 36955750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 271631250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 127524250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 127524250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 234675500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 164480000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 399155500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 234675500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 164480000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 399155500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15817 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 485 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 16302 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 15835 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 15817 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2230 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 18065 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15835 # number of overall (read+write) accesses
system.cpu.l2cache.demand_accesses::total 18047 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15817 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2230 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 18065 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200000 # miss rate for ReadReq accesses
system.cpu.l2cache.overall_accesses::total 18047 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200228 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890722 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.220527 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.220770 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985100 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200000 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200228 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964574 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.294381 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses
system.cpu.l2cache.demand_miss_rate::total 0.294675 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200228 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74413.640669 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83247.106481 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75473.951098 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74882.635253 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74882.635253 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75282.813088 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75282.813088 # average overall miss latency
system.cpu.l2cache.overall_miss_rate::total 0.294675 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74100.252605 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85545.717593 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75474.090025 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74185.136707 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74185.136707 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74100.252605 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76466.759647 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75057.446408 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74100.252605 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76466.759647 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75057.446408 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -619,68 +619,68 @@ system.cpu.l2cache.demand_mshr_misses::total 5318
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3167 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196043000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30551250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 226594250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 107188750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 107188750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196043000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137740000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 333783000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196043000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137740000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 333783000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195052500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31544750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 226597250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 106089750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 106089750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195052500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137634500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 332687000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195052500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137634500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 332687000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200228 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220770 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200228 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for overall accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.294675 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200228 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61901.799811 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.486111 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62960.336205 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62355.293775 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62355.293775 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294675 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61589.043259 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73020.254630 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62961.169769 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61715.968586 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61715.968586 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61589.043259 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63986.285449 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62558.668672 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61589.043259 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63986.285449 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62558.668672 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 16320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadReq 16302 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 16302 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31670 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31634 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 36237 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013440 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 36201 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012288 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 1163008 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 1161856 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 18172 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 18154 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 18172 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 18154 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 18172 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 9193000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 18154 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 9184000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 24439500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 24412500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3770500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 3745500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadReq 3599 # Transaction distribution
system.membus.trans_dist::ReadResp 3599 # Transaction distribution
@ -701,9 +701,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 5318 # Request fanout histogram
system.membus.reqLayer0.occupancy 6453000 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 6399500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 28232500 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 28155000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

678
tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
View file

@ -1,42 +1,42 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.131767 # Number of seconds simulated
sim_ticks 131767151500 # Number of ticks simulated
final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.131586 # Number of seconds simulated
sim_ticks 131586268500 # Number of ticks simulated
final_tick 131586268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 244794 # Simulator instruction rate (inst/s)
host_op_rate 258052 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 187187675 # Simulator tick rate (ticks/s)
host_mem_usage 317932 # Number of bytes of host memory used
host_seconds 703.93 # Real time elapsed on the host
host_inst_rate 246297 # Simulator instruction rate (inst/s)
host_op_rate 259636 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 188078312 # Simulator tick rate (ticks/s)
host_mem_usage 317920 # Number of bytes of host memory used
host_seconds 699.64 # Real time elapsed on the host
sim_insts 172317810 # Number of instructions simulated
sim_ops 181650743 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 138368 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
system.physmem.bytes_read::total 247616 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory
system.physmem.bytes_read::total 247680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 138368 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 138368 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2162 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1049609 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 829585 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1879194 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1049609 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1049609 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1049609 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 829585 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1879194 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 3869 # Number of read requests accepted
system.physmem.num_reads::total 3870 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1051538 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 830725 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1882263 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1051538 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1051538 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1051538 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 830725 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1882263 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 3870 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.readBursts 3870 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM
system.physmem.bytesReadDRAM 247680 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side
system.physmem.bytesReadSys 247680 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@ -45,18 +45,18 @@ system.physmem.perBankRdBursts::0 305 # Pe
system.physmem.perBankRdBursts::1 217 # Per bank write bursts
system.physmem.perBankRdBursts::2 135 # Per bank write bursts
system.physmem.perBankRdBursts::3 313 # Per bank write bursts
system.physmem.perBankRdBursts::4 307 # Per bank write bursts
system.physmem.perBankRdBursts::4 308 # Per bank write bursts
system.physmem.perBankRdBursts::5 305 # Per bank write bursts
system.physmem.perBankRdBursts::6 273 # Per bank write bursts
system.physmem.perBankRdBursts::7 222 # Per bank write bursts
system.physmem.perBankRdBursts::8 249 # Per bank write bursts
system.physmem.perBankRdBursts::9 218 # Per bank write bursts
system.physmem.perBankRdBursts::10 295 # Per bank write bursts
system.physmem.perBankRdBursts::11 200 # Per bank write bursts
system.physmem.perBankRdBursts::11 201 # Per bank write bursts
system.physmem.perBankRdBursts::12 183 # Per bank write bursts
system.physmem.perBankRdBursts::13 218 # Per bank write bursts
system.physmem.perBankRdBursts::14 224 # Per bank write bursts
system.physmem.perBankRdBursts::15 205 # Per bank write bursts
system.physmem.perBankRdBursts::15 204 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 131767057000 # Total gap between requests
system.physmem.totGap 131586174000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 3869 # Read request sizes (log2)
system.physmem.readPktSize::6 3870 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 907 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 272.793826 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 180.627814 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 276.033343 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 260 28.67% 28.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 352 38.81% 67.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 83 9.15% 76.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 54 5.95% 82.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 42 4.63% 87.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 20 2.21% 89.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 22 2.43% 91.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 19 2.09% 93.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 55 6.06% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 907 # Bytes accessed per row activation
system.physmem.totQLat 28218000 # Total ticks spent queuing
system.physmem.totMemAccLat 100761750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7293.36 # Average queueing delay per DRAM burst
system.physmem.bytesPerActivate::samples 901 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 272.834628 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 180.187503 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 278.027106 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 257 28.52% 28.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 352 39.07% 67.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 83 9.21% 76.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 53 5.88% 82.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 41 4.55% 87.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 20 2.22% 89.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 17 1.89% 91.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 20 2.22% 93.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 58 6.44% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 901 # Bytes accessed per row activation
system.physmem.totQLat 26462250 # Total ticks spent queuing
system.physmem.totMemAccLat 99024750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 19350000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6837.79 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 26043.36 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 25587.79 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s
@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.01 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 2961 # Number of row buffer hits during reads
system.physmem.readRowHits 2963 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads
system.physmem.readRowHitRate 76.56 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 34057135.44 # Average gap between requests
system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3114720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1699500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 16200600 # Energy for read commands per rank (pJ)
system.physmem.avgGap 34001595.35 # Average gap between requests
system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3107160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1695375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 3598001595 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 75904039500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 88129416795 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.827838 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 126271035750 # Time in different power states
system.physmem_0.memoryStateTime::REF 4399980000 # Time in different power states
system.physmem_0.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 3588895845 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 75799905000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 88003936020 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.824061 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 126101706500 # Time in different power states
system.physmem_0.memoryStateTime::REF 4393740000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1095966750 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1088502500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3742200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2041875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 13954200 # Energy for read commands per rank (pJ)
system.physmem_1.actEnergy 3689280 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2013000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 3577878315 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 75921691500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 88125668970 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.799395 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 126300767500 # Time in different power states
system.physmem_1.memoryStateTime::REF 4399980000 # Time in different power states
system.physmem_1.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 3567061710 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 75819057750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 87999744180 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.792204 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 126130418250 # Time in different power states
system.physmem_1.memoryStateTime::REF 4393740000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1066235000 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1056288250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 49934214 # Number of BP lookups
system.cpu.branchPred.condPredicted 39669228 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 5745476 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 24397430 # Number of BTB lookups
system.cpu.branchPred.BTBHits 23302007 # Number of BTB hits
system.cpu.branchPred.lookups 49889699 # Number of BP lookups
system.cpu.branchPred.condPredicted 39633555 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 5745356 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 24337780 # Number of BTB lookups
system.cpu.branchPred.BTBHits 23279998 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 95.510089 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1908013 # Number of times the RAS was used to get a target.
system.cpu.branchPred.BTBHitPct 95.653745 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1903300 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 140 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 263534303 # number of cpu cycles simulated
system.cpu.numCycles 263172537 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 172317810 # Number of instructions committed
system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
system.cpu.discardedOps 11762366 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 11983755 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.529350 # CPI: cycles per instruction
system.cpu.ipc 0.653872 # IPC: instructions per cycle
system.cpu.tickCycles 257146871 # Number of cycles that the object actually ticked
system.cpu.idleCycles 6387432 # Total number of cycles that the object has spent stopped
system.cpu.cpi 1.527251 # CPI: cycles per instruction
system.cpu.ipc 0.654771 # IPC: instructions per cycle
system.cpu.tickCycles 256740434 # Number of cycles that the object actually ticked
system.cpu.idleCycles 6432103 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 42 # number of replacements
system.cpu.dcache.tags.tagsinuse 1377.696434 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40764379 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 1377.700648 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40793912 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 22521.756354 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 22538.072928 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1377.696434 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 1377.700648 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.336353 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.336353 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
@ -404,10 +404,10 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 81535444 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 81535444 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 28356460 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 28356460 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 81594514 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 81594514 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 28385993 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 28385993 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 464 # number of SoftPFReq hits
@ -416,30 +416,30 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 40719101 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 40719101 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 40719565 # number of overall hits
system.cpu.dcache.overall_hits::total 40719565 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
system.cpu.dcache.demand_hits::cpu.data 40748634 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 40748634 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 40749098 # number of overall hits
system.cpu.dcache.overall_hits::total 40749098 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 2437 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2437 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2438 # number of overall misses
system.cpu.dcache.overall_misses::total 2438 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 59434234 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 59434234 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 127677000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 127677000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 187111234 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 187111234 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 187111234 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 187111234 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 28357251 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 28357251 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_misses::cpu.data 2439 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2439 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2440 # number of overall misses
system.cpu.dcache.overall_misses::total 2440 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 57815734 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 57815734 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 126489000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 126489000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 184304734 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 184304734 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 184304734 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 184304734 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 28386786 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 28386786 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 465 # number of SoftPFReq accesses(hits+misses)
@ -448,10 +448,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 40721538 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 40721538 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 40722003 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 40722003 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 40751073 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 40751073 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 40751538 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 40751538 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses
@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060
system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75138.096081 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 75138.096081 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77568.043742 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 77568.043742 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76779.332786 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76779.332786 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76747.840033 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76747.840033 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72907.609079 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 72907.609079 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76846.294046 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 76846.294046 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75565.696597 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 75565.696597 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75534.727049 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 75534.727049 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -480,14 +480,14 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
system.cpu.dcache.writebacks::total 16 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 628 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 628 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 628 # number of overall MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses
@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809
system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52911264 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 52911264 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 85210500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51168764 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 51168764 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84319000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84319000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138121764 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 138121764 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138191264 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 138191264 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 135487764 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 135487764 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 135557264 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 135557264 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74418.092827 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77605.191257 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77605.191257 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71967.319269 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71967.319269 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76793.260474 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76793.260474 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76352.550580 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76352.550580 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76348.764641 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76348.764641 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74896.497512 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74896.497512 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74893.516022 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74893.516022 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 2892 # number of replacements
system.cpu.icache.tags.tagsinuse 1425.992142 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 71598587 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 4690 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 15266.223241 # Average number of references to valid blocks.
system.cpu.icache.tags.replacements 2889 # number of replacements
system.cpu.icache.tags.tagsinuse 1425.913177 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 71538503 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 4687 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 15263.175379 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1425.992142 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.696285 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.696285 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 1425.913177 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.696247 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.696247 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1798 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.877930 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 143211246 # Number of tag accesses
system.cpu.icache.tags.data_accesses 143211246 # Number of data accesses
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system.cpu.icache.ReadReq_misses::total 4691 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 4691 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4691 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 200040248 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 200040248 # number of demand (read+write) miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 200735747 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.412492 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 42643.412492 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.412492 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 42643.412492 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.412492 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 42643.412492 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42819.058660 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 42819.058660 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 42819.058660 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency
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@ -591,123 +591,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4691 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4691 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4691 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 4691 # number of demand (read+write) MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192077752 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 192077752 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192077752 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 192077752 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192077752 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 192077752 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4688 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4688 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4688 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 4688 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4688 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4688 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192780753 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 192780753 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192780753 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 192780753 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192780753 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 192780753 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40946.014069 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40946.014069 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40946.014069 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 40946.014069 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40946.014069 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 40946.014069 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41122.174275 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41122.174275 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41122.174275 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 41122.174275 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41122.174275 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 41122.174275 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2003.582702 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2608 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.935773 # Average number of references to valid blocks.
system.cpu.l2cache.tags.tagsinuse 2002.534339 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2603 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2788 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.933644 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029186 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1509.739376 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814139 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029198 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1508.688891 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 490.816250 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.061144 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id
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system.cpu.l2cache.tags.occ_percent::total 0.061112 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2788 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2007 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 56021 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 56021 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 2527 # number of ReadReq hits
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2006 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085083 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 55998 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 55998 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 2522 # number of ReadReq hits
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@ -716,111 +716,111 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 5403 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 5402 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadReq 5400 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 5399 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9381 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9375 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count::total 13011 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 416832 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 6514 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 6517 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 6514 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 6514 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 3273000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 7498748 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 7492747 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3019736 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadReq 2779 # Transaction distribution
system.membus.trans_dist::ReadResp 2779 # Transaction distribution
system.membus.trans_dist::ReadReq 2780 # Transaction distribution
system.membus.trans_dist::ReadResp 2780 # Transaction distribution
system.membus.trans_dist::ReadExReq 1090 # Transaction distribution
system.membus.trans_dist::ReadExResp 1090 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7740 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 7740 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247680 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 247680 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 3869 # Request fanout histogram
system.membus.snoop_fanout::samples 3870 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 3870 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 3869 # Request fanout histogram
system.membus.reqLayer0.occupancy 4517000 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 3870 # Request fanout histogram
system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 20556500 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 20561750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

388
tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000038 # Number of seconds simulated
sim_ticks 37928000 # Number of ticks simulated
final_tick 37928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 37930000 # Number of ticks simulated
final_tick 37930000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 174102 # Simulator instruction rate (inst/s)
host_op_rate 174036 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1031016392 # Simulator tick rate (ticks/s)
host_mem_usage 293404 # Number of bytes of host memory used
host_inst_rate 161486 # Simulator instruction rate (inst/s)
host_op_rate 161429 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 956403338 # Simulator tick rate (ticks/s)
host_mem_usage 294064 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 6400 # Number of instructions simulated
sim_ops 6400 # Number of ops (including micro ops) simulated
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu
system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 614216410 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 285171905 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 899388315 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 614216410 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 614216410 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 614216410 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 285171905 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 899388315 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 614184023 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 285156868 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 899340891 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 614184023 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 614184023 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 614184023 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 285156868 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 899340891 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 533 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 37822500 # Total gap between requests
system.physmem.totGap 37824500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@ -206,9 +206,9 @@ system.physmem.totBusLat 2665000 # To
system.physmem.avgQLat 6100.38 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 24850.38 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 899.39 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgRdBW 899.34 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 899.39 # Average system read bandwidth in MiByte/s
system.physmem.avgRdBWSys 899.34 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 7.03 # Data bus utilization in percentage
@ -220,7 +220,7 @@ system.physmem.readRowHits 437 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 70961.54 # Average gap between requests
system.physmem.avgGap 70965.29 # Average gap between requests
system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ)
@ -231,7 +231,7 @@ system.physmem_0.actBackEnergy 21404070 # En
system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ)
system.physmem_0.averagePower 825.080242 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 371750 # Time in different power states
system.physmem_0.memoryStateTime::IDLE 372750 # Time in different power states
system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states
@ -250,13 +250,13 @@ system.physmem_1.memoryStateTime::REF 1040000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 28783000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 1968 # Number of BP lookups
system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted
system.cpu.branchPred.lookups 1964 # Number of BP lookups
system.cpu.branchPred.condPredicted 1204 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1559 # Number of BTB lookups
system.cpu.branchPred.BTBHits 385 # Number of BTB hits
system.cpu.branchPred.BTBLookups 1555 # Number of BTB lookups
system.cpu.branchPred.BTBHits 382 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 24.695318 # BTB Hit Percentage
system.cpu.branchPred.BTBHitPct 24.565916 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
@ -264,22 +264,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1370 # DTB read hits
system.cpu.dtb.read_hits 1371 # DTB read hits
system.cpu.dtb.read_misses 11 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1381 # DTB read accesses
system.cpu.dtb.read_accesses 1382 # DTB read accesses
system.cpu.dtb.write_hits 884 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 887 # DTB write accesses
system.cpu.dtb.data_hits 2254 # DTB hits
system.cpu.dtb.data_hits 2255 # DTB hits
system.cpu.dtb.data_misses 14 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2268 # DTB accesses
system.cpu.itb.fetch_hits 2639 # ITB hits
system.cpu.dtb.data_accesses 2269 # DTB accesses
system.cpu.itb.fetch_hits 2638 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2656 # ITB accesses
system.cpu.itb.fetch_accesses 2655 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -293,40 +293,40 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 75856 # number of cpu cycles simulated
system.cpu.numCycles 75860 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6400 # Number of instructions committed
system.cpu.committedOps 6400 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1110 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 11.852500 # CPI: cycles per instruction
system.cpu.ipc 0.084370 # IPC: instructions per cycle
system.cpu.tickCycles 12576 # Number of cycles that the object actually ticked
system.cpu.idleCycles 63280 # Total number of cycles that the object has spent stopped
system.cpu.cpi 11.853125 # CPI: cycles per instruction
system.cpu.ipc 0.084366 # IPC: instructions per cycle
system.cpu.tickCycles 12560 # Number of cycles that the object actually ticked
system.cpu.idleCycles 63300 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 103.896503 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 103.899066 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1976 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.692308 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 103.896503 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025365 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025365 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 103.899066 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025366 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025366 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4571 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4571 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1235 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1235 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 741 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 741 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits
system.cpu.dcache.overall_hits::total 1975 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 1976 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1976 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1976 # number of overall hits
system.cpu.dcache.overall_hits::total 1976 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 124 # number of WriteReq misses
@ -335,38 +335,38 @@ system.cpu.dcache.demand_misses::cpu.data 226 # n
system.cpu.dcache.demand_misses::total 226 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 226 # number of overall misses
system.cpu.dcache.overall_misses::total 226 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8143750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8143750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9234250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9234250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 17378000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17378000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17378000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17378000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1336 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1336 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8144750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8144750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9233750 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9233750 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 17378500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17378500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17378500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17378500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2201 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2201 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2201 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2201 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076347 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.076347 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2202 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2202 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2202 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076290 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.076290 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.143353 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.143353 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.102681 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.102681 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.102681 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.102681 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79840.686275 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 79840.686275 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74469.758065 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 74469.758065 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76893.805310 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76893.805310 # average overall miss latency
system.cpu.dcache.demand_miss_rate::cpu.data 0.102634 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.102634 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.102634 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.102634 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79850.490196 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 79850.490196 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74465.725806 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 74465.725806 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76896.017699 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76896.017699 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7563250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7563250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7564250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7564250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5364250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5364250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12927500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12927500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12927500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12927500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071856 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071856 # mshr miss rate for ReadReq accesses
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12928500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12928500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12928500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12928500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78783.854167 # average ReadReq mshr miss latency
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system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency
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system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 175.733533 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks.
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system.cpu.icache.tags.total_refs 2273 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 6.227397 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 175.733533 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.085807 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.085807 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 175.739822 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::total 0.085810 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
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system.cpu.icache.tags.data_accesses 5643 # Number of data accesses
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency
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@ -481,36 +481,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency
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system.cpu.icache.ReadReq_mshr_miss_latency::total 27622750 # number of ReadReq MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 27622750 # number of overall MSHR miss cycles
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency
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@ -567,17 +567,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.998127 #
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses
@ -619,17 +619,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62324.862637 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65200.520833 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62925 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62326.236264 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65210.937500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62928.260870 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59976.027397 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59976.027397 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
@ -678,7 +678,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 533 # Request fanout histogram
system.membus.reqLayer0.occupancy 604000 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 2833250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 7.5 # Layer utilization (%)

14
tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -4,10 +4,10 @@ sim_seconds 0.000020 # Nu
sim_ticks 20287000 # Number of ticks simulated
final_tick 20287000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 136939 # Simulator instruction rate (inst/s)
host_op_rate 136838 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1073215892 # Simulator tick rate (ticks/s)
host_mem_usage 292092 # Number of bytes of host memory used
host_inst_rate 140405 # Simulator instruction rate (inst/s)
host_op_rate 140306 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1100341704 # Simulator tick rate (ticks/s)
host_mem_usage 292772 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 2585 # Number of instructions simulated
sim_ops 2585 # Number of ops (including micro ops) simulated
@ -298,12 +298,12 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2585 # Number of instructions committed
system.cpu.committedOps 2585 # Number of ops (including micro ops) committed
system.cpu.discardedOps 595 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 594 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 15.695938 # CPI: cycles per instruction
system.cpu.ipc 0.063711 # IPC: instructions per cycle
system.cpu.tickCycles 5396 # Number of cycles that the object actually ticked
system.cpu.idleCycles 35178 # Total number of cycles that the object has spent stopped
system.cpu.tickCycles 5391 # Number of cycles that the object actually ticked
system.cpu.idleCycles 35183 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 48.342007 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks.

318
tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000030 # Number of seconds simulated
sim_ticks 30321500 # Number of ticks simulated
final_tick 30321500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 30323500 # Number of ticks simulated
final_tick 30323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 50258 # Simulator instruction rate (inst/s)
host_op_rate 58824 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 330783185 # Simulator tick rate (ticks/s)
host_mem_usage 302404 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_inst_rate 117134 # Simulator instruction rate (inst/s)
host_op_rate 137081 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 770805796 # Simulator tick rate (ticks/s)
host_mem_usage 310084 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 4605 # Number of instructions simulated
sim_ops 5391 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu
system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 643767624 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 244842768 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 888610392 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 643767624 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 643767624 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 643767624 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 244842768 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 888610392 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 643725164 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 244826620 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 888551783 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 643725164 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 643725164 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 643725164 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 244826620 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 888551783 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 421 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 30230000 # Total gap between requests
system.physmem.totGap 30232000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # By
system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
system.physmem.totQLat 2532750 # Total ticks spent queuing
system.physmem.totMemAccLat 10426500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 2542750 # Total ticks spent queuing
system.physmem.totMemAccLat 10436500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6016.03 # Average queueing delay per DRAM burst
system.physmem.avgQLat 6039.79 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 24766.03 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 888.61 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgMemAccLat 24789.79 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 888.55 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 888.61 # Average system read bandwidth in MiByte/s
system.physmem.avgRdBWSys 888.55 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 6.94 # Data bus utilization in percentage
@ -220,7 +220,7 @@ system.physmem.readRowHits 349 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 71805.23 # Average gap between requests
system.physmem.avgGap 71809.98 # Average gap between requests
system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
@ -377,44 +377,44 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 60643 # number of cpu cycles simulated
system.cpu.numCycles 60647 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 4605 # Number of instructions committed
system.cpu.committedOps 5391 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1105 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 13.168947 # CPI: cycles per instruction
system.cpu.ipc 0.075936 # IPC: instructions per cycle
system.cpu.tickCycles 10594 # Number of cycles that the object actually ticked
system.cpu.idleCycles 50049 # Total number of cycles that the object has spent stopped
system.cpu.cpi 13.169815 # CPI: cycles per instruction
system.cpu.ipc 0.075931 # IPC: instructions per cycle
system.cpu.tickCycles 10567 # Number of cycles that the object actually ticked
system.cpu.idleCycles 50080 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 86.367225 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1917 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 86.373507 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.130137 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 86.367225 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.021086 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.021086 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 86.373507 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.021087 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.021087 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4344 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4344 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 4346 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4346 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 1895 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1895 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1895 # number of overall hits
system.cpu.dcache.overall_hits::total 1895 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
system.cpu.dcache.overall_hits::total 1896 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses
@ -423,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
system.cpu.dcache.overall_misses::total 182 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7249991 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7249991 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7248241 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7248241 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 12303491 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12303491 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12303491 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12303491 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency::cpu.data 12301741 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12301741 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12301741 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12301741 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1165 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1165 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2077 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2077 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2077 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2077 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098797 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.098797 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2078 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2078 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2078 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2078 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098712 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.098712 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.087626 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.087626 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.087626 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.087626 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63043.400000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 63043.400000 # average ReadReq miss latency
system.cpu.dcache.demand_miss_rate::cpu.data 0.087584 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.087584 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.087584 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.087584 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.182609 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.182609 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 67601.598901 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67601.598901 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 67591.983516 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67591.983516 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -483,43 +483,43 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6563508 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6563508 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6562258 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6562258 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9742758 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9742758 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9742758 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9742758 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088488 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088488 # mshr miss rate for ReadReq accesses
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9741508 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9741508 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency
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system.cpu.icache.tags.data_accesses 4784 # Number of data accesses
@ -535,12 +535,12 @@ system.cpu.icache.demand_misses::cpu.inst 322 # n
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@ -629,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 429 # nu
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@ -662,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 #
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
@ -758,7 +758,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 234000 # La
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 240992 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.membus.trans_dist::ReadReq 378 # Transaction distribution
system.membus.trans_dist::ReadResp 378 # Transaction distribution
@ -779,9 +779,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 421 # Request fanout histogram
system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 2238750 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 2238000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 7.4 # Layer utilization (%)
---------- End Simulation Statistics ----------