ARM: Decode 16 bit thumb register addressed memory instructions.
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@ -90,16 +90,7 @@
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0xe, 0xf: WarnUnimpl::blx(); //register
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0xe, 0xf: WarnUnimpl::blx(); //register
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}
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}
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0x2, 0x3: WarnUnimpl::ldr();
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0x2, 0x3: WarnUnimpl::ldr();
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default: decode TOPCODE_11_9 {
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default: Thumb16MemReg::thumb16MemReg();
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0x0: WarnUnimpl::str(); //register
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0x1: WarnUnimpl::strh(); //register
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0x2: WarnUnimpl::strb(); //register
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0x3: WarnUnimpl::ldrsb(); //register
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0x4: WarnUnimpl::ldr(); //register
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0x5: WarnUnimpl::ldrh(); //register
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0x6: WarnUnimpl::ldrb(); //register
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0x7: WarnUnimpl::ldrsh(); //register
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}
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}
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}
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0x3: decode TOPCODE_12_11 {
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0x3: decode TOPCODE_12_11 {
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0x0: WarnUnimpl::str(); //immediate, thumb
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0x0: WarnUnimpl::str(); //immediate, thumb
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@ -358,6 +358,46 @@ def format Thumb32StoreSingle() {{
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decode_block = decode % classNames
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decode_block = decode % classNames
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}};
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}};
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def format Thumb16MemReg() {{
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decode = '''
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{
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const uint32_t opb = bits(machInst, 11, 9);
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const uint32_t rt = bits(machInst, 2, 0);
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const uint32_t rn = bits(machInst, 5, 3);
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const uint32_t rm = bits(machInst, 8, 6);
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switch (opb) {
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case 0x0:
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return new %(str)s(machInst, rt, rn, true, 0, LSL, rm);
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case 0x1:
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return new %(strh)s(machInst, rt, rn, true, 0, LSL, rm);
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case 0x2:
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return new %(strb)s(machInst, rt, rn, true, 0, LSL, rm);
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case 0x3:
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return new %(ldrsb)s(machInst, rt, rn, true, 0, LSL, rm);
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case 0x4:
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return new %(ldr)s(machInst, rt, rn, true, 0, LSL, rm);
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case 0x5:
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return new %(ldrh)s(machInst, rt, rn, true, 0, LSL, rm);
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case 0x6:
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return new %(ldrb)s(machInst, rt, rn, true, 0, LSL, rm);
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case 0x7:
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return new %(ldrsh)s(machInst, rt, rn, true, 0, LSL, rm);
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}
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}
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'''
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classNames = {
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"str" : storeRegClassName(False, True, False),
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"strh" : storeRegClassName(False, True, False, size=2),
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"strb" : storeRegClassName(False, True, False, size=1),
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"ldrsb" : loadRegClassName(False, True, False, sign=True, size=1),
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"ldr" : loadRegClassName(False, True, False),
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"ldrh" : loadRegClassName(False, True, False, size=2),
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"ldrb" : loadRegClassName(False, True, False, size=1),
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"ldrsh" : loadRegClassName(False, True, False, sign=True, size=2),
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}
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decode_block = decode % classNames
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}};
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def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
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def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
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mem_flags = [], inst_flags = []) {{
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mem_flags = [], inst_flags = []) {{
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ea_code = ArmGenericCodeSubs(ea_code)
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ea_code = ArmGenericCodeSubs(ea_code)
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