Fix up instructions to read and write control registers, and got rid of the control register fields which won't work on a big endian host.
--HG-- extra : convert_revision : 1b518873b6e1a073b58cbe27642537d5ae3a604d
This commit is contained in:
parent
232c3f1b27
commit
4aea5deccb
6 changed files with 271 additions and 264 deletions
|
@ -346,22 +346,93 @@ decode OP default Unknown::unknown()
|
||||||
0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
|
0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
|
||||||
0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
|
0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
|
||||||
}
|
}
|
||||||
// XXX might want a format rdipr thing here
|
|
||||||
0x28: decode RS1 {
|
0x28: decode RS1 {
|
||||||
0xF: decode I {
|
0x00: NoPriv::rdy({{Rd = Y;}});
|
||||||
|
//1 should cause an illegal instruction exception
|
||||||
|
0x02: NoPriv::rdccr({{Rd = Ccr;}});
|
||||||
|
0x03: NoPriv::rdasi({{Rd = Asi;}});
|
||||||
|
0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
|
||||||
|
0x05: NoPriv::rdpc({{
|
||||||
|
if(Pstate<3:>)
|
||||||
|
Rd = (xc->readPC())<31:0>;
|
||||||
|
else
|
||||||
|
Rd = xc->readPC();}});
|
||||||
|
0x06: NoPriv::rdfprs({{
|
||||||
|
//Wait for all fpops to finish.
|
||||||
|
Rd = Fprs;
|
||||||
|
}});
|
||||||
|
//7-14 should cause an illegal instruction exception
|
||||||
|
0x0F: decode I {
|
||||||
0x0: Nop::stbar({{/*stuff*/}});
|
0x0: Nop::stbar({{/*stuff*/}});
|
||||||
0x1: Nop::membar({{/*stuff*/}});
|
0x1: Nop::membar({{/*stuff*/}});
|
||||||
}
|
}
|
||||||
default: rdasr({{
|
0x10: Priv::rdpcr({{Rd = Pcr;}});
|
||||||
Rd = xc->readMiscRegWithEffect(RS1 + AsrStart);
|
0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
|
||||||
|
//0x12 should cause an illegal instruction exception
|
||||||
|
0x13: NoPriv::rdgsr({{
|
||||||
|
if(Fprs<2:> == 0 || Pstate<4:> == 0)
|
||||||
|
Rd = Gsr;
|
||||||
|
else
|
||||||
|
fault = new FpDisabled;
|
||||||
}});
|
}});
|
||||||
|
//0x14-0x15 should cause an illegal instruction exception
|
||||||
|
0x16: Priv::rdsoftint({{Rd = Softint;}});
|
||||||
|
0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
|
||||||
|
0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
|
||||||
|
0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
|
||||||
|
//0x1A-0x1F should cause an illegal instruction exception
|
||||||
|
}
|
||||||
|
0x29: decode RS1 {
|
||||||
|
0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
|
||||||
|
0x01: HPriv::rdhprhtstate({{
|
||||||
|
if(Tl == 0)
|
||||||
|
return new IllegalInstruction;
|
||||||
|
Rd = Htstate;
|
||||||
|
}});
|
||||||
|
//0x02 should cause an illegal instruction exception
|
||||||
|
0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
|
||||||
|
//0x04 should cause an illegal instruction exception
|
||||||
|
0x05: HPriv::rdhprhtba({{Rd = Htba;}});
|
||||||
|
0x06: HPriv::rdhprhver({{Rd = Hver;}});
|
||||||
|
//0x07-0x1E should cause an illegal instruction exception
|
||||||
|
0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
|
||||||
|
}
|
||||||
|
0x2A: decode RS1 {
|
||||||
|
0x00: Priv::rdprtpc({{
|
||||||
|
if(Tl == 0)
|
||||||
|
return new IllegalInstruction;
|
||||||
|
Rd = Tpc;
|
||||||
|
}});
|
||||||
|
0x01: Priv::rdprtnpc({{
|
||||||
|
if(Tl == 0)
|
||||||
|
return new IllegalInstruction;
|
||||||
|
Rd = Tnpc;
|
||||||
|
}});
|
||||||
|
0x02: Priv::rdprtstate({{
|
||||||
|
if(Tl == 0)
|
||||||
|
return new IllegalInstruction;
|
||||||
|
Rd = Tstate;
|
||||||
|
}});
|
||||||
|
0x03: Priv::rdprtt({{
|
||||||
|
if(Tl == 0)
|
||||||
|
return new IllegalInstruction;
|
||||||
|
Rd = Tt;
|
||||||
|
}});
|
||||||
|
0x04: Priv::rdprtick({{Rd = Tick;}});
|
||||||
|
0x05: Priv::rdprtba({{Rd = Tba;}});
|
||||||
|
0x06: Priv::rdprpstate({{Rd = Pstate;}});
|
||||||
|
0x07: Priv::rdprtl({{Rd = Tl;}});
|
||||||
|
0x08: Priv::rdprpil({{Rd = Pil;}});
|
||||||
|
0x09: Priv::rdprcwp({{Rd = Cwp;}});
|
||||||
|
0x0A: Priv::rdprcansave({{Rd = Cansave;}});
|
||||||
|
0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
|
||||||
|
0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
|
||||||
|
0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
|
||||||
|
0x0E: Priv::rdprwstate({{Rd = Wstate;}});
|
||||||
|
//0x0F should cause an illegal instruction exception
|
||||||
|
0x10: Priv::rdprgl({{Rd = Gl;}});
|
||||||
|
//0x11-0x1F should cause an illegal instruction exception
|
||||||
}
|
}
|
||||||
0x29: HPriv::rdhpr({{
|
|
||||||
Rd = xc->readMiscRegWithEffect(RS1 + HprStart);
|
|
||||||
}});
|
|
||||||
0x2A: Priv::rdpr({{
|
|
||||||
Rd = xc->readMiscRegWithEffect(RS1 + PrStart);
|
|
||||||
}});
|
|
||||||
0x2B: BasicOperate::flushw({{
|
0x2B: BasicOperate::flushw({{
|
||||||
if(NWindows - 2 - Cansave == 0)
|
if(NWindows - 2 - Cansave == 0)
|
||||||
{
|
{
|
||||||
|
@ -417,9 +488,35 @@ decode OP default Unknown::unknown()
|
||||||
0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
|
0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
|
||||||
0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
|
0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
|
||||||
}
|
}
|
||||||
0x30: wrasr({{
|
0x30: decode RD {
|
||||||
xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
|
0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
|
||||||
}});
|
//0x01 should cause an illegal instruction exception
|
||||||
|
0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
//0x04-0x05 should cause an illegal instruction exception
|
||||||
|
0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
//0x07-0x0E should cause an illegal instruction exception
|
||||||
|
0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
|
||||||
|
0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
|
||||||
|
//0x12 should cause an illegal instruction exception
|
||||||
|
0x13: NoPriv::wrgsr({{
|
||||||
|
if(Fprs<2:> == 0 || Pstate<4:> == 0)
|
||||||
|
return new FpDisabled;
|
||||||
|
Gsr = Rs1 ^ Rs2_or_imm13;
|
||||||
|
}});
|
||||||
|
0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x18: NoPriv::wrstick({{
|
||||||
|
if(!Hpstate<2:>)
|
||||||
|
return new IllegalInstruction;
|
||||||
|
Stick = Rs1 ^ Rs2_or_imm13;
|
||||||
|
}});
|
||||||
|
0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
//0x1A-0x1F should cause an illegal instruction exception
|
||||||
|
}
|
||||||
0x31: decode FCN {
|
0x31: decode FCN {
|
||||||
0x0: Priv::saved({{
|
0x0: Priv::saved({{
|
||||||
assert(Cansave < NWindows - 2);
|
assert(Cansave < NWindows - 2);
|
||||||
|
@ -440,16 +537,70 @@ decode OP default Unknown::unknown()
|
||||||
Otherwin = Otherwin - 1;
|
Otherwin = Otherwin - 1;
|
||||||
}});
|
}});
|
||||||
}
|
}
|
||||||
0x32: Priv::wrpr({{
|
0x32: decode RD {
|
||||||
// XXX Need to protect with format that traps non-priv
|
0x00: Priv::wrprtpc({{
|
||||||
// access
|
if(Tl == 0)
|
||||||
xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
|
return new IllegalInstruction;
|
||||||
}});
|
else
|
||||||
0x33: HPriv::wrhpr({{
|
Tpc = Rs1 ^ Rs2_or_imm13;
|
||||||
// XXX Need to protect with format that traps non-priv/priv
|
}});
|
||||||
// access
|
0x01: Priv::wrprtnpc({{
|
||||||
xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
|
if(Tl == 0)
|
||||||
}});
|
return new IllegalInstruction;
|
||||||
|
else
|
||||||
|
Tnpc = Rs1 ^ Rs2_or_imm13;
|
||||||
|
}});
|
||||||
|
0x02: Priv::wrprtstate({{
|
||||||
|
if(Tl == 0)
|
||||||
|
return new IllegalInstruction;
|
||||||
|
else
|
||||||
|
Tstate = Rs1 ^ Rs2_or_imm13;
|
||||||
|
}});
|
||||||
|
0x03: Priv::wrprtt({{
|
||||||
|
if(Tl == 0)
|
||||||
|
return new IllegalInstruction;
|
||||||
|
else
|
||||||
|
Tt = Rs1 ^ Rs2_or_imm13;
|
||||||
|
}});
|
||||||
|
0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x07: Priv::wrprtl({{
|
||||||
|
if(Pstate<2:> && !Hpstate<2:>)
|
||||||
|
Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
|
||||||
|
else
|
||||||
|
Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
|
||||||
|
}});
|
||||||
|
0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
//0x0F should cause an illegal instruction exception
|
||||||
|
0x10: Priv::wrprgl({{
|
||||||
|
if(Pstate<2:> && !Hpstate<2:>)
|
||||||
|
Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
|
||||||
|
else
|
||||||
|
Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
|
||||||
|
}});
|
||||||
|
//0x11-0x1F should cause an illegal instruction exception
|
||||||
|
}
|
||||||
|
0x33: decode RD {
|
||||||
|
0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
0x01: HPriv::wrhprhtstate({{
|
||||||
|
if(Tl == 0)
|
||||||
|
return new IllegalInstruction;
|
||||||
|
Htstate = Rs1 ^ Rs2_or_imm13;
|
||||||
|
}});
|
||||||
|
//0x02 should cause an illegal instruction exception
|
||||||
|
0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
//0x04 should cause an illegal instruction exception
|
||||||
|
0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
//0x06-0x01D should cause an illegal instruction exception
|
||||||
|
0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
|
||||||
|
}
|
||||||
0x34: decode OPF{
|
0x34: decode OPF{
|
||||||
format BasicOperate{
|
format BasicOperate{
|
||||||
0x01: fmovs({{
|
0x01: fmovs({{
|
||||||
|
|
|
@ -119,18 +119,34 @@ let {{
|
||||||
return (header_output, decoder_output, exec_output, decode_block)
|
return (header_output, decoder_output, exec_output, decode_block)
|
||||||
}};
|
}};
|
||||||
|
|
||||||
// Primary format for integer operate instructions:
|
|
||||||
def format Priv(code, *opt_flags) {{
|
def format Priv(code, *opt_flags) {{
|
||||||
checkCode = "!(Pstate<2:2> || Hpstate<2:2>)"
|
checkCode = "!(Pstate<2:> || Hpstate<2:>)"
|
||||||
(header_output, decoder_output,
|
(header_output, decoder_output,
|
||||||
exec_output, decode_block) = doPrivFormat(code,
|
exec_output, decode_block) = doPrivFormat(code,
|
||||||
checkCode, name, Name, opt_flags + ('IprAccessOp',))
|
checkCode, name, Name, opt_flags)
|
||||||
|
}};
|
||||||
|
|
||||||
|
def format NoPriv(code, *opt_flags) {{
|
||||||
|
#Instructions which use this format don't really check for
|
||||||
|
#any particular mode, but the disassembly is performed
|
||||||
|
#using the control registers actual name
|
||||||
|
checkCode = "false"
|
||||||
|
(header_output, decoder_output,
|
||||||
|
exec_output, decode_block) = doPrivFormat(code,
|
||||||
|
checkCode, name, Name, opt_flags)
|
||||||
|
}};
|
||||||
|
|
||||||
|
def format PrivCheck(code, extraCheckCode, *opt_flags) {{
|
||||||
|
checkCode = "(%s) && !(Pstate<2:> || Hpstate<2:>)" % extraCheckCode
|
||||||
|
(header_output, decoder_output,
|
||||||
|
exec_output, decode_block) = doPrivFormat(code,
|
||||||
|
checkCode, name, Name, opt_flags)
|
||||||
}};
|
}};
|
||||||
|
|
||||||
def format HPriv(code, *opt_flags) {{
|
def format HPriv(code, *opt_flags) {{
|
||||||
checkCode = "!Hpstate<2:2>"
|
checkCode = "!Hpstate<2:2>"
|
||||||
(header_output, decoder_output,
|
(header_output, decoder_output,
|
||||||
exec_output, decode_block) = doPrivFormat(code,
|
exec_output, decode_block) = doPrivFormat(code,
|
||||||
checkCode, name, Name, opt_flags + ('IprAccessOp',))
|
checkCode, name, Name, opt_flags)
|
||||||
}};
|
}};
|
||||||
|
|
||||||
|
|
|
@ -54,6 +54,7 @@ output decoder {{
|
||||||
#if defined(linux)
|
#if defined(linux)
|
||||||
#include <fenv.h>
|
#include <fenv.h>
|
||||||
#endif
|
#endif
|
||||||
|
#include <algorithm>
|
||||||
|
|
||||||
using namespace SparcISA;
|
using namespace SparcISA;
|
||||||
}};
|
}};
|
||||||
|
|
|
@ -80,8 +80,6 @@ def operands {{
|
||||||
'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
|
'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
|
||||||
'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
|
'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
|
||||||
'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
|
'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
|
||||||
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
|
|
||||||
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
|
|
||||||
'R0': ('IntReg', 'udw', '0', None, 6),
|
'R0': ('IntReg', 'udw', '0', None, 6),
|
||||||
'R1': ('IntReg', 'udw', '1', None, 7),
|
'R1': ('IntReg', 'udw', '1', None, 7),
|
||||||
'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
|
'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
|
||||||
|
@ -91,24 +89,42 @@ def operands {{
|
||||||
'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
|
'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
|
||||||
'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
|
'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
|
||||||
'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
|
'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
|
||||||
|
'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
|
||||||
|
'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
|
||||||
|
'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
|
||||||
|
'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46),
|
||||||
|
'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
|
||||||
|
'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
|
||||||
|
'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
|
||||||
|
'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
|
||||||
|
'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
|
||||||
|
'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
|
||||||
|
|
||||||
'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43),
|
'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
|
||||||
'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
|
'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
|
||||||
'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
|
'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
|
||||||
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
|
'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
|
||||||
'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47),
|
'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
|
||||||
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48),
|
'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
|
||||||
|
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
|
||||||
|
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
|
||||||
|
'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
|
||||||
|
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 62),
|
||||||
|
'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
|
||||||
|
'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
|
||||||
|
'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
|
||||||
|
'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
|
||||||
|
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
|
||||||
|
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
|
||||||
|
|
||||||
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49),
|
'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
|
||||||
'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50),
|
'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
|
||||||
'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51),
|
'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
|
||||||
'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52),
|
'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
|
||||||
'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53),
|
'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
|
||||||
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54),
|
'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
|
||||||
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55),
|
|
||||||
|
|
||||||
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56),
|
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
|
||||||
'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57),
|
|
||||||
# Mem gets a large number so it's always last
|
# Mem gets a large number so it's always last
|
||||||
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
|
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
|
||||||
|
|
||||||
|
|
|
@ -30,6 +30,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "arch/sparc/miscregfile.hh"
|
#include "arch/sparc/miscregfile.hh"
|
||||||
|
#include "base/bitfield.hh"
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
||||||
#include "config/full_system.hh"
|
#include "config/full_system.hh"
|
||||||
#include "cpu/base.hh"
|
#include "cpu/base.hh"
|
||||||
|
@ -78,8 +79,9 @@ MiscReg MiscRegFile::readReg(int miscReg)
|
||||||
case MISCREG_TICK:
|
case MISCREG_TICK:
|
||||||
return tick;
|
return tick;
|
||||||
case MISCREG_PCR:
|
case MISCREG_PCR:
|
||||||
|
panic("PCR not implemented\n");
|
||||||
case MISCREG_PIC:
|
case MISCREG_PIC:
|
||||||
panic("ASR number %d not implemented\n", miscReg - AsrStart);
|
panic("PIC not implemented\n");
|
||||||
case MISCREG_GSR:
|
case MISCREG_GSR:
|
||||||
return gsr;
|
return gsr;
|
||||||
case MISCREG_SOFTINT:
|
case MISCREG_SOFTINT:
|
||||||
|
@ -154,8 +156,8 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
|
||||||
switch (miscReg) {
|
switch (miscReg) {
|
||||||
case MISCREG_TICK:
|
case MISCREG_TICK:
|
||||||
case MISCREG_PRIVTICK:
|
case MISCREG_PRIVTICK:
|
||||||
return tc->getCpuPtr()->curCycle() - tickFields.counter |
|
return tc->getCpuPtr()->curCycle() - (tick & mask(63)) |
|
||||||
tickFields.npt << 63;
|
(tick & ~(mask(63))) << 63;
|
||||||
case MISCREG_FPRS:
|
case MISCREG_FPRS:
|
||||||
panic("FPU not implemented\n");
|
panic("FPU not implemented\n");
|
||||||
case MISCREG_PCR:
|
case MISCREG_PCR:
|
||||||
|
@ -171,7 +173,7 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
|
||||||
SparcSystem *sys;
|
SparcSystem *sys;
|
||||||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||||
assert(sys != NULL);
|
assert(sys != NULL);
|
||||||
return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
|
return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
|
||||||
#endif
|
#endif
|
||||||
case MISCREG_HVER:
|
case MISCREG_HVER:
|
||||||
return NWindows | MaxTL << 8 | MaxGL << 16;
|
return NWindows | MaxTL << 8 | MaxGL << 16;
|
||||||
|
@ -198,8 +200,9 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
|
||||||
tick = val;
|
tick = val;
|
||||||
break;
|
break;
|
||||||
case MISCREG_PCR:
|
case MISCREG_PCR:
|
||||||
|
panic("PCR not implemented\n");
|
||||||
case MISCREG_PIC:
|
case MISCREG_PIC:
|
||||||
panic("ASR number %d not implemented\n", miscReg - AsrStart);
|
panic("PIC not implemented\n");
|
||||||
case MISCREG_GSR:
|
case MISCREG_GSR:
|
||||||
gsr = val;
|
gsr = val;
|
||||||
break;
|
break;
|
||||||
|
@ -303,12 +306,12 @@ inline void MiscRegFile::setImplicitAsis()
|
||||||
if(tl == 0)
|
if(tl == 0)
|
||||||
{
|
{
|
||||||
implicitInstAsi = implicitDataAsi =
|
implicitInstAsi = implicitDataAsi =
|
||||||
pstateFields.cle ? ASI_PRIMARY_LITTLE : ASI_PRIMARY;
|
(pstate & (1 << 9)) ? ASI_PRIMARY_LITTLE : ASI_PRIMARY;
|
||||||
}
|
}
|
||||||
else if(tl <= MaxPTL)
|
else if(tl <= MaxPTL)
|
||||||
{
|
{
|
||||||
implicitInstAsi = ASI_NUCLEUS;
|
implicitInstAsi = ASI_NUCLEUS;
|
||||||
implicitDataAsi = pstateFields.cle ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS;
|
implicitDataAsi = (pstate & (1 << 9)) ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS;
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
|
@ -328,8 +331,8 @@ void MiscRegFile::setRegWithEffect(int miscReg,
|
||||||
#endif
|
#endif
|
||||||
switch (miscReg) {
|
switch (miscReg) {
|
||||||
case MISCREG_TICK:
|
case MISCREG_TICK:
|
||||||
tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64;
|
tick = tc->getCpuPtr()->curCycle() - val & ~Bit64;
|
||||||
tickFields.npt = val & Bit64 ? 1 : 0;
|
tick |= val & Bit64;
|
||||||
break;
|
break;
|
||||||
case MISCREG_FPRS:
|
case MISCREG_FPRS:
|
||||||
//Configure the fpu based on the fprs
|
//Configure the fpu based on the fprs
|
||||||
|
@ -369,10 +372,10 @@ void MiscRegFile::setRegWithEffect(int miscReg,
|
||||||
if (tickCompare == NULL)
|
if (tickCompare == NULL)
|
||||||
tickCompare = new TickCompareEvent(this, tc);
|
tickCompare = new TickCompareEvent(this, tc);
|
||||||
setReg(miscReg, val);
|
setReg(miscReg, val);
|
||||||
if (tick_cmprFields.int_dis && tickCompare->scheduled())
|
if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
|
||||||
tickCompare->deschedule();
|
tickCompare->deschedule();
|
||||||
time = tick_cmprFields.tick_cmpr - tickFields.counter;
|
time = (tick_cmpr & mask(63)) - (tick & mask(63));
|
||||||
if (!tick_cmprFields.int_dis && time > 0)
|
if (!(tick_cmpr & ~mask(63)) && time > 0)
|
||||||
tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
|
tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
|
@ -390,17 +393,17 @@ void MiscRegFile::setRegWithEffect(int miscReg,
|
||||||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||||
assert(sys != NULL);
|
assert(sys != NULL);
|
||||||
sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
|
sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
|
||||||
stickFields.npt = val & Bit64 ? 1 : 0;
|
stick |= val & Bit64;
|
||||||
break;
|
break;
|
||||||
case MISCREG_STICK_CMPR:
|
case MISCREG_STICK_CMPR:
|
||||||
if (sTickCompare == NULL)
|
if (sTickCompare == NULL)
|
||||||
sTickCompare = new STickCompareEvent(this, tc);
|
sTickCompare = new STickCompareEvent(this, tc);
|
||||||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||||
assert(sys != NULL);
|
assert(sys != NULL);
|
||||||
if (stick_cmprFields.int_dis && sTickCompare->scheduled())
|
if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
|
||||||
sTickCompare->deschedule();
|
sTickCompare->deschedule();
|
||||||
time = stick_cmprFields.tick_cmpr - sys->sysTick;
|
time = (stick_cmpr & mask(63)) - sys->sysTick;
|
||||||
if (!stick_cmprFields.int_dis && time > 0)
|
if (!(stick_cmpr & ~mask(63)) && time > 0)
|
||||||
sTickCompare->schedule(time * Clock::Int::ns);
|
sTickCompare->schedule(time * Clock::Int::ns);
|
||||||
break;
|
break;
|
||||||
case MISCREG_HSTICK_CMPR:
|
case MISCREG_HSTICK_CMPR:
|
||||||
|
@ -408,10 +411,10 @@ void MiscRegFile::setRegWithEffect(int miscReg,
|
||||||
hSTickCompare = new HSTickCompareEvent(this, tc);
|
hSTickCompare = new HSTickCompareEvent(this, tc);
|
||||||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||||
assert(sys != NULL);
|
assert(sys != NULL);
|
||||||
if (hstick_cmprFields.int_dis && hSTickCompare->scheduled())
|
if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
|
||||||
hSTickCompare->deschedule();
|
hSTickCompare->deschedule();
|
||||||
int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick;
|
int64_t time = (hstick_cmpr & mask(63)) - sys->sysTick;
|
||||||
if (!hstick_cmprFields.int_dis && time > 0)
|
if (!(hstick_cmpr & ~mask(63)) && time > 0)
|
||||||
hSTickCompare->schedule(time * Clock::Int::ns);
|
hSTickCompare->schedule(time * Clock::Int::ns);
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -92,8 +92,7 @@ namespace SparcISA
|
||||||
MISCREG_HSTICK_CMPR,
|
MISCREG_HSTICK_CMPR,
|
||||||
|
|
||||||
/** Floating Point Status Register */
|
/** Floating Point Status Register */
|
||||||
MISCREG_FSR,
|
MISCREG_FSR
|
||||||
NumMiscRegs
|
|
||||||
};
|
};
|
||||||
|
|
||||||
// The control registers, broken out into fields
|
// The control registers, broken out into fields
|
||||||
|
@ -102,93 +101,16 @@ namespace SparcISA
|
||||||
private:
|
private:
|
||||||
|
|
||||||
/* ASR Registers */
|
/* ASR Registers */
|
||||||
union {
|
uint64_t y; // Y (used in obsolete multiplication)
|
||||||
uint64_t y; // Y (used in obsolete multiplication)
|
uint8_t ccr; // Condition Code Register
|
||||||
struct {
|
|
||||||
uint64_t value:32; // The actual value stored in y
|
|
||||||
uint64_t :32; // reserved bits
|
|
||||||
} yFields;
|
|
||||||
};
|
|
||||||
union {
|
|
||||||
uint8_t ccr; // Condition Code Register
|
|
||||||
struct {
|
|
||||||
union {
|
|
||||||
uint8_t icc:4; // 32-bit condition codes
|
|
||||||
struct {
|
|
||||||
uint8_t c:1; // Carry
|
|
||||||
uint8_t v:1; // Overflow
|
|
||||||
uint8_t z:1; // Zero
|
|
||||||
uint8_t n:1; // Negative
|
|
||||||
} iccFields;
|
|
||||||
};
|
|
||||||
union {
|
|
||||||
uint8_t xcc:4; // 64-bit condition codes
|
|
||||||
struct {
|
|
||||||
uint8_t c:1; // Carry
|
|
||||||
uint8_t v:1; // Overflow
|
|
||||||
uint8_t z:1; // Zero
|
|
||||||
uint8_t n:1; // Negative
|
|
||||||
} xccFields;
|
|
||||||
};
|
|
||||||
} ccrFields;
|
|
||||||
};
|
|
||||||
uint8_t asi; // Address Space Identifier
|
uint8_t asi; // Address Space Identifier
|
||||||
union {
|
uint64_t tick; // Hardware clock-tick counter
|
||||||
uint64_t tick; // Hardware clock-tick counter
|
uint8_t fprs; // Floating-Point Register State
|
||||||
struct {
|
uint64_t gsr; // General Status Register
|
||||||
int64_t counter:63; // Clock-tick count
|
uint64_t softint;
|
||||||
uint64_t npt:1; // Non-priveleged trap
|
uint64_t tick_cmpr; // Hardware tick compare registers
|
||||||
} tickFields;
|
uint64_t stick; // Hardware clock-tick counter
|
||||||
};
|
uint64_t stick_cmpr; // Hardware tick compare registers
|
||||||
union {
|
|
||||||
uint8_t fprs; // Floating-Point Register State
|
|
||||||
struct {
|
|
||||||
uint8_t dl:1; // Dirty lower
|
|
||||||
uint8_t du:1; // Dirty upper
|
|
||||||
uint8_t fef:1; // FPRS enable floating-Point
|
|
||||||
} fprsFields;
|
|
||||||
};
|
|
||||||
union {
|
|
||||||
uint64_t gsr; //General Status Register
|
|
||||||
struct {
|
|
||||||
uint64_t mask:32;
|
|
||||||
uint64_t :4;
|
|
||||||
uint64_t im:1;
|
|
||||||
uint64_t irnd:2;
|
|
||||||
uint64_t :17;
|
|
||||||
uint64_t scale:5;
|
|
||||||
uint64_t align:3;
|
|
||||||
} gsrFields;
|
|
||||||
};
|
|
||||||
union {
|
|
||||||
uint64_t softint;
|
|
||||||
struct {
|
|
||||||
uint64_t tm:1;
|
|
||||||
uint64_t int_level:14;
|
|
||||||
uint64_t sm:1;
|
|
||||||
} softintFields;
|
|
||||||
};
|
|
||||||
union {
|
|
||||||
uint64_t tick_cmpr; // Hardware tick compare registers
|
|
||||||
struct {
|
|
||||||
uint64_t tick_cmpr:63; // Clock-tick count
|
|
||||||
uint64_t int_dis:1; // Non-priveleged trap
|
|
||||||
} tick_cmprFields;
|
|
||||||
};
|
|
||||||
union {
|
|
||||||
uint64_t stick; // Hardware clock-tick counter
|
|
||||||
struct {
|
|
||||||
int64_t :63; // Not used, storage in SparcSystem
|
|
||||||
uint64_t npt:1; // Non-priveleged trap
|
|
||||||
} stickFields;
|
|
||||||
};
|
|
||||||
union {
|
|
||||||
uint64_t stick_cmpr; // Hardware tick compare registers
|
|
||||||
struct {
|
|
||||||
uint64_t tick_cmpr:63; // Clock-tick count
|
|
||||||
uint64_t int_dis:1; // Non-priveleged trap
|
|
||||||
} stick_cmprFields;
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/* Privileged Registers */
|
/* Privileged Registers */
|
||||||
|
@ -196,37 +118,12 @@ namespace SparcISA
|
||||||
// previous trap level)
|
// previous trap level)
|
||||||
uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
|
uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
|
||||||
// previous trap level)
|
// previous trap level)
|
||||||
union {
|
uint64_t tstate[MaxTL]; // Trap State
|
||||||
uint64_t tstate[MaxTL]; // Trap State
|
|
||||||
struct {
|
|
||||||
//Values are from previous trap level
|
|
||||||
uint64_t cwp:5; // Current Window Pointer
|
|
||||||
uint64_t :3; // Reserved bits
|
|
||||||
uint64_t pstate:13; // Process State
|
|
||||||
uint64_t :3; // Reserved bits
|
|
||||||
uint64_t asi:8; // Address Space Identifier
|
|
||||||
uint64_t ccr:8; // Condition Code Register
|
|
||||||
uint64_t gl:8; // Global level
|
|
||||||
} tstateFields[MaxTL];
|
|
||||||
};
|
|
||||||
uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
|
uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
|
||||||
// on the previous level)
|
// on the previous level)
|
||||||
uint64_t tba; // Trap Base Address
|
uint64_t tba; // Trap Base Address
|
||||||
|
|
||||||
union {
|
uint16_t pstate; // Process State Register
|
||||||
uint16_t pstate; // Process State Register
|
|
||||||
struct {
|
|
||||||
uint16_t :1; // reserved
|
|
||||||
uint16_t ie:1; // Interrupt enable
|
|
||||||
uint16_t priv:1; // Privelege mode
|
|
||||||
uint16_t am:1; // Address mask
|
|
||||||
uint16_t pef:1; // PSTATE enable floating-point
|
|
||||||
uint16_t :1; // reserved2
|
|
||||||
uint16_t mm:2; // Memory Model
|
|
||||||
uint16_t tle:1; // Trap little-endian
|
|
||||||
uint16_t cle:1; // Current little-endian
|
|
||||||
} pstateFields;
|
|
||||||
};
|
|
||||||
uint8_t tl; // Trap Level
|
uint8_t tl; // Trap Level
|
||||||
uint8_t pil; // Process Interrupt Register
|
uint8_t pil; // Process Interrupt Register
|
||||||
uint8_t cwp; // Current Window Pointer
|
uint8_t cwp; // Current Window Pointer
|
||||||
|
@ -234,97 +131,20 @@ namespace SparcISA
|
||||||
uint8_t canrestore; // Restorable windows
|
uint8_t canrestore; // Restorable windows
|
||||||
uint8_t cleanwin; // Clean windows
|
uint8_t cleanwin; // Clean windows
|
||||||
uint8_t otherwin; // Other windows
|
uint8_t otherwin; // Other windows
|
||||||
union {
|
uint8_t wstate; // Window State
|
||||||
uint8_t wstate; // Window State
|
|
||||||
struct {
|
|
||||||
uint8_t normal:3; // Bits TT<4:2> are set to on a normal
|
|
||||||
// register window trap
|
|
||||||
uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
|
|
||||||
// register window trap
|
|
||||||
} wstateFields;
|
|
||||||
};
|
|
||||||
uint8_t gl; // Global level register
|
uint8_t gl; // Global level register
|
||||||
|
|
||||||
|
|
||||||
/** Hyperprivileged Registers */
|
/** Hyperprivileged Registers */
|
||||||
union {
|
uint64_t hpstate; // Hyperprivileged State Register
|
||||||
uint64_t hpstate; // Hyperprivileged State Register
|
uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
|
||||||
struct {
|
|
||||||
uint8_t tlz: 1;
|
|
||||||
uint8_t :1;
|
|
||||||
uint8_t hpriv:1;
|
|
||||||
uint8_t :2;
|
|
||||||
uint8_t red:1;
|
|
||||||
uint8_t :4;
|
|
||||||
uint8_t ibe:1;
|
|
||||||
uint8_t id:1;
|
|
||||||
} hpstateFields;
|
|
||||||
};
|
|
||||||
|
|
||||||
uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register
|
|
||||||
uint64_t hintp;
|
uint64_t hintp;
|
||||||
uint64_t htba; // Hyperprivileged Trap Base Address register
|
uint64_t htba; // Hyperprivileged Trap Base Address register
|
||||||
union {
|
uint64_t hstick_cmpr; // Hardware tick compare registers
|
||||||
uint64_t hstick_cmpr; // Hardware tick compare registers
|
|
||||||
struct {
|
|
||||||
uint64_t tick_cmpr:63; // Clock-tick count
|
|
||||||
uint64_t int_dis:1; // Non-priveleged trap
|
|
||||||
} hstick_cmprFields;
|
|
||||||
};
|
|
||||||
|
|
||||||
uint64_t strandStatusReg; // Per strand status register
|
|
||||||
|
|
||||||
|
uint64_t strandStatusReg;// Per strand status register
|
||||||
|
|
||||||
/** Floating point misc registers. */
|
/** Floating point misc registers. */
|
||||||
union {
|
uint64_t fsr; // Floating-Point State Register
|
||||||
uint64_t fsr; // Floating-Point State Register
|
|
||||||
struct {
|
|
||||||
union {
|
|
||||||
uint64_t cexc:5; // Current excpetion
|
|
||||||
struct {
|
|
||||||
uint64_t nxc:1; // Inexact
|
|
||||||
uint64_t dzc:1; // Divide by zero
|
|
||||||
uint64_t ufc:1; // Underflow
|
|
||||||
uint64_t ofc:1; // Overflow
|
|
||||||
uint64_t nvc:1; // Invalid operand
|
|
||||||
} cexcFields;
|
|
||||||
};
|
|
||||||
union {
|
|
||||||
uint64_t aexc:5; // Accrued exception
|
|
||||||
struct {
|
|
||||||
uint64_t nxc:1; // Inexact
|
|
||||||
uint64_t dzc:1; // Divide by zero
|
|
||||||
uint64_t ufc:1; // Underflow
|
|
||||||
uint64_t ofc:1; // Overflow
|
|
||||||
uint64_t nvc:1; // Invalid operand
|
|
||||||
} aexcFields;
|
|
||||||
};
|
|
||||||
uint64_t fcc0:2; // Floating-Point condtion codes
|
|
||||||
uint64_t :1; // Reserved bits
|
|
||||||
uint64_t qne:1; // Deferred trap queue not empty
|
|
||||||
// with no queue, it should read 0
|
|
||||||
uint64_t ftt:3; // Floating-Point trap type
|
|
||||||
uint64_t ver:3; // Version (of the FPU)
|
|
||||||
uint64_t :2; // Reserved bits
|
|
||||||
uint64_t ns:1; // Nonstandard floating point
|
|
||||||
union {
|
|
||||||
uint64_t tem:5; // Trap Enable Mask
|
|
||||||
struct {
|
|
||||||
uint64_t nxm:1; // Inexact
|
|
||||||
uint64_t dzm:1; // Divide by zero
|
|
||||||
uint64_t ufm:1; // Underflow
|
|
||||||
uint64_t ofm:1; // Overflow
|
|
||||||
uint64_t nvm:1; // Invalid operand
|
|
||||||
} temFields;
|
|
||||||
};
|
|
||||||
uint64_t :2; // Reserved bits
|
|
||||||
uint64_t rd:2; // Rounding direction
|
|
||||||
uint64_t fcc1:2; // Floating-Point condition codes
|
|
||||||
uint64_t fcc2:2; // Floating-Point condition codes
|
|
||||||
uint64_t fcc3:2; // Floating-Point condition codes
|
|
||||||
uint64_t :26; // Reserved bits
|
|
||||||
} fsrFields;
|
|
||||||
};
|
|
||||||
|
|
||||||
ASI implicitInstAsi;
|
ASI implicitInstAsi;
|
||||||
ASI implicitDataAsi;
|
ASI implicitDataAsi;
|
||||||
|
@ -386,8 +206,8 @@ namespace SparcISA
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
|
|
||||||
bool isHyperPriv() { return hpstateFields.hpriv; }
|
bool isHyperPriv() { return (hpstate & (1 << 2)); }
|
||||||
bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
|
bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
|
||||||
bool isNonPriv() { return !isPriv(); }
|
bool isNonPriv() { return !isPriv(); }
|
||||||
inline void setImplicitAsis();
|
inline void setImplicitAsis();
|
||||||
};
|
};
|
||||||
|
|
Loading…
Reference in a new issue