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set the softint appropriately on an timer compare interrupt

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there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly

src/arch/sparc/faults.cc:
    there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.hh:
    correct protection defines
src/arch/sparc/ua2005.cc:
    set the softint appropriately on an timer compare interrupt

--HG--
extra : convert_revision : f41c10ec78db973b3f856c70b58a17f83b60bbe2
This commit is contained in:
Ali Saidi 2007-01-05 15:04:17 -05:00
parent b0f11f8f81
commit 4a8078192d
3 changed files with 8 additions and 7 deletions
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2
src/arch/sparc/faults.cc
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@ -197,7 +197,7 @@ template<> SparcFaultBase::FaultVals
template<> SparcFaultBase::FaultVals template<> SparcFaultBase::FaultVals
SparcFault<InterruptLevelN>::vals = SparcFault<InterruptLevelN>::vals =
{"interrupt_level_n", 0x041, 0, {P, P, SH}}; {"interrupt_level_n", 0x040, 0, {P, P, SH}};
template<> SparcFaultBase::FaultVals template<> SparcFaultBase::FaultVals
SparcFault<HstickMatch>::vals = SparcFault<HstickMatch>::vals =

6
src/arch/sparc/faults.hh
View file

@ -29,8 +29,8 @@
* Kevin Lim * Kevin Lim
*/ */
#ifndef __ALPHA_FAULTS_HH__ #ifndef __SPARC_FAULTS_HH__
#define __ALPHA_FAULTS_HH__ #define __SPARC_FAULTS_HH__
#include "sim/faults.hh" #include "sim/faults.hh"
@ -280,4 +280,4 @@ static inline Fault genAlignmentFault()
} // SparcISA namespace } // SparcISA namespace
#endif // __FAULTS_HH__ #endif // __SPARC_FAULTS_HH__

7
src/arch/sparc/ua2005.cc
View file

@ -73,7 +73,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
setReg(miscReg, val); setReg(miscReg, val);
if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
sTickCompare->deschedule(); sTickCompare->deschedule();
time = ((int64_t)(stick_cmpr & mask(63)) + (int64_t)stick) - time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
tc->getCpuPtr()->instCount(); tc->getCpuPtr()->instCount();
if (!(stick_cmpr & ~mask(63)) && time > 0) if (!(stick_cmpr & ~mask(63)) && time > 0)
sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick); sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
@ -197,14 +197,15 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
// we're actually at the correct cycle or we need to wait a little while // we're actually at the correct cycle or we need to wait a little while
// more // more
int ticks; int ticks;
ticks = (stick_cmpr & mask(63)) - tc->getCpuPtr()->instCount(); ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
tc->getCpuPtr()->instCount();
assert(ticks >= 0 && "stick compare missed interrupt cycle"); assert(ticks >= 0 && "stick compare missed interrupt cycle");
if (ticks == 0) { if (ticks == 0) {
DPRINTF(Timer, "STick compare cycle reached at %#x\n", DPRINTF(Timer, "STick compare cycle reached at %#x\n",
(stick_cmpr & mask(63))); (stick_cmpr & mask(63)));
tc->getCpuPtr()->checkInterrupts = true; tc->getCpuPtr()->checkInterrupts = true;
softint |= ULL(1) << 16;
} else } else
sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
} }