mem: Change AbstractMemory defaults to match the common case
This patch changes the default parameter value of conf_table_reported to match the common case. It also simplifies the regression and config scripts to reflect this change.
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e553844efc
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7 changed files with 17 additions and 18 deletions
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@ -174,8 +174,7 @@ CacheConfig.config_cache(options, test_sys)
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# Create the appropriate memory controllers and connect them to the
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# memory bus
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test_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True)
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for r in test_sys.mem_ranges]
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test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
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for i in xrange(len(test_sys.mem_ctrls)):
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test_sys.mem_ctrls[i].port = test_sys.membus.master
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@ -225,7 +224,7 @@ if len(bm) == 2:
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# Create the appropriate memory controllers and connect them to the
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# memory bus
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drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True)
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drive_sys.mem_ctrls = [DriveMemClass(range = r)
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for r in drive_sys.mem_ranges]
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for i in xrange(len(drive_sys.mem_ctrls)):
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drive_sys.mem_ctrls[i].port = drive_sys.membus.master
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@ -128,9 +128,7 @@ for (i, cpu) in enumerate(system.cpu):
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# Create the appropriate memory controllers and connect them to the
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# PIO bus
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system.mem_ctrls = [TestMemClass(range = r,
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conf_table_reported = True)
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for r in system.mem_ranges]
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system.mem_ctrls = [TestMemClass(range = r) for r in system.mem_ranges]
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for i in xrange(len(system.physmem)):
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system.mem_ctrls[i].port = system.piobus.master
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@ -159,8 +159,8 @@ class RealView(Platform):
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max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform")
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def setupBootLoader(self, mem_bus, cur_sys, loc):
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self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'),
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size = '64MB'))
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self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
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conf_table_reported = False)
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self.nvmem.port = mem_bus.master
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cur_sys.boot_loader = loc('boot.arm')
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@ -357,7 +357,8 @@ class VExpress_EMM(RealView):
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InterruptLine=2, InterruptPin=2)
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vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'))
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vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
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conf_table_reported = False)
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rtc = PL031(pio_addr=0x1C170000, int_num=36)
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l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
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@ -372,7 +373,8 @@ class VExpress_EMM(RealView):
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mmc_fake = AmbaFake(pio_addr=0x1c050000)
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def setupBootLoader(self, mem_bus, cur_sys, loc):
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self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
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self.nvmem = SimpleMemory(range = AddrRange('64MB'),
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conf_table_reported = False)
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self.nvmem.port = mem_bus.master
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cur_sys.boot_loader = loc('boot_emm.arm')
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cur_sys.atags_addr = 0x80000100
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@ -46,7 +46,10 @@ class AbstractMemory(MemObject):
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type = 'AbstractMemory'
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abstract = True
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cxx_header = "mem/abstract_mem.hh"
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range = Param.AddrRange(AddrRange('128MB'), "Address range")
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# A default memory size of 128 MB (starting at 0) is used to
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# simplify the regressions
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range = Param.AddrRange('128MB', "Address range (potentially interleaved)")
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null = Param.Bool(False, "Do not store data, always return zero")
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# All memories are passed to the global physical memory, and
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@ -57,4 +60,4 @@ class AbstractMemory(MemObject):
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# Should the bootloader include this memory when passing
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# configuration information about the physical memory layout to
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# the kernel, e.g. using ATAG or ACPI
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conf_table_reported = Param.Bool(False, "Report to configuration table")
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conf_table_reported = Param.Bool(True, "Report to configuration table")
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@ -228,8 +228,7 @@ class BaseFSSystem(BaseSystem):
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# create the memory controllers and connect them, stick with
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# the physmem name to avoid bumping all the reference stats
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system.physmem = [self.mem_class(range = r,
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conf_table_reported = True)
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system.physmem = [self.mem_class(range = r)
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for r in system.mem_ranges]
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for i in xrange(len(system.physmem)):
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system.physmem[i].port = system.membus.master
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@ -89,8 +89,7 @@ for (i, cpu) in enumerate(system.cpu):
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# Set access_phys_mem to True for ruby port
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system.ruby._cpu_ruby_ports[i].access_phys_mem = True
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system.physmem = [DDR3_1600_x64(range = r,
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conf_table_reported = True)
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system.physmem = [DDR3_1600_x64(range = r)
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for r in system.mem_ranges]
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for i in xrange(len(system.physmem)):
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system.physmem[i].port = system.piobus.master
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@ -45,8 +45,7 @@ cpu.connectAllPorts(system.membus)
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# create the memory controllers and connect them, stick with
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# the physmem name to avoid bumping all the reference stats
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system.physmem = [SimpleMemory(range = r,
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conf_table_reported = True)
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system.physmem = [SimpleMemory(range = r)
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for r in system.mem_ranges]
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for i in xrange(len(system.physmem)):
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system.physmem[i].port = system.membus.master
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