Update stats for brk fix (cset f28f020f3006).
This commit is contained in:
Steve Reinhardt
parent
3087be945d
commit
47789cc974
2 changed files with 57 additions and 59 deletions
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@ -1,13 +1,13 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1243989 # Simulator instruction rate (inst/s)
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host_mem_usage 207864 # Number of bytes of host memory used
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host_seconds 155.50 # Real time elapsed on the host
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host_tick_rate 1740014863 # Simulator tick rate (ticks/s)
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host_inst_rate 1229412 # Simulator instruction rate (inst/s)
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host_mem_usage 207888 # Number of bytes of host memory used
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host_seconds 157.35 # Real time elapsed on the host
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host_tick_rate 1719613407 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 193444769 # Number of instructions simulated
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sim_seconds 0.270579 # Number of seconds simulated
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sim_ticks 270578958000 # Number of ticks simulated
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sim_ticks 270578573000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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@ -31,16 +31,16 @@ system.cpu.dcache.SwapReq_mshr_misses 2 # nu
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system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 18975331 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 62048000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_hits 18975338 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1108 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 58724000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1108 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 48472.729627 # Average number of references to valid blocks.
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system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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@ -49,14 +49,14 @@ system.cpu.dcache.cache_copies 0 # nu
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system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 76709902 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 89936000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_hits 76709909 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 89544000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1606 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses 1599 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 85118000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency 84747000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1606 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses 1599 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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@ -64,14 +64,14 @@ system.cpu.dcache.overall_accesses 76711508 # nu
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system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 76709902 # number of overall hits
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system.cpu.dcache.overall_miss_latency 89936000 # number of overall miss cycles
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system.cpu.dcache.overall_hits 76709909 # number of overall hits
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system.cpu.dcache.overall_miss_latency 89544000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 1606 # number of overall misses
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system.cpu.dcache.overall_misses 1599 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 85118000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency 84747000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1606 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses 1599 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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@ -83,13 +83,13 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 26 # number of replacements
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system.cpu.dcache.sampled_refs 1583 # Sample count of references to valid blocks.
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system.cpu.dcache.replacements 2 # number of replacements
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system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 1235.200907 # Cycle average of tags in use
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system.cpu.dcache.total_refs 76732331 # Total number of references to valid blocks.
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system.cpu.dcache.tagsinuse 1237.193452 # Cycle average of tags in use
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system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 23 # number of writebacks
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system.cpu.dcache.writebacks 2 # number of writebacks
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system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency
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@ -148,20 +148,20 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
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system.cpu.icache.replacements 10362 # number of replacements
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system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1591.567399 # Cycle average of tags in use
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system.cpu.icache.tagsinuse 1591.566927 # Cycle average of tags in use
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system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 1085 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 56420000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 1085 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 43400000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 1085 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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@ -181,42 +181,42 @@ system.cpu.l2cache.UpgradeReq_misses 25 # nu
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 23 # number of Writeback hits
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system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 2.127019 # Average number of references to valid blocks.
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system.cpu.l2cache.avg_refs 2.134332 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 13871 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 269360000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.373441 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 5180 # number of demand (read+write) misses
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system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 207200000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.373441 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 5180 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 13871 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 8691 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 269360000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.373441 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 5180 # number of overall misses
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system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 5173 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 207200000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.373441 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 5180 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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@ -229,14 +229,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
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system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 4086 # Sample count of references to valid blocks.
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system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 2657.336317 # Cycle average of tags in use
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system.cpu.l2cache.tagsinuse 2657.329033 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 541157916 # number of cpu cycles simulated
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system.cpu.numCycles 541157146 # number of cpu cycles simulated
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system.cpu.num_insts 193444769 # Number of instructions executed
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system.cpu.num_refs 76733959 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 401 # Number of system calls
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@ -5,14 +5,12 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Nov 5 2008 22:40:47
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M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
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M5 commit date Wed Nov 05 16:19:17 2008 -0500
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M5 started Nov 5 2008 22:41:20
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M5 compiled Nov 17 2008 13:45:49
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M5 revision 5749:7015e400bd1deffa6e51e839baf2ed6d9bd3e31f
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M5 commit date Sat Nov 15 23:42:11 2008 -0500
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M5 started Nov 17 2008 13:46:11
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M5 executing on zizzer
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command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-timing
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Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
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Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@ -28,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz
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91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
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106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
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122 123 124 Exiting @ tick 270578958000 because target called exit()
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122 123 124 Exiting @ tick 270578573000 because target called exit()
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