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arm: Mark v7 cbz instructions as direct branches

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v7 cbz/cbnz instructions were improperly marked as indirect branches.
This commit is contained in:
Mitch Hayenga 2014-09-03 07:42:40 -04:00
parent 4f13f676aa
commit 476c6fe368
2 changed files with 12 additions and 5 deletions
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11
src/arch/arm/isa/insts/branch.isa
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@ -1,6 +1,6 @@
// -*- mode:c++ -*- // -*- mode:c++ -*-
// Copyright (c) 2010-2012 ARM Limited // Copyright (c) 2010-2012, 2014 ARM Limited
// All rights reserved // All rights reserved
// //
// The license below extends only to copyright in the software and shall // The license below extends only to copyright in the software and shall
@ -174,12 +174,15 @@ let {{
#CBNZ, CBZ. These are always unconditional as far as predicates #CBNZ, CBZ. These are always unconditional as far as predicates
for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")): for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")):
code = 'NPC = (uint32_t)(PC + imm);\n' code = 'NPC = (uint32_t)(PC + imm);\n'
br_tgt_code = '''pcs.instNPC((uint32_t)(branchPC.instPC() + imm));'''
predTest = "Op1 %(test)s 0" % {"test": test} predTest = "Op1 %(test)s 0" % {"test": test}
iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg", iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
{"code": code, "predicate_test": predTest}, {"code": code, "predicate_test": predTest,
["IsIndirectControl"]) "brTgtCode" : br_tgt_code},
["IsDirectControl"])
header_output += BranchImmRegDeclare.subst(iop) header_output += BranchImmRegDeclare.subst(iop)
decoder_output += BranchImmRegConstructor.subst(iop) decoder_output += BranchImmRegConstructor.subst(iop) + \
BranchTarget.subst(iop)
exec_output += PredOpExecute.subst(iop) exec_output += PredOpExecute.subst(iop)
#TBB, TBH #TBB, TBH

6
src/arch/arm/isa/templates/branch.isa
View file

@ -1,6 +1,6 @@
// -*- mode:c++ -*- // -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited // Copyright (c) 2010, 2014 ARM Limited
// All rights reserved // All rights reserved
// //
// The license below extends only to copyright in the software and shall // The license below extends only to copyright in the software and shall
@ -212,6 +212,10 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, %(class_name)s(ExtMachInst machInst,
int32_t imm, IntRegIndex _op1); int32_t imm, IntRegIndex _op1);
%(BasicExecDeclare)s %(BasicExecDeclare)s
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
/// Explicitly import the otherwise hidden branchTarget
using StaticInst::branchTarget;
}; };
}}; }};