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arm: Bootloader fix for v8 over 16 cores

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Previous code used a smaller 4 bit mask to test the MPIDR-EL1 register.
The bitmask was extended to support greater than 16 cores.
This commit is contained in:
Karthik Sangaiah 2015-07-15 14:43:35 +01:00
parent 6fa936b021
commit 47326f5422
1 changed files with 13 additions and 4 deletions
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17
system/arm/aarch64_bootloader/boot.S
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@ -34,8 +34,12 @@ _start:
* registers. * registers.
*/ */
mrs x0, mpidr_el1 mrs x0, mpidr_el1
tst x0, #15 // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
b.ne 1f // secondary CPU // Test the the MPIDR_EL1 register against 0xff00ffffff to
// extract the primary CPU.
ldr x1, =0xff00ffffff
tst x0, x1 // check for cpuid==zero
b.ne 1f // secondary CPU
ldr x1, =GIC_DIST_BASE // GICD_CTLR ldr x1, =GIC_DIST_BASE // GICD_CTLR
mov w0, #3 // EnableGrp0 | EnableGrp1 mov w0, #3 // EnableGrp0 | EnableGrp1
@ -77,8 +81,13 @@ start_ns:
mov x3, xzr mov x3, xzr
mrs x4, mpidr_el1 mrs x4, mpidr_el1
tst x4, #15 // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
b.eq 2f // Test the the MPIDR_EL1 register against 0xff00ffffff to
// extract the primary CPU.
ldr x1, =0xff00ffffff
tst x4, x1 // check for cpuid==zero
mov x1, xzr // load previous 'xzr' value back to x1
b.eq 2f // secondary CPU
/* /*
* Secondary CPUs * Secondary CPUs