ruby: eliminate type uint64 and int64
These types are being replaced with uint64_t and int64_t.
This commit is contained in:
parent
e9d6bf5e35
commit
4727fc26f8
32 changed files with 116 additions and 122 deletions
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@ -109,9 +109,9 @@ class RubyDirectedTester : public MemObject
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RubyDirectedTester(const RubyDirectedTester& obj);
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RubyDirectedTester& operator=(const RubyDirectedTester& obj);
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uint64 m_requests_completed;
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uint64_t m_requests_completed;
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std::vector<MasterPort*> ports;
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uint64 m_requests_to_complete;
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uint64_t m_requests_to_complete;
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DirectedGenerator* generator;
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};
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@ -143,10 +143,10 @@ class RubyTester : public MemObject
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std::vector<Cycles> m_last_progress_vector;
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int m_num_cpus;
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uint64 m_checks_completed;
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uint64_t m_checks_completed;
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std::vector<MasterPort*> writePorts;
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std::vector<MasterPort*> readPorts;
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uint64 m_checks_to_complete;
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uint64_t m_checks_to_complete;
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int m_deadlock_threshold;
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int m_num_writers;
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int m_num_readers;
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@ -84,7 +84,7 @@ Histogram::doubleBinSize()
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}
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void
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Histogram::add(int64 value)
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Histogram::add(int64_t value)
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{
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assert(value >= 0);
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m_max = max(m_max, value);
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@ -40,7 +40,7 @@ class Histogram
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Histogram(int binsize = 1, uint32_t bins = 50);
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~Histogram();
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void add(int64 value);
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void add(int64_t value);
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void add(Histogram& hist);
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void doubleBinSize();
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@ -51,10 +51,10 @@ class Histogram
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uint64_t size() const { return m_count; }
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uint32_t getBins() const { return m_data.size(); }
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int getBinSize() const { return m_binsize; }
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int64 getTotal() const { return m_sumSamples; }
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int64_t getTotal() const { return m_sumSamples; }
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uint64_t getSquaredTotal() const { return m_sumSquaredSamples; }
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uint64_t getData(int index) const { return m_data[index]; }
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int64 getMax() const { return m_max; }
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int64_t getMax() const { return m_max; }
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void printWithMultiplier(std::ostream& out, double multiplier) const;
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void printPercent(std::ostream& out) const;
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@ -62,12 +62,12 @@ class Histogram
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private:
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std::vector<uint64_t> m_data;
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int64 m_max; // the maximum value seen so far
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int64_t m_max; // the maximum value seen so far
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uint64_t m_count; // the number of elements added
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int m_binsize; // the size of each bucket
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uint32_t m_largest_bin; // the largest bin used
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int64 m_sumSamples; // the sum of all samples
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int64_t m_sumSamples; // the sum of all samples
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uint64_t m_sumSquaredSamples; // the sum of the square of all samples
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double getStandardDeviation() const;
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@ -30,9 +30,6 @@
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#ifndef TYPEDEFINES_H
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#define TYPEDEFINES_H
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typedef unsigned long long uint64;
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typedef long long int64;
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typedef unsigned int LinkID;
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typedef unsigned int NodeID;
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typedef unsigned int SwitchID;
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@ -507,8 +507,8 @@ H3BloomFilter::print(ostream& out) const
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int
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H3BloomFilter::get_index(Addr addr, int i)
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{
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uint64 x = makeLineAddress(addr);
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// uint64 y = (x*mults_list[i] + adds_list[i]) % primes_list[i];
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uint64_t x = makeLineAddress(addr);
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// uint64_t y = (x*mults_list[i] + adds_list[i]) % primes_list[i];
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int y = hash_H3(x,i);
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if (isParallel) {
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@ -519,10 +519,10 @@ H3BloomFilter::get_index(Addr addr, int i)
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}
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int
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H3BloomFilter::hash_H3(uint64 value, int index)
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H3BloomFilter::hash_H3(uint64_t value, int index)
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{
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uint64 mask = 1;
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uint64 val = value;
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uint64_t mask = 1;
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uint64_t val = value;
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int result = 0;
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for (int i = 0; i < 64; i++) {
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@ -68,7 +68,7 @@ class H3BloomFilter : public AbstractBloomFilter
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private:
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int get_index(Addr addr, int hashNumber);
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int hash_H3(uint64 value, int index);
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int hash_H3(uint64_t value, int index);
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std::vector<int> m_filter;
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int m_filter_size;
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@ -171,7 +171,7 @@ MultiBitSelBloomFilter::get_index(Addr addr, int i)
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// m_skip_bits is used to perform BitSelect after skipping some
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// bits. Used to simulate BitSel hashing on larger than cache-line
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// granularities
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uint64 x = (makeLineAddress(addr) >> m_skip_bits);
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uint64_t x = (makeLineAddress(addr) >> m_skip_bits);
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int y = hash_bitsel(x, i, m_num_hashes, 30, m_filter_size_bits);
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//36-bit addresses, 6-bit cache lines
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@ -183,10 +183,10 @@ MultiBitSelBloomFilter::get_index(Addr addr, int i)
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}
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int
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MultiBitSelBloomFilter::hash_bitsel(uint64 value, int index, int jump,
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MultiBitSelBloomFilter::hash_bitsel(uint64_t value, int index, int jump,
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int maxBits, int numBits)
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{
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uint64 mask = 1;
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uint64_t mask = 1;
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int result = 0;
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int bit, i;
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@ -68,7 +68,7 @@ class MultiBitSelBloomFilter : public AbstractBloomFilter
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private:
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int get_index(Addr addr, int hashNumber);
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int hash_bitsel(uint64 value, int index, int jump, int maxBits,
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int hash_bitsel(uint64_t value, int index, int jump, int maxBits,
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int numBits);
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std::vector<int> m_filter;
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@ -184,7 +184,7 @@ class MessageBuffer : public SimObject
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int m_not_avail_count; // count the # of times I didn't have N
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// slots available
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uint64 m_msg_counter;
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uint64_t m_msg_counter;
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int m_priority_rank;
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const bool m_strict_fifo;
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const bool m_randomization;
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@ -67,12 +67,12 @@ class AccessTraceForAddress
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private:
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Addr m_addr;
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uint64 m_loads;
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uint64 m_stores;
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uint64 m_atomics;
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uint64 m_total;
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uint64 m_user;
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uint64 m_sharing;
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uint64_t m_loads;
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uint64_t m_stores;
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uint64_t m_atomics;
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uint64_t m_total;
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uint64_t m_user;
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uint64_t m_sharing;
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Set m_touched_by;
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Histogram* m_histogram_ptr;
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};
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@ -67,7 +67,7 @@ printSorted(ostream& out, int num_of_sequencers, const AddressMap &record_map,
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{
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const int records_printed = 100;
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uint64 misses = 0;
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uint64_t misses = 0;
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std::vector<const AccessTraceForAddress *> sorted;
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AddressMap::const_iterator i = record_map.begin();
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@ -95,8 +95,8 @@ printSorted(ostream& out, int num_of_sequencers, const AddressMap &record_map,
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Histogram all_records_log(-1);
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// Allows us to track how many lines where touched by n processors
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std::vector<int64> m_touched_vec;
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std::vector<int64> m_touched_weighted_vec;
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std::vector<int64_t> m_touched_vec;
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std::vector<int64_t> m_touched_weighted_vec;
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m_touched_vec.resize(num_of_sequencers+1);
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m_touched_weighted_vec.resize(num_of_sequencers+1);
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for (int j = 0; j < m_touched_vec.size(); j++) {
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@ -75,7 +75,7 @@ class AddressProfiler
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AddressProfiler(const AddressProfiler& obj);
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AddressProfiler& operator=(const AddressProfiler& obj);
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int64 m_sharing_miss_counter;
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int64_t m_sharing_miss_counter;
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AddressMap m_dataAccessTrace;
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AddressMap m_macroBlockAccessTrace;
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@ -33,7 +33,7 @@ using namespace std;
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bool StoreTrace::s_init = false; // Total number of store lifetimes of
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// all lines
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int64 StoreTrace::s_total_samples = 0; // Total number of store
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int64_t StoreTrace::s_total_samples = 0; // Total number of store
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// lifetimes of all lines
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Histogram* StoreTrace::s_store_count_ptr = NULL;
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Histogram* StoreTrace::s_store_first_to_stolen_ptr = NULL;
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@ -53,7 +53,7 @@ class StoreTrace
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private:
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static bool s_init;
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static int64 s_total_samples; // Total number of store lifetimes
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static int64_t s_total_samples; // Total number of store lifetimes
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// of all lines
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static Histogram* s_store_count_ptr;
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static Histogram* s_store_first_to_stolen_ptr;
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@ -66,7 +66,7 @@ class StoreTrace
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Tick m_last_store;
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int m_stores_this_interval;
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int64 m_total_samples; // Total number of store lifetimes of this line
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int64_t m_total_samples; // Total number of store lifetimes of this line
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Histogram m_store_count;
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Histogram m_store_first_to_stolen;
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Histogram m_store_last_to_stolen;
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@ -66,7 +66,7 @@ AbstractReplacementPolicy::~AbstractReplacementPolicy()
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}
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Tick
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AbstractReplacementPolicy::getLastAccess(int64 set, int64 way)
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AbstractReplacementPolicy::getLastAccess(int64_t set, int64_t way)
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{
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return m_last_ref_ptr[set][way];
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}
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@ -44,13 +44,13 @@ class AbstractReplacementPolicy : public SimObject
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virtual ~AbstractReplacementPolicy();
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/* touch a block. a.k.a. update timestamp */
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virtual void touch(int64 set, int64 way, Tick time) = 0;
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virtual void touch(int64_t set, int64_t way, Tick time) = 0;
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/* returns the way to replace */
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virtual int64 getVictim(int64 set) const = 0;
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virtual int64_t getVictim(int64_t set) const = 0;
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/* get the time of the last access */
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Tick getLastAccess(int64 set, int64 way);
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Tick getLastAccess(int64_t set, int64_t way);
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virtual bool useOccupancy() const { return false; }
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@ -49,7 +49,7 @@ BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,
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}
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bool
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BankedArray::tryAccess(int64 idx)
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BankedArray::tryAccess(int64_t idx)
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{
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if (accessLatency == 0)
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return true;
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@ -65,7 +65,7 @@ BankedArray::tryAccess(int64 idx)
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}
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void
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BankedArray::reserve(int64 idx)
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BankedArray::reserve(int64_t idx)
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{
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if (accessLatency == 0)
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return;
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@ -91,7 +91,7 @@ BankedArray::reserve(int64 idx)
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}
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unsigned int
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BankedArray::mapIndexToBank(int64 idx)
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BankedArray::mapIndexToBank(int64_t idx)
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{
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if (banks == 1) {
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return 0;
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@ -51,7 +51,7 @@ class BankedArray
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{
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public:
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AccessRecord() : idx(0), startAccess(0), endAccess(0) {}
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int64 idx;
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int64_t idx;
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Tick startAccess;
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Tick endAccess;
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};
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@ -60,7 +60,7 @@ class BankedArray
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// otherwise, schedule the event and wait for it to complete
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std::vector<AccessRecord> busyBanks;
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unsigned int mapIndexToBank(int64 idx);
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unsigned int mapIndexToBank(int64_t idx);
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public:
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BankedArray(unsigned int banks, Cycles accessLatency,
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@ -68,9 +68,9 @@ class BankedArray
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// Note: We try the access based on the cache index, not the address
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// This is so we don't get aliasing on blocks being replaced
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bool tryAccess(int64 idx);
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bool tryAccess(int64_t idx);
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void reserve(int64 idx);
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void reserve(int64_t idx);
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Cycles getLatency() const { return accessLatency; }
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};
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@ -98,7 +98,7 @@ CacheMemory::~CacheMemory()
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}
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// convert a Address to its location in the cache
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int64
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int64_t
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CacheMemory::addressToCacheSet(Addr address) const
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{
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assert(address == makeLineAddress(address));
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@ -109,7 +109,7 @@ CacheMemory::addressToCacheSet(Addr address) const
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// Given a cache index: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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int
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CacheMemory::findTagInSet(int64 cacheSet, Addr tag) const
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CacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const
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{
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assert(tag == makeLineAddress(tag));
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// search the set for the tags
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@ -124,7 +124,7 @@ CacheMemory::findTagInSet(int64 cacheSet, Addr tag) const
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// Given a cache index: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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int
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CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet,
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CacheMemory::findTagInSetIgnorePermissions(int64_t cacheSet,
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Addr tag) const
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{
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assert(tag == makeLineAddress(tag));
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@ -164,7 +164,7 @@ CacheMemory::tryCacheAccess(Addr address, RubyRequestType type,
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{
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assert(address == makeLineAddress(address));
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DPRINTF(RubyCache, "address: %s\n", address);
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int64 cacheSet = addressToCacheSet(address);
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if (loc != -1) {
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// Do we even have a tag match?
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@ -191,7 +191,7 @@ CacheMemory::testCacheAccess(Addr address, RubyRequestType type,
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{
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assert(address == makeLineAddress(address));
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DPRINTF(RubyCache, "address: %s\n", address);
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int64 cacheSet = addressToCacheSet(address);
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if (loc != -1) {
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@ -213,7 +213,7 @@ bool
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CacheMemory::isTagPresent(Addr address) const
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{
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assert(address == makeLineAddress(address));
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int64 cacheSet = addressToCacheSet(address);
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if (loc == -1) {
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@ -233,7 +233,7 @@ CacheMemory::cacheAvail(Addr address) const
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{
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assert(address == makeLineAddress(address));
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int64 cacheSet = addressToCacheSet(address);
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int64_t cacheSet = addressToCacheSet(address);
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for (int i = 0; i < m_cache_assoc; i++) {
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AbstractCacheEntry* entry = m_cache[cacheSet][i];
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@ -259,7 +259,7 @@ CacheMemory::allocate(Addr address, AbstractCacheEntry* entry, bool touch)
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DPRINTF(RubyCache, "address: %s\n", address);
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// Find the first open slot
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int64 cacheSet = addressToCacheSet(address);
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int64_t cacheSet = addressToCacheSet(address);
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std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet];
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for (int i = 0; i < m_cache_assoc; i++) {
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if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) {
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@ -287,7 +287,7 @@ CacheMemory::deallocate(Addr address)
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assert(address == makeLineAddress(address));
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assert(isTagPresent(address));
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DPRINTF(RubyCache, "address: %s\n", address);
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int64 cacheSet = addressToCacheSet(address);
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if (loc != -1) {
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delete m_cache[cacheSet][loc];
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@ -303,7 +303,7 @@ CacheMemory::cacheProbe(Addr address) const
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assert(address == makeLineAddress(address));
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assert(!cacheAvail(address));
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int64 cacheSet = addressToCacheSet(address);
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int64_t cacheSet = addressToCacheSet(address);
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return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]->
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m_Address;
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}
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@ -313,7 +313,7 @@ AbstractCacheEntry*
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CacheMemory::lookup(Addr address)
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{
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assert(address == makeLineAddress(address));
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int64 cacheSet = addressToCacheSet(address);
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if(loc == -1) return NULL;
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return m_cache[cacheSet][loc];
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@ -324,7 +324,7 @@ const AbstractCacheEntry*
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CacheMemory::lookup(Addr address) const
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{
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assert(address == makeLineAddress(address));
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int64 cacheSet = addressToCacheSet(address);
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if(loc == -1) return NULL;
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return m_cache[cacheSet][loc];
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@ -334,7 +334,7 @@ CacheMemory::lookup(Addr address) const
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void
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||||
CacheMemory::setMRU(Addr address)
|
||||
{
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int64_t cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
|
||||
if(loc != -1)
|
||||
|
@ -344,9 +344,9 @@ CacheMemory::setMRU(Addr address)
|
|||
void
|
||||
CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const
|
||||
{
|
||||
uint64 warmedUpBlocks = 0;
|
||||
uint64 totalBlocks M5_VAR_USED = (uint64)m_cache_num_sets
|
||||
* (uint64)m_cache_assoc;
|
||||
uint64_t warmedUpBlocks = 0;
|
||||
uint64_t totalBlocks M5_VAR_USED = (uint64_t)m_cache_num_sets *
|
||||
(uint64_t)m_cache_assoc;
|
||||
|
||||
for (int i = 0; i < m_cache_num_sets; i++) {
|
||||
for (int j = 0; j < m_cache_assoc; j++) {
|
||||
|
@ -376,8 +376,7 @@ CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const
|
|||
|
||||
DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks"
|
||||
"recorded %.2f%% \n", name().c_str(), warmedUpBlocks,
|
||||
(uint64)m_cache_num_sets * (uint64)m_cache_assoc,
|
||||
(float(warmedUpBlocks)/float(totalBlocks))*100.0);
|
||||
totalBlocks, (float(warmedUpBlocks) / float(totalBlocks)) * 100.0);
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -410,7 +409,7 @@ CacheMemory::setLocked(Addr address, int context)
|
|||
{
|
||||
DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
|
||||
assert(address == makeLineAddress(address));
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int64_t cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
assert(loc != -1);
|
||||
m_cache[cacheSet][loc]->setLocked(context);
|
||||
|
@ -421,7 +420,7 @@ CacheMemory::clearLocked(Addr address)
|
|||
{
|
||||
DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
|
||||
assert(address == makeLineAddress(address));
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int64_t cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
assert(loc != -1);
|
||||
m_cache[cacheSet][loc]->clearLocked();
|
||||
|
@ -431,7 +430,7 @@ bool
|
|||
CacheMemory::isLocked(Addr address, int context)
|
||||
{
|
||||
assert(address == makeLineAddress(address));
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int64_t cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
assert(loc != -1);
|
||||
DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
|
||||
|
@ -594,13 +593,13 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr)
|
|||
}
|
||||
|
||||
bool
|
||||
CacheMemory::isBlockInvalid(int64 cache_set, int64 loc)
|
||||
CacheMemory::isBlockInvalid(int64_t cache_set, int64_t loc)
|
||||
{
|
||||
return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid);
|
||||
}
|
||||
|
||||
bool
|
||||
CacheMemory::isBlockNotBusy(int64 cache_set, int64 loc)
|
||||
CacheMemory::isBlockNotBusy(int64_t cache_set, int64_t loc)
|
||||
{
|
||||
return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy);
|
||||
}
|
||||
|
|
|
@ -98,8 +98,8 @@ class CacheMemory : public SimObject
|
|||
Cycles getTagLatency() const { return tagArray.getLatency(); }
|
||||
Cycles getDataLatency() const { return dataArray.getLatency(); }
|
||||
|
||||
bool isBlockInvalid(int64 cache_set, int64 loc);
|
||||
bool isBlockNotBusy(int64 cache_set, int64 loc);
|
||||
bool isBlockInvalid(int64_t cache_set, int64_t loc);
|
||||
bool isBlockNotBusy(int64_t cache_set, int64_t loc);
|
||||
|
||||
// Hook for checkpointing the contents of the cache
|
||||
void recordCacheContents(int cntrl, CacheRecorder* tr) const;
|
||||
|
@ -149,12 +149,12 @@ class CacheMemory : public SimObject
|
|||
|
||||
private:
|
||||
// convert a Address to its location in the cache
|
||||
int64 addressToCacheSet(Addr address) const;
|
||||
int64_t addressToCacheSet(Addr address) const;
|
||||
|
||||
// Given a cache tag: returns the index of the tag in a set.
|
||||
// returns -1 if the tag is not found.
|
||||
int findTagInSet(int64 line, Addr tag) const;
|
||||
int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const;
|
||||
int findTagInSet(int64_t line, Addr tag) const;
|
||||
int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const;
|
||||
|
||||
// Private copy constructor and assignment operator
|
||||
CacheMemory(const CacheMemory& obj);
|
||||
|
|
|
@ -50,7 +50,7 @@ LRUReplacementPolicyParams::create()
|
|||
|
||||
|
||||
void
|
||||
LRUPolicy::touch(int64 set, int64 index, Tick time)
|
||||
LRUPolicy::touch(int64_t set, int64_t index, Tick time)
|
||||
{
|
||||
assert(index >= 0 && index < m_assoc);
|
||||
assert(set >= 0 && set < m_num_sets);
|
||||
|
@ -58,13 +58,11 @@ LRUPolicy::touch(int64 set, int64 index, Tick time)
|
|||
m_last_ref_ptr[set][index] = time;
|
||||
}
|
||||
|
||||
int64
|
||||
LRUPolicy::getVictim(int64 set) const
|
||||
int64_t
|
||||
LRUPolicy::getVictim(int64_t set) const
|
||||
{
|
||||
Tick time, smallest_time;
|
||||
int64 smallest_index;
|
||||
|
||||
smallest_index = 0;
|
||||
int64_t smallest_index = 0;
|
||||
smallest_time = m_last_ref_ptr[set][0];
|
||||
|
||||
for (unsigned i = 0; i < m_assoc; i++) {
|
||||
|
|
|
@ -41,8 +41,8 @@ class LRUPolicy : public AbstractReplacementPolicy
|
|||
LRUPolicy(const Params * p);
|
||||
~LRUPolicy();
|
||||
|
||||
void touch(int64 set, int64 way, Tick time);
|
||||
int64 getVictim(int64 set) const;
|
||||
void touch(int64_t set, int64_t way, Tick time);
|
||||
int64_t getVictim(int64_t set) const;
|
||||
};
|
||||
|
||||
#endif // __MEM_RUBY_STRUCTURES_LRUPOLICY_HH__
|
||||
|
|
|
@ -38,7 +38,7 @@ PseudoLRUPolicy::PseudoLRUPolicy(const Params * p)
|
|||
// associativity cannot exceed capacity of tree representation
|
||||
assert(m_num_sets > 0 &&
|
||||
m_assoc > 1 &&
|
||||
m_assoc <= (int64) sizeof(uint64)*4);
|
||||
m_assoc <= (int64_t) sizeof(uint64_t)*4);
|
||||
|
||||
m_trees = NULL;
|
||||
m_num_levels = 0;
|
||||
|
@ -55,7 +55,7 @@ PseudoLRUPolicy::PseudoLRUPolicy(const Params * p)
|
|||
m_num_levels++;
|
||||
}
|
||||
assert(m_num_levels < sizeof(unsigned int)*4);
|
||||
m_trees = new uint64[m_num_sets];
|
||||
m_trees = new uint64_t[m_num_sets];
|
||||
for (unsigned i = 0; i < m_num_sets; i++) {
|
||||
m_trees[i] = 0;
|
||||
}
|
||||
|
@ -75,7 +75,7 @@ PseudoLRUPolicy::~PseudoLRUPolicy()
|
|||
}
|
||||
|
||||
void
|
||||
PseudoLRUPolicy::touch(int64 set, int64 index, Tick time)
|
||||
PseudoLRUPolicy::touch(int64_t set, int64_t index, Tick time)
|
||||
{
|
||||
assert(index >= 0 && index < m_assoc);
|
||||
assert(set >= 0 && set < m_num_sets);
|
||||
|
@ -93,10 +93,10 @@ PseudoLRUPolicy::touch(int64 set, int64 index, Tick time)
|
|||
m_last_ref_ptr[set][index] = time;
|
||||
}
|
||||
|
||||
int64
|
||||
PseudoLRUPolicy::getVictim(int64 set) const
|
||||
int64_t
|
||||
PseudoLRUPolicy::getVictim(int64_t set) const
|
||||
{
|
||||
int64 index = 0;
|
||||
int64_t index = 0;
|
||||
|
||||
int tree_index = 0;
|
||||
int node_val;
|
||||
|
|
|
@ -53,13 +53,13 @@ class PseudoLRUPolicy : public AbstractReplacementPolicy
|
|||
PseudoLRUPolicy(const Params * p);
|
||||
~PseudoLRUPolicy();
|
||||
|
||||
void touch(int64 set, int64 way, Tick time);
|
||||
int64 getVictim(int64 set) const;
|
||||
void touch(int64_t set, int64_t way, Tick time);
|
||||
int64_t getVictim(int64_t set) const;
|
||||
|
||||
private:
|
||||
unsigned int m_effective_assoc; /** nearest (to ceiling) power of 2 */
|
||||
unsigned int m_num_levels; /** number of levels in the tree */
|
||||
uint64* m_trees; /** bit representation of the
|
||||
uint64_t* m_trees; /** bit representation of the
|
||||
* trees, one for each set */
|
||||
};
|
||||
|
||||
|
|
|
@ -176,7 +176,7 @@ void
|
|||
RubyMemoryControl::init()
|
||||
{
|
||||
m_msg_counter = 0;
|
||||
assert(m_tFaw <= 62); // must fit in a uint64 shift register
|
||||
assert(m_tFaw <= 62); // must fit in a uint64_t shift register
|
||||
|
||||
m_total_banks = m_banks_per_rank * m_ranks_per_dimm * m_dimms_per_channel;
|
||||
m_total_ranks = m_ranks_per_dimm * m_dimms_per_channel;
|
||||
|
@ -213,7 +213,7 @@ RubyMemoryControl::init()
|
|||
// m_tfaw_count keeps track of how many 1 bits are set
|
||||
// in each shift register. When m_tfaw_count is >= 4,
|
||||
// new activates are not allowed.
|
||||
m_tfaw_shift = new uint64[m_total_ranks];
|
||||
m_tfaw_shift = new uint64_t[m_total_ranks];
|
||||
m_tfaw_count = new int[m_total_ranks];
|
||||
for (int i = 0; i < m_total_ranks; i++) {
|
||||
m_tfaw_shift[i] = 0;
|
||||
|
@ -236,7 +236,7 @@ RubyMemoryControl::reset()
|
|||
{
|
||||
m_msg_counter = 0;
|
||||
|
||||
assert(m_tFaw <= 62); // must fit in a uint64 shift register
|
||||
assert(m_tFaw <= 62); // must fit in a uint64_t shift register
|
||||
|
||||
m_total_banks = m_banks_per_rank * m_ranks_per_dimm * m_dimms_per_channel;
|
||||
m_total_ranks = m_ranks_per_dimm * m_dimms_per_channel;
|
||||
|
|
|
@ -162,11 +162,11 @@ class RubyMemoryControl : public AbstractMemory, public Consumer
|
|||
|
||||
// Each entry indicates number of address-bus cycles until bank
|
||||
// is reschedulable:
|
||||
int* m_bankBusyCounter;
|
||||
int* m_oldRequest;
|
||||
int *m_bankBusyCounter;
|
||||
int *m_oldRequest;
|
||||
|
||||
uint64* m_tfaw_shift;
|
||||
int* m_tfaw_count;
|
||||
uint64_t *m_tfaw_shift;
|
||||
int *m_tfaw_count;
|
||||
|
||||
// Each of these indicates number of address-bus cycles until
|
||||
// we can issue a new request of the corresponding type:
|
||||
|
@ -182,12 +182,12 @@ class RubyMemoryControl : public AbstractMemory, public Consumer
|
|||
int m_ageCounter; // age of old requests; to detect starvation
|
||||
int m_idleCount; // watchdog timer for shutting down
|
||||
|
||||
MemCntrlProfiler* m_profiler_ptr;
|
||||
MemCntrlProfiler *m_profiler_ptr;
|
||||
|
||||
class MemCntrlEvent : public Event
|
||||
{
|
||||
public:
|
||||
MemCntrlEvent(RubyMemoryControl* _mem_cntrl)
|
||||
MemCntrlEvent(RubyMemoryControl *_mem_cntrl)
|
||||
{
|
||||
mem_cntrl = _mem_cntrl;
|
||||
}
|
||||
|
|
|
@ -161,13 +161,13 @@ CacheRecorder::addRecord(int cntrl, Addr data_addr, Addr pc_addr,
|
|||
m_records.push_back(rec);
|
||||
}
|
||||
|
||||
uint64
|
||||
CacheRecorder::aggregateRecords(uint8_t** buf, uint64 total_size)
|
||||
uint64_t
|
||||
CacheRecorder::aggregateRecords(uint8_t **buf, uint64_t total_size)
|
||||
{
|
||||
std::sort(m_records.begin(), m_records.end(), compareTraceRecords);
|
||||
|
||||
int size = m_records.size();
|
||||
uint64 current_size = 0;
|
||||
uint64_t current_size = 0;
|
||||
int record_size = sizeof(TraceRecord) + m_block_size_bytes;
|
||||
|
||||
for (int i = 0; i < size; ++i) {
|
||||
|
|
|
@ -77,7 +77,7 @@ class CacheRecorder
|
|||
void addRecord(int cntrl, Addr data_addr, Addr pc_addr,
|
||||
RubyRequestType type, Tick time, DataBlock& data);
|
||||
|
||||
uint64 aggregateRecords(uint8_t** data, uint64 size);
|
||||
uint64_t aggregateRecords(uint8_t **data, uint64_t size);
|
||||
|
||||
/*!
|
||||
* Function for flushing the memory contents of the caches to the
|
||||
|
|
|
@ -102,8 +102,8 @@ RubySystem::~RubySystem()
|
|||
|
||||
void
|
||||
RubySystem::makeCacheRecorder(uint8_t *uncompressed_trace,
|
||||
uint64 cache_trace_size,
|
||||
uint64 block_size_bytes)
|
||||
uint64_t cache_trace_size,
|
||||
uint64_t block_size_bytes)
|
||||
{
|
||||
vector<Sequencer*> sequencer_map;
|
||||
Sequencer* sequencer_ptr = NULL;
|
||||
|
@ -207,7 +207,7 @@ RubySystem::memWriteback()
|
|||
|
||||
void
|
||||
RubySystem::writeCompressedTrace(uint8_t *raw_data, string filename,
|
||||
uint64 uncompressed_trace_size)
|
||||
uint64_t uncompressed_trace_size)
|
||||
{
|
||||
// Create the checkpoint file for the memory
|
||||
string thefile = CheckpointIn::dir() + "/" + filename.c_str();
|
||||
|
@ -240,7 +240,7 @@ RubySystem::serialize(CheckpointOut &cp) const
|
|||
// Store the cache-block size, so we are able to restore on systems with a
|
||||
// different cache-block size. CacheRecorder depends on the correct
|
||||
// cache-block size upon unserializing.
|
||||
uint64 block_size_bytes = getBlockSizeBytes();
|
||||
uint64_t block_size_bytes = getBlockSizeBytes();
|
||||
SERIALIZE_SCALAR(block_size_bytes);
|
||||
|
||||
// Check that there's a valid trace to use. If not, then memory won't be
|
||||
|
@ -252,7 +252,7 @@ RubySystem::serialize(CheckpointOut &cp) const
|
|||
|
||||
// Aggregate the trace entries together into a single array
|
||||
uint8_t *raw_data = new uint8_t[4096];
|
||||
uint64 cache_trace_size = m_cache_recorder->aggregateRecords(&raw_data,
|
||||
uint64_t cache_trace_size = m_cache_recorder->aggregateRecords(&raw_data,
|
||||
4096);
|
||||
string cache_trace_file = name() + ".cache.gz";
|
||||
writeCompressedTrace(raw_data, cache_trace_file, cache_trace_size);
|
||||
|
@ -274,7 +274,7 @@ RubySystem::drainResume()
|
|||
|
||||
void
|
||||
RubySystem::readCompressedTrace(string filename, uint8_t *&raw_data,
|
||||
uint64& uncompressed_trace_size)
|
||||
uint64_t &uncompressed_trace_size)
|
||||
{
|
||||
// Read the trace file
|
||||
gzFile compressedTrace;
|
||||
|
@ -311,11 +311,11 @@ RubySystem::unserialize(CheckpointIn &cp)
|
|||
// This value should be set to the checkpoint-system's block-size.
|
||||
// Optional, as checkpoints without it can be run if the
|
||||
// checkpoint-system's block-size == current block-size.
|
||||
uint64 block_size_bytes = getBlockSizeBytes();
|
||||
uint64_t block_size_bytes = getBlockSizeBytes();
|
||||
UNSERIALIZE_OPT_SCALAR(block_size_bytes);
|
||||
|
||||
string cache_trace_file;
|
||||
uint64 cache_trace_size = 0;
|
||||
uint64_t cache_trace_size = 0;
|
||||
|
||||
UNSERIALIZE_SCALAR(cache_trace_file);
|
||||
UNSERIALIZE_SCALAR(cache_trace_size);
|
||||
|
|
|
@ -119,14 +119,14 @@ class RubySystem : public ClockedObject
|
|||
RubySystem& operator=(const RubySystem& obj);
|
||||
|
||||
void makeCacheRecorder(uint8_t *uncompressed_trace,
|
||||
uint64 cache_trace_size,
|
||||
uint64 block_size_bytes);
|
||||
uint64_t cache_trace_size,
|
||||
uint64_t block_size_bytes);
|
||||
|
||||
static void readCompressedTrace(std::string filename,
|
||||
uint8_t *&raw_data,
|
||||
uint64& uncompressed_trace_size);
|
||||
uint64_t &uncompressed_trace_size);
|
||||
static void writeCompressedTrace(uint8_t *raw_data, std::string file,
|
||||
uint64 uncompressed_trace_size);
|
||||
uint64_t uncompressed_trace_size);
|
||||
|
||||
private:
|
||||
// configuration parameters
|
||||
|
|
|
@ -320,9 +320,9 @@ class $c_ident : public AbstractController
|
|||
|
||||
void countTransition(${ident}_State state, ${ident}_Event event);
|
||||
void possibleTransition(${ident}_State state, ${ident}_Event event);
|
||||
uint64 getEventCount(${ident}_Event event);
|
||||
uint64_t getEventCount(${ident}_Event event);
|
||||
bool isPossible(${ident}_State state, ${ident}_Event event);
|
||||
uint64 getTransitionCount(${ident}_State state, ${ident}_Event event);
|
||||
uint64_t getTransitionCount(${ident}_State state, ${ident}_Event event);
|
||||
|
||||
private:
|
||||
''')
|
||||
|
@ -802,7 +802,7 @@ $c_ident::possibleTransition(${ident}_State state,
|
|||
m_possible[state][event] = true;
|
||||
}
|
||||
|
||||
uint64
|
||||
uint64_t
|
||||
$c_ident::getEventCount(${ident}_Event event)
|
||||
{
|
||||
return m_event_counters[event];
|
||||
|
@ -814,7 +814,7 @@ $c_ident::isPossible(${ident}_State state, ${ident}_Event event)
|
|||
return m_possible[state][event];
|
||||
}
|
||||
|
||||
uint64
|
||||
uint64_t
|
||||
$c_ident::getTransitionCount(${ident}_State state,
|
||||
${ident}_Event event)
|
||||
{
|
||||
|
|
Loading…
Reference in a new issue