Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : cb15101d24ef2969e1819d6bdeeb2dd1f23f02d1
This commit is contained in:
Gabe Black
commit
466c387318
15 changed files with 462 additions and 276 deletions
6
configs/boot/mutex-test.rcS
Normal file
6
configs/boot/mutex-test.rcS
Normal file
|
|
@ -0,0 +1,6 @@
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#!/bin/sh
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cd /benchmarks/tests
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/sbin/m5 resetstats
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./pthread_mutex_test 4 10000
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/sbin/m5 exit
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@ -97,6 +97,8 @@ Benchmarks = {
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'ValStreamScale': [SysConfig('micro_streamscale.rcS', '512MB')],
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'ValStreamCopy': [SysConfig('micro_streamcopy.rcS', '512MB')],
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'MutexTest': [SysConfig('mutex-test.rcS', '128MB')],
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'bnAn': [SysConfig('/z/saidi/work/m5.newmem.head/configs/boot/bn-app.rcS',
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'128MB', '/z/saidi/work/bottleneck/bnimg.img')]
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}
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@ -1,4 +1,4 @@
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# Copyright (c) 2005 The Regents of The University of Michigan
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# Copyright (c) 2005-2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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@ -26,54 +26,243 @@
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#
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# Authors: Ron Dreslinski
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from m5 import *
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import Splash2
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# Splash2 Run Script
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#
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if 'SYSTEM' not in env:
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panic("The SYSTEM environment variable must be set!\ne.g -ESYSTEM=Detailed\n")
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import m5
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from m5.objects import *
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import os, optparse, sys
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m5.AddToPath('../common')
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if env['SYSTEM'] == 'Simple':
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from SimpleConfig import *
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BaseCPU.workload = Parent.workload
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SimpleStandAlone.cpu = [ CPU() for i in xrange(int(env['NP'])) ]
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root = SimpleStandAlone()
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elif env['SYSTEM'] == 'Detailed':
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from DetailedConfig import *
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BaseCPU.workload = Parent.workload
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DetailedStandAlone.cpu = [ DetailedCPU() for i in xrange(int(env['NP'])) ]
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root = DetailedStandAlone()
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# --------------------
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# Define Command Line Options
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# ====================
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parser = optparse.OptionParser()
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parser.add_option("-d", "--detailed", action="store_true")
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parser.add_option("-t", "--timing", action="store_true")
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parser.add_option("-m", "--maxtick", type="int")
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parser.add_option("-n", "--numcpus",
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help="Number of cpus in total", type="int")
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parser.add_option("-f", "--frequency",
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default = "1GHz",
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help="Frequency of each CPU")
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parser.add_option("-p", "--protocol",
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default="moesi",
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help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)")
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parser.add_option("--l1size",
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default = "32kB")
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parser.add_option("--l1latency",
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default = 1)
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parser.add_option("--l2size",
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default = "256kB")
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parser.add_option("--l2latency",
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default = 10)
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parser.add_option("--rootdir",
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help="ROot directory of Splash2",
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default="/dist/splash2/codes")
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parser.add_option("-b", "--benchmark",
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help="Splash 2 benchmark to run")
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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if not options.numcpus:
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print "Specify the number of cpus with -n"
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sys.exit(1)
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# --------------------
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# Define Splash2 Benchmarks
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# ====================
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class Cholesky(LiveProcess):
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executable = options.rootdir + '/kernels/cholesky/CHOLESKY'
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cmd = 'CHOLESKY -p' + str(options.numcpus) + ' '\
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+ options.rootdir + '/kernels/cholesky/inputs/tk23.O'
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class FFT(LiveProcess):
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executable = options.rootdir + '/kernels/fft/FFT'
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cmd = 'FFT -p' + str(options.numcpus) + ' -m18'
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class LU_contig(LiveProcess):
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executable = options.rootdir + '/kernels/lu/contiguous_blocks/LU'
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cmd = 'LU -p' + str(options.numcpus)
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class LU_noncontig(LiveProcess):
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executable = options.rootdir + '/kernels/lu/non_contiguous_blocks/LU'
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cmd = 'LU -p' + str(options.numcpus)
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class Radix(LiveProcess):
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executable = options.rootdir + '/kernels/radix/RADIX'
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cmd = 'RADIX -n524288 -p' + str(options.numcpus)
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class Barnes(LiveProcess):
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executable = options.rootdir + '/apps/barnes/BARNES'
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cmd = 'BARNES'
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input = options.rootdir + '/apps/barnes/input.p' + str(options.numcpus)
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class FMM(LiveProcess):
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executable = options.rootdir + '/apps/fmm/FMM'
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cmd = 'FMM'
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input = options.rootdir + '/apps/fmm/inputs/input.2048.p' + str(options.numcpus)
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class Ocean_contig(LiveProcess):
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executable = options.rootdir + '/apps/ocean/contiguous_partitions/OCEAN'
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cmd = 'OCEAN -p' + str(options.numcpus)
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class Ocean_noncontig(LiveProcess):
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executable = options.rootdir + '/apps/ocean/non_contiguous_partitions/OCEAN'
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cmd = 'OCEAN -p' + str(options.numcpus)
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class Raytrace(LiveProcess):
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executable = options.rootdir + '/apps/raytrace/RAYTRACE'
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cmd = 'RAYTRACE -p' + str(options.numcpus) + ' ' \
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+ options.rootdir + 'apps/raytrace/inputs/teapot.env'
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class Water_nsquared(LiveProcess):
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executable = options.rootdir + '/apps/water-nsquared/WATER-NSQUARED'
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cmd = 'WATER-NSQUARED'
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input = options.rootdir + '/apps/water-nsquared/input.p' + str(options.numcpus)
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class Water_spatial(LiveProcess):
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executable = options.rootdir + '/apps/water-spatial/WATER-SPATIAL'
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cmd = 'WATER-SPATIAL'
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input = options.rootdir + '/apps/water-spatial/input.p' + str(options.numcpus)
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# --------------------
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# Base L1 Cache Definition
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# ====================
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class L1(BaseCache):
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latency = options.l1latency
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block_size = 64
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mshrs = 12
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tgts_per_mshr = 8
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protocol = CoherenceProtocol(protocol=options.protocol)
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# ----------------------
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# Base L2 Cache Definition
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# ----------------------
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class L2(BaseCache):
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block_size = 64
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latency = options.l2latency
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mshrs = 92
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tgts_per_mshr = 16
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write_buffers = 8
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# ----------------------
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# Define the cpus
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# ----------------------
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busFrequency = Frequency(options.frequency)
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if options.timing:
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cpus = [TimingSimpleCPU(cpu_id = i,
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clock=options.frequency)
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for i in xrange(options.numcpus)]
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elif options.detailed:
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cpus = [DerivO3CPU(cpu_id = i,
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clock=options.frequency)
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for i in xrange(options.numcpus)]
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else:
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panic("The SYSTEM environment variable was set to something improper.\n Use Simple or Detailed\n")
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cpus = [AtomicSimpleCPU(cpu_id = i,
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clock=options.frequency)
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for i in xrange(options.numcpus)]
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if 'BENCHMARK' not in env:
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panic("The BENCHMARK environment variable must be set!\ne.g. -EBENCHMARK=Cholesky\n")
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# ----------------------
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# Create a system, and add system wide objects
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# ----------------------
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system = System(cpu = cpus, physmem = PhysicalMemory(),
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membus = Bus(clock = busFrequency))
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if env['BENCHMARK'] == 'Cholesky':
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root.workload = Splash2.Cholesky()
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elif env['BENCHMARK'] == 'FFT':
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root.workload = Splash2.FFT()
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elif env['BENCHMARK'] == 'LUContig':
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root.workload = Splash2.LU_contig()
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elif env['BENCHMARK'] == 'LUNoncontig':
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root.workload = Splash2.LU_noncontig()
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elif env['BENCHMARK'] == 'Radix':
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root.workload = Splash2.Radix()
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elif env['BENCHMARK'] == 'Barnes':
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root.workload = Splash2.Barnes()
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elif env['BENCHMARK'] == 'FMM':
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root.workload = Splash2.FMM()
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elif env['BENCHMARK'] == 'OceanContig':
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root.workload = Splash2.Ocean_contig()
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elif env['BENCHMARK'] == 'OceanNoncontig':
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root.workload = Splash2.Ocean_noncontig()
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elif env['BENCHMARK'] == 'Raytrace':
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root.workload = Splash2.Raytrace()
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elif env['BENCHMARK'] == 'WaterNSquared':
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root.workload = Splash2.Water_nsquared()
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elif env['BENCHMARK'] == 'WaterSpatial':
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root.workload = Splash2.Water_spatial()
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system.toL2bus = Bus(clock = busFrequency)
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system.l2 = L2(size = options.l2size, assoc = 8)
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# ----------------------
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# Connect the L2 cache and memory together
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# ----------------------
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system.physmem.port = system.membus.port
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system.l2.cpu_side = system.toL2bus.port
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system.l2.mem_side = system.membus.port
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# ----------------------
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# Connect the L2 cache and clusters together
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# ----------------------
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for cpu in cpus:
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cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
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L1(size = options.l1size, assoc = 4))
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cpu.mem = cpu.dcache
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# connect cpu level-1 caches to shared level-2 cache
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cpu.connectMemPorts(system.toL2bus)
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# ----------------------
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# Define the root
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# ----------------------
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root = Root(system = system)
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# --------------------
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# Pick the correct Splash2 Benchmarks
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# ====================
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if options.benchmark == 'Cholesky':
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root.workload = Cholesky()
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elif options.benchmark == 'FFT':
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root.workload = FFT()
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elif options.benchmark == 'LUContig':
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root.workload = LU_contig()
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elif options.benchmark == 'LUNoncontig':
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root.workload = LU_noncontig()
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elif options.benchmark == 'Radix':
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root.workload = Radix()
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elif options.benchmark == 'Barnes':
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root.workload = Barnes()
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elif options.benchmark == 'FMM':
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root.workload = FMM()
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elif options.benchmark == 'OceanContig':
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root.workload = Ocean_contig()
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elif options.benchmark == 'OceanNoncontig':
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root.workload = Ocean_noncontig()
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elif options.benchmark == 'Raytrace':
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root.workload = Raytrace()
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elif options.benchmark == 'WaterNSquared':
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root.workload = Water_nsquared()
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elif options.benchmark == 'WaterSpatial':
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root.workload = Water_spatial()
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else:
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panic("The BENCHMARK environment variable was set to something" \
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panic("The --benchmark environment variable was set to something" \
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+" improper.\nUse Cholesky, FFT, LUContig, LUNoncontig, Radix" \
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+", Barnes, FMM, OceanContig,\nOceanNoncontig, Raytrace," \
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+" WaterNSquared, or WaterSpatial\n")
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# --------------------
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# Assign the workload to the cpus
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# ====================
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|
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for cpu in cpus:
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cpu.workload = root.workload
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|
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# ----------------------
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# Run the simulation
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# ----------------------
|
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|
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if options.timing or options.detailed:
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root.system.mem_mode = 'timing'
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|
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# instantiate configuration
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m5.instantiate(root)
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|
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# simulate until program terminates
|
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if options.maxtick:
|
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exit_event = m5.simulate(options.maxtick)
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else:
|
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exit_event = m5.simulate()
|
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|
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print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
|
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|
||||
|
|
|
|||
|
|
@ -194,7 +194,8 @@ void PageTableFault::invoke(ThreadContext *tc)
|
|||
|
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// We've accessed the next page
|
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if (vaddr > p->stack_min - PageBytes) {
|
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warn("Increasing stack %#x:%#x to %#x:%#x because of access to %#x",
|
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DPRINTF(Stack,
|
||||
"Increasing stack %#x:%#x to %#x:%#x because of access to %#x",
|
||||
p->stack_min, p->stack_base, p->stack_min - PageBytes,
|
||||
p->stack_base, vaddr);
|
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p->stack_min -= PageBytes;
|
||||
|
|
@ -202,6 +203,7 @@ void PageTableFault::invoke(ThreadContext *tc)
|
|||
fatal("Over max stack size for one thread\n");
|
||||
p->pTable->allocate(p->stack_min, PageBytes);
|
||||
} else {
|
||||
warn("Page fault on address %#x\n", vaddr);
|
||||
FaultBase::invoke(tc);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -133,6 +133,7 @@ baseFlags = [
|
|||
'PciConfigAll',
|
||||
'Pipeline',
|
||||
'Printf',
|
||||
'Quiesce',
|
||||
'ROB',
|
||||
'Regs',
|
||||
'Rename',
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
* Authors: Kevin Lim
|
||||
*/
|
||||
|
||||
#include "cpu/base.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "cpu/quiesce_event.hh"
|
||||
|
||||
|
|
@ -39,6 +40,7 @@ EndQuiesceEvent::EndQuiesceEvent(ThreadContext *_tc)
|
|||
void
|
||||
EndQuiesceEvent::process()
|
||||
{
|
||||
DPRINTF(Quiesce, "activating %s\n", tc->getCpuPtr()->name());
|
||||
tc->activate();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ IsaFake::read(PacketPtr pkt)
|
|||
DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
|
||||
|
||||
switch (pkt->getSize()) {
|
||||
case sizeof(uint64_t):
|
||||
pkt->set(0xFFFFFFFFFFFFFFFFULL);
|
||||
break;
|
||||
case sizeof(uint32_t):
|
||||
|
|
|
|||
|
|
@ -544,12 +544,19 @@ class Tru64 : public OperatingSystem
|
|||
process->next_thread_stack_base -= stack_size;
|
||||
}
|
||||
|
||||
stack_base = roundDown(stack_base, VMPageSize);
|
||||
Addr rounded_stack_base = roundDown(stack_base, VMPageSize);
|
||||
Addr rounded_stack_size = roundUp(stack_size, VMPageSize);
|
||||
|
||||
DPRINTF(SyscallVerbose,
|
||||
"stack_create: allocating stack @ %#x size %#x "
|
||||
"(rounded from %#x, %#x)\n",
|
||||
rounded_stack_base, rounded_stack_size,
|
||||
stack_base, stack_size);
|
||||
|
||||
// map memory
|
||||
process->pTable->allocate(stack_base, roundUp(stack_size, VMPageSize));
|
||||
process->pTable->allocate(rounded_stack_base, rounded_stack_size);
|
||||
|
||||
argp->address = gtoh(stack_base);
|
||||
argp->address = gtoh(rounded_stack_base);
|
||||
argp.copyOut(tc->getMemPort());
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
16
src/mem/cache/cache_impl.hh
vendored
16
src/mem/cache/cache_impl.hh
vendored
|
|
@ -231,8 +231,16 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
|
|||
exitSimLoop("A cache reached the maximum miss count");
|
||||
}
|
||||
}
|
||||
|
||||
if (pkt->flags & SATISFIED) {
|
||||
// happens when a store conditional fails because it missed
|
||||
// the cache completely
|
||||
if (pkt->needsResponse())
|
||||
respond(pkt, curTick+lat);
|
||||
} else {
|
||||
missQueue->handleMiss(pkt, size, curTick + hitLatency);
|
||||
// return MA_CACHE_MISS;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -585,7 +593,7 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
|
|||
assert(pkt->result == Packet::Success);
|
||||
}
|
||||
return 0;
|
||||
} else if (!blk) {
|
||||
} else if (!blk && !(pkt->flags & SATISFIED)) {
|
||||
// update the cache state and statistics
|
||||
if (mshr || !writes.empty()){
|
||||
// Can't handle it, return pktuest unsatisfied.
|
||||
|
|
@ -653,6 +661,7 @@ return 0;
|
|||
return memSidePort->sendAtomic(pkt);
|
||||
}
|
||||
} else {
|
||||
if (blk) {
|
||||
// There was a cache hit.
|
||||
// Handle writebacks if needed
|
||||
while (!writebacks.empty()){
|
||||
|
|
@ -661,10 +670,11 @@ return 0;
|
|||
}
|
||||
|
||||
hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
|
||||
}
|
||||
|
||||
return hitLatency;
|
||||
}
|
||||
fatal("Probe not handled.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
271
src/mem/cache/coherence/coherence_protocol.cc
vendored
271
src/mem/cache/coherence/coherence_protocol.cc
vendored
|
|
@ -206,8 +206,7 @@ bool
|
|||
CoherenceProtocol::supplyTrans(BaseCache *cache, PacketPtr &pkt,
|
||||
CacheBlk *blk,
|
||||
MSHR *mshr,
|
||||
CacheBlk::State & new_state
|
||||
)
|
||||
CacheBlk::State & new_state)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
|
@ -263,182 +262,106 @@ CoherenceProtocol::CoherenceProtocol(const string &name,
|
|||
const bool doUpgrades)
|
||||
: SimObject(name)
|
||||
{
|
||||
if ((protocol == "mosi" || protocol == "moesi") && !doUpgrades) {
|
||||
cerr << "CoherenceProtocol: ownership protocols require upgrade transactions"
|
||||
<< "(write miss on owned block generates ReadExcl, which will clobber dirty block)"
|
||||
<< endl;
|
||||
fatal("");
|
||||
// Python should catch this, but in case it doesn't...
|
||||
if (!(protocol == "msi" || protocol == "mesi" ||
|
||||
protocol == "mosi" || protocol == "moesi")) {
|
||||
fatal("CoherenceProtocol: unrecognized protocol %s\n", protocol);
|
||||
}
|
||||
|
||||
Packet::Command writeToSharedCmd = doUpgrades ? Packet::UpgradeReq : Packet::ReadExReq;
|
||||
Packet::Command writeToSharedResp = doUpgrades ? Packet::UpgradeReq : Packet::ReadExResp;
|
||||
bool hasOwned = (protocol == "mosi" || protocol == "moesi");
|
||||
bool hasExclusive = (protocol == "mesi" || protocol == "moesi");
|
||||
|
||||
if (hasOwned && !doUpgrades) {
|
||||
fatal("CoherenceProtocol: ownership protocols require upgrade "
|
||||
"transactions\n(write miss on owned block generates ReadExcl, "
|
||||
"which will clobber dirty block)\n");
|
||||
}
|
||||
|
||||
// set up a few shortcuts to save typing & visual clutter
|
||||
typedef Packet P;
|
||||
StateTransition (&tt)[stateMax+1][NUM_MEM_CMDS] = transitionTable;
|
||||
|
||||
P::Command writeToSharedCmd = doUpgrades ? P::UpgradeReq : P::ReadExReq;
|
||||
P::Command writeToSharedResp = doUpgrades ? P::UpgradeReq : P::ReadExResp;
|
||||
|
||||
// Note that all transitions by default cause a panic.
|
||||
// Override the valid transitions with the appropriate actions here.
|
||||
|
||||
//
|
||||
// ----- incoming requests: specify outgoing bus request -----
|
||||
//
|
||||
tt[Invalid][P::ReadReq].onRequest(P::ReadReq);
|
||||
// we only support write allocate right now
|
||||
tt[Invalid][P::WriteReq].onRequest(P::ReadExReq);
|
||||
tt[Shared][P::WriteReq].onRequest(writeToSharedCmd);
|
||||
if (hasOwned) {
|
||||
tt[Owned][P::WriteReq].onRequest(writeToSharedCmd);
|
||||
}
|
||||
|
||||
// Prefetching causes a read
|
||||
tt[Invalid][P::SoftPFReq].onRequest(P::ReadReq);
|
||||
tt[Invalid][P::HardPFReq].onRequest(P::ReadReq);
|
||||
|
||||
//
|
||||
// ----- on response to given request: specify new state -----
|
||||
//
|
||||
tt[Invalid][P::ReadExResp].onResponse(Modified);
|
||||
tt[Shared][writeToSharedResp].onResponse(Modified);
|
||||
// Go to Exclusive state on read response if we have one (will
|
||||
// move into shared if the shared line is asserted in the
|
||||
// getNewState function)
|
||||
//
|
||||
// originally had this as:
|
||||
// tt[Invalid][P::ReadResp].onResponse(hasExclusive ? Exclusive: Shared);
|
||||
// ...but for some reason that caused a link error...
|
||||
if (hasExclusive) {
|
||||
tt[Invalid][P::ReadResp].onResponse(Exclusive);
|
||||
} else {
|
||||
tt[Invalid][P::ReadResp].onResponse(Shared);
|
||||
}
|
||||
if (hasOwned) {
|
||||
tt[Owned][writeToSharedResp].onResponse(Modified);
|
||||
}
|
||||
|
||||
//
|
||||
// ----- bus snoop transition functions -----
|
||||
//
|
||||
tt[Invalid][P::ReadReq].onSnoop(nullTransition);
|
||||
tt[Invalid][P::ReadExReq].onSnoop(nullTransition);
|
||||
tt[Invalid][P::InvalidateReq].onSnoop(invalidateTrans);
|
||||
tt[Invalid][P::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
tt[Shared][P::ReadReq].onSnoop(hasExclusive
|
||||
? assertShared : nullTransition);
|
||||
tt[Shared][P::ReadExReq].onSnoop(invalidateTrans);
|
||||
tt[Shared][P::InvalidateReq].onSnoop(invalidateTrans);
|
||||
tt[Shared][P::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
if (doUpgrades) {
|
||||
tt[Invalid][P::UpgradeReq].onSnoop(nullTransition);
|
||||
tt[Shared][P::UpgradeReq].onSnoop(invalidateTrans);
|
||||
}
|
||||
tt[Modified][P::ReadExReq].onSnoop(supplyAndInvalidateTrans);
|
||||
tt[Modified][P::ReadReq].onSnoop(hasOwned
|
||||
? supplyAndGotoOwnedTrans
|
||||
: supplyAndGotoSharedTrans);
|
||||
tt[Modified][P::InvalidateReq].onSnoop(invalidateTrans);
|
||||
tt[Modified][P::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
|
||||
if (hasExclusive) {
|
||||
tt[Exclusive][P::ReadReq].onSnoop(assertShared);
|
||||
tt[Exclusive][P::ReadExReq].onSnoop(invalidateTrans);
|
||||
tt[Exclusive][P::InvalidateReq].onSnoop(invalidateTrans);
|
||||
tt[Exclusive][P::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
}
|
||||
|
||||
if (hasOwned) {
|
||||
tt[Owned][P::ReadReq].onSnoop(supplyAndGotoOwnedTrans);
|
||||
tt[Owned][P::ReadExReq].onSnoop(supplyAndInvalidateTrans);
|
||||
tt[Owned][P::UpgradeReq].onSnoop(invalidateTrans);
|
||||
tt[Owned][P::InvalidateReq].onSnoop(invalidateTrans);
|
||||
tt[Owned][P::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
}
|
||||
|
||||
// @todo add in hardware prefetch to this list
|
||||
if (protocol == "msi") {
|
||||
// incoming requests: specify outgoing bus request
|
||||
transitionTable[Invalid][Packet::ReadReq].onRequest(Packet::ReadReq);
|
||||
transitionTable[Invalid][Packet::WriteReq].onRequest(Packet::ReadExReq);
|
||||
transitionTable[Shared][Packet::WriteReq].onRequest(writeToSharedCmd);
|
||||
//Prefetching causes a read
|
||||
transitionTable[Invalid][Packet::SoftPFReq].onRequest(Packet::ReadReq);
|
||||
transitionTable[Invalid][Packet::HardPFReq].onRequest(Packet::ReadReq);
|
||||
|
||||
// on response to given request: specify new state
|
||||
transitionTable[Invalid][Packet::ReadResp].onResponse(Shared);
|
||||
transitionTable[Invalid][Packet::ReadExResp].onResponse(Modified);
|
||||
transitionTable[Shared][writeToSharedResp].onResponse(Modified);
|
||||
|
||||
// bus snoop transition functions
|
||||
transitionTable[Invalid][Packet::ReadReq].onSnoop(nullTransition);
|
||||
transitionTable[Invalid][Packet::ReadExReq].onSnoop(nullTransition);
|
||||
transitionTable[Shared][Packet::ReadReq].onSnoop(nullTransition);
|
||||
transitionTable[Shared][Packet::ReadExReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Modified][Packet::ReadExReq].onSnoop(supplyAndInvalidateTrans);
|
||||
transitionTable[Modified][Packet::ReadReq].onSnoop(supplyAndGotoSharedTrans);
|
||||
//Tansitions on seeing a DMA (writeInv(samelevel) or DMAInv)
|
||||
transitionTable[Invalid][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Shared][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Modified][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Invalid][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Shared][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Modified][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
|
||||
if (doUpgrades) {
|
||||
transitionTable[Invalid][Packet::UpgradeReq].onSnoop(nullTransition);
|
||||
transitionTable[Shared][Packet::UpgradeReq].onSnoop(invalidateTrans);
|
||||
}
|
||||
}
|
||||
|
||||
else if(protocol == "mesi") {
|
||||
// incoming requests: specify outgoing bus request
|
||||
transitionTable[Invalid][Packet::ReadReq].onRequest(Packet::ReadReq);
|
||||
transitionTable[Invalid][Packet::WriteReq].onRequest(Packet::ReadExReq);
|
||||
transitionTable[Shared][Packet::WriteReq].onRequest(writeToSharedCmd);
|
||||
//Prefetching causes a read
|
||||
transitionTable[Invalid][Packet::SoftPFReq].onRequest(Packet::ReadReq);
|
||||
transitionTable[Invalid][Packet::HardPFReq].onRequest(Packet::ReadReq);
|
||||
|
||||
// on response to given request: specify new state
|
||||
transitionTable[Invalid][Packet::ReadResp].onResponse(Exclusive);
|
||||
//It will move into shared if the shared line is asserted in the
|
||||
//getNewState function
|
||||
transitionTable[Invalid][Packet::ReadExResp].onResponse(Modified);
|
||||
transitionTable[Shared][writeToSharedResp].onResponse(Modified);
|
||||
|
||||
// bus snoop transition functions
|
||||
transitionTable[Invalid][Packet::ReadReq].onSnoop(nullTransition);
|
||||
transitionTable[Invalid][Packet::ReadExReq].onSnoop(nullTransition);
|
||||
transitionTable[Shared][Packet::ReadReq].onSnoop(assertShared);
|
||||
transitionTable[Shared][Packet::ReadExReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Exclusive][Packet::ReadReq].onSnoop(assertShared);
|
||||
transitionTable[Exclusive][Packet::ReadExReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Modified][Packet::ReadExReq].onSnoop(supplyAndInvalidateTrans);
|
||||
transitionTable[Modified][Packet::ReadReq].onSnoop(supplyAndGotoSharedTrans);
|
||||
//Tansitions on seeing a DMA (writeInv(samelevel) or DMAInv)
|
||||
transitionTable[Invalid][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Shared][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Modified][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Exclusive][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Invalid][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Shared][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Modified][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Exclusive][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
|
||||
if (doUpgrades) {
|
||||
transitionTable[Invalid][Packet::UpgradeReq].onSnoop(nullTransition);
|
||||
transitionTable[Shared][Packet::UpgradeReq].onSnoop(invalidateTrans);
|
||||
}
|
||||
}
|
||||
|
||||
else if(protocol == "mosi") {
|
||||
// incoming requests: specify outgoing bus request
|
||||
transitionTable[Invalid][Packet::ReadReq].onRequest(Packet::ReadReq);
|
||||
transitionTable[Invalid][Packet::WriteReq].onRequest(Packet::ReadExReq);
|
||||
transitionTable[Shared][Packet::WriteReq].onRequest(writeToSharedCmd);
|
||||
transitionTable[Owned][Packet::WriteReq].onRequest(writeToSharedCmd);
|
||||
//Prefetching causes a read
|
||||
transitionTable[Invalid][Packet::SoftPFReq].onRequest(Packet::ReadReq);
|
||||
transitionTable[Invalid][Packet::HardPFReq].onRequest(Packet::ReadReq);
|
||||
|
||||
// on response to given request: specify new state
|
||||
transitionTable[Invalid][Packet::ReadResp].onResponse(Shared);
|
||||
transitionTable[Invalid][Packet::ReadExResp].onResponse(Modified);
|
||||
transitionTable[Shared][writeToSharedResp].onResponse(Modified);
|
||||
transitionTable[Owned][writeToSharedResp].onResponse(Modified);
|
||||
|
||||
// bus snoop transition functions
|
||||
transitionTable[Invalid][Packet::ReadReq].onSnoop(nullTransition);
|
||||
transitionTable[Invalid][Packet::ReadExReq].onSnoop(nullTransition);
|
||||
transitionTable[Invalid][Packet::UpgradeReq].onSnoop(nullTransition);
|
||||
transitionTable[Shared][Packet::ReadReq].onSnoop(assertShared);
|
||||
transitionTable[Shared][Packet::ReadExReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Shared][Packet::UpgradeReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Modified][Packet::ReadExReq].onSnoop(supplyAndInvalidateTrans);
|
||||
transitionTable[Modified][Packet::ReadReq].onSnoop(supplyAndGotoOwnedTrans);
|
||||
transitionTable[Owned][Packet::ReadReq].onSnoop(supplyAndGotoOwnedTrans);
|
||||
transitionTable[Owned][Packet::ReadExReq].onSnoop(supplyAndInvalidateTrans);
|
||||
transitionTable[Owned][Packet::UpgradeReq].onSnoop(invalidateTrans);
|
||||
//Tansitions on seeing a DMA (writeInv(samelevel) or DMAInv)
|
||||
transitionTable[Invalid][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Shared][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Modified][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Owned][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Invalid][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Shared][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Modified][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Owned][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
}
|
||||
|
||||
else if(protocol == "moesi") {
|
||||
// incoming requests: specify outgoing bus request
|
||||
transitionTable[Invalid][Packet::ReadReq].onRequest(Packet::ReadReq);
|
||||
transitionTable[Invalid][Packet::WriteReq].onRequest(Packet::ReadExReq);
|
||||
transitionTable[Shared][Packet::WriteReq].onRequest(writeToSharedCmd);
|
||||
transitionTable[Owned][Packet::WriteReq].onRequest(writeToSharedCmd);
|
||||
//Prefetching causes a read
|
||||
transitionTable[Invalid][Packet::SoftPFReq].onRequest(Packet::ReadReq);
|
||||
transitionTable[Invalid][Packet::HardPFReq].onRequest(Packet::ReadReq);
|
||||
|
||||
// on response to given request: specify new state
|
||||
transitionTable[Invalid][Packet::ReadResp].onResponse(Exclusive);
|
||||
//It will move into shared if the shared line is asserted in the
|
||||
//getNewState function
|
||||
transitionTable[Invalid][Packet::ReadExResp].onResponse(Modified);
|
||||
transitionTable[Shared][writeToSharedResp].onResponse(Modified);
|
||||
transitionTable[Owned][writeToSharedResp].onResponse(Modified);
|
||||
|
||||
// bus snoop transition functions
|
||||
transitionTable[Invalid][Packet::ReadReq].onSnoop(nullTransition);
|
||||
transitionTable[Invalid][Packet::ReadExReq].onSnoop(nullTransition);
|
||||
transitionTable[Invalid][Packet::UpgradeReq].onSnoop(nullTransition);
|
||||
transitionTable[Shared][Packet::ReadReq].onSnoop(assertShared);
|
||||
transitionTable[Shared][Packet::ReadExReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Shared][Packet::UpgradeReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Exclusive][Packet::ReadReq].onSnoop(assertShared);
|
||||
transitionTable[Exclusive][Packet::ReadExReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Modified][Packet::ReadReq].onSnoop(supplyAndGotoOwnedTrans);
|
||||
transitionTable[Modified][Packet::ReadExReq].onSnoop(supplyAndInvalidateTrans);
|
||||
transitionTable[Owned][Packet::ReadReq].onSnoop(supplyAndGotoOwnedTrans);
|
||||
transitionTable[Owned][Packet::ReadExReq].onSnoop(supplyAndInvalidateTrans);
|
||||
transitionTable[Owned][Packet::UpgradeReq].onSnoop(invalidateTrans);
|
||||
//Transitions on seeing a DMA (writeInv(samelevel) or DMAInv)
|
||||
transitionTable[Invalid][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Shared][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Exclusive][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Modified][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Owned][Packet::InvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Invalid][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Shared][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Exclusive][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Modified][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
transitionTable[Owned][Packet::WriteInvalidateReq].onSnoop(invalidateTrans);
|
||||
}
|
||||
|
||||
else {
|
||||
cerr << "CoherenceProtocol: unrecognized protocol " << protocol
|
||||
<< endl;
|
||||
fatal("");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
20
src/mem/cache/coherence/coherence_protocol.hh
vendored
20
src/mem/cache/coherence/coherence_protocol.hh
vendored
|
|
@ -211,31 +211,25 @@ class CoherenceProtocol : public SimObject
|
|||
friend class CoherenceProtocol::StateTransition;
|
||||
|
||||
/** Mask to select status bits relevant to coherence protocol. */
|
||||
const static CacheBlk::State
|
||||
stateMask = BlkValid | BlkWritable | BlkDirty;
|
||||
static const int stateMask = BlkValid | BlkWritable | BlkDirty;
|
||||
|
||||
/** The Modified (M) state. */
|
||||
const static CacheBlk::State
|
||||
Modified = BlkValid | BlkWritable | BlkDirty;
|
||||
static const int Modified = BlkValid | BlkWritable | BlkDirty;
|
||||
/** The Owned (O) state. */
|
||||
const static CacheBlk::State
|
||||
Owned = BlkValid | BlkDirty;
|
||||
static const int Owned = BlkValid | BlkDirty;
|
||||
/** The Exclusive (E) state. */
|
||||
const static CacheBlk::State
|
||||
Exclusive = BlkValid | BlkWritable;
|
||||
static const int Exclusive = BlkValid | BlkWritable;
|
||||
/** The Shared (S) state. */
|
||||
const static CacheBlk::State
|
||||
Shared = BlkValid;
|
||||
static const int Shared = BlkValid;
|
||||
/** The Invalid (I) state. */
|
||||
const static CacheBlk::State
|
||||
Invalid = 0;
|
||||
static const int Invalid = 0;
|
||||
|
||||
/**
|
||||
* Maximum state encoding value (used to size transition lookup
|
||||
* table). Could be more than number of states, depends on
|
||||
* encoding of status bits.
|
||||
*/
|
||||
const static int stateMax = stateMask;
|
||||
static const int stateMax = stateMask;
|
||||
|
||||
/**
|
||||
* The table of all possible transitions, organized by starting state and
|
||||
|
|
|
|||
|
|
@ -51,16 +51,16 @@ typedef uint8_t* PacketDataPtr;
|
|||
typedef std::list<PacketPtr> PacketList;
|
||||
|
||||
//Coherence Flags
|
||||
#define NACKED_LINE 1 << 0
|
||||
#define SATISFIED 1 << 1
|
||||
#define SHARED_LINE 1 << 2
|
||||
#define CACHE_LINE_FILL 1 << 3
|
||||
#define COMPRESSED 1 << 4
|
||||
#define NO_ALLOCATE 1 << 5
|
||||
#define SNOOP_COMMIT 1 << 6
|
||||
#define NACKED_LINE (1 << 0)
|
||||
#define SATISFIED (1 << 1)
|
||||
#define SHARED_LINE (1 << 2)
|
||||
#define CACHE_LINE_FILL (1 << 3)
|
||||
#define COMPRESSED (1 << 4)
|
||||
#define NO_ALLOCATE (1 << 5)
|
||||
#define SNOOP_COMMIT (1 << 6)
|
||||
|
||||
//for now. @todo fix later
|
||||
#define NUM_MEM_CMDS 1 << 11
|
||||
#define NUM_MEM_CMDS (1 << 11)
|
||||
/**
|
||||
* A Packet is used to encapsulate a transfer between two objects in
|
||||
* the memory system (e.g., the L1 and L2 cache). (In contrast, a
|
||||
|
|
@ -205,8 +205,8 @@ class Packet
|
|||
InvalidateReq = IsInvalidate | IsRequest,
|
||||
WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest
|
||||
| HasData | NeedsResponse,
|
||||
WriteInvalidateResp = IsWrite | IsInvalidate | IsRequest | NeedsResponse
|
||||
| IsResponse,
|
||||
WriteInvalidateResp = IsWrite | IsInvalidate | IsRequest
|
||||
| NeedsResponse | IsResponse,
|
||||
UpgradeReq = IsInvalidate | IsRequest | IsUpgrade,
|
||||
ReadExReq = IsRead | IsInvalidate | IsRequest | NeedsResponse,
|
||||
ReadExResp = IsRead | IsInvalidate | IsResponse
|
||||
|
|
@ -310,6 +310,7 @@ class Packet
|
|||
* multiple transactions. */
|
||||
void reinitFromRequest() {
|
||||
assert(req->validPaddr);
|
||||
flags = 0;
|
||||
addr = req->paddr;
|
||||
size = req->size;
|
||||
time = req->time;
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@
|
|||
#if !FULL_SYSTEM
|
||||
void FaultBase::invoke(ThreadContext * tc)
|
||||
{
|
||||
fatal("fault (%s) detected @ PC 0x%08p", name(), tc->readPC());
|
||||
fatal("fault (%s) detected @ PC %p", name(), tc->readPC());
|
||||
}
|
||||
#else
|
||||
void FaultBase::invoke(ThreadContext * tc)
|
||||
|
|
|
|||
|
|
@ -87,10 +87,15 @@ namespace AlphaPseudo
|
|||
|
||||
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
|
||||
|
||||
Tick resume = curTick + Clock::Int::ns * ns;
|
||||
|
||||
if (quiesceEvent->scheduled())
|
||||
quiesceEvent->reschedule(curTick + Clock::Int::ns * ns);
|
||||
quiesceEvent->reschedule(resume);
|
||||
else
|
||||
quiesceEvent->schedule(curTick + Clock::Int::ns * ns);
|
||||
quiesceEvent->schedule(resume);
|
||||
|
||||
DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n",
|
||||
tc->getCpuPtr()->name(), ns, resume);
|
||||
|
||||
tc->suspend();
|
||||
if (tc->getKernelStats())
|
||||
|
|
@ -105,12 +110,15 @@ namespace AlphaPseudo
|
|||
|
||||
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
|
||||
|
||||
Tick resume = curTick + tc->getCpuPtr()->cycles(cycles);
|
||||
|
||||
if (quiesceEvent->scheduled())
|
||||
quiesceEvent->reschedule(curTick +
|
||||
tc->getCpuPtr()->cycles(cycles));
|
||||
quiesceEvent->reschedule(resume);
|
||||
else
|
||||
quiesceEvent->schedule(curTick +
|
||||
tc->getCpuPtr()->cycles(cycles));
|
||||
quiesceEvent->schedule(resume);
|
||||
|
||||
DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n",
|
||||
tc->getCpuPtr()->name(), cycles, resume);
|
||||
|
||||
tc->suspend();
|
||||
if (tc->getKernelStats())
|
||||
|
|
|
|||
|
|
@ -33,23 +33,63 @@
|
|||
# ******Note that you need to enable some trace flags in the args in order
|
||||
# to do anything useful!******
|
||||
#
|
||||
# If you want to pass different arguments to the two instances of m5,
|
||||
# you can embed them in the simulator arguments like this:
|
||||
# Script arguments are handled uniformly as follows:
|
||||
# - If the argument does not contain a '|' character, it is appended
|
||||
# to both command lines.
|
||||
# - If the argument has a '|' character in it, the text on either side
|
||||
# of the '|' is appended to the respective command lines. Note that
|
||||
# you'll have to quote the arg or escape the '|' with a backslash
|
||||
# so that the shell doesn't think you're doing a pipe.
|
||||
#
|
||||
# % tracediff "m5.opt --option1" "m5.opt --option2" [common args]
|
||||
# In other words, the arguments should look like the command line you
|
||||
# want to run, with "|" used to list the alternatives for the parts
|
||||
# that you want to differ between the two runs.
|
||||
#
|
||||
# For example:
|
||||
#
|
||||
# % tracediff m5.opt --opt1 "--opt2|--opt3" --opt4
|
||||
# would compare these two runs:
|
||||
# m5.opt --opt1 --opt2 --opt4
|
||||
# m5.opt --opt1 --opt3 --opt4
|
||||
#
|
||||
# If you want to compare two different simulator binaries, put a '|'
|
||||
# in the first script argument ("path1/m5.opt|path2/m5.opt"). If you
|
||||
# want to add arguments to one run only, just put a '|' in with text
|
||||
# only on one side ("--onlyOn1|"). You can do this with multiple
|
||||
# arguments together too ("|-a -b -c" adds three args to the second
|
||||
# run only).
|
||||
#
|
||||
|
||||
if (@ARGV < 2) {
|
||||
die "Usage: tracediff sim1 sim2 [--root.trace.flags=X args...]\n";
|
||||
die "Usage: tracediff \"sim1|sim2\" [common-arg \"arg1|arg2\" ...]\n";
|
||||
}
|
||||
|
||||
foreach $arg (@ARGV) {
|
||||
@pair = split('\|', $arg, -1); # -1 enables null trailing fields
|
||||
if ($#pair > 0) {
|
||||
push @cmd1, $pair[0];
|
||||
push @cmd2, $pair[1];
|
||||
} else {
|
||||
push @cmd1, $arg;
|
||||
push @cmd2, $arg;
|
||||
}
|
||||
}
|
||||
|
||||
# First two args are the two simulator binaries to compare
|
||||
$sim1 = shift;
|
||||
$sim2 = shift;
|
||||
$sim1 = shift @cmd1;
|
||||
$sim2 = shift @cmd2;
|
||||
|
||||
# Everything else on the command line is taken to be an m5 argument to
|
||||
# be given to both invocations
|
||||
$simargs = '"' . join('" "', @ARGV) . '"';
|
||||
# Everything else is a simulator arg.
|
||||
$args1 = join(' ', @cmd1);
|
||||
$args2 = join(' ', @cmd2);
|
||||
|
||||
# Common mistake: if you don't set any traceflags this often isn't
|
||||
# doing what you want.
|
||||
if ($args1 !~ /--trace-flags/) {
|
||||
print "****\n";
|
||||
print "**** WARNING: no trace flags set... you may not be diffing much!\n";
|
||||
print "****\n";
|
||||
}
|
||||
|
||||
# Run individual invocations in separate dirs so output and intermediate
|
||||
# files (particularly config.py and config.ini) don't conflict.
|
||||
|
|
@ -58,8 +98,8 @@ $dir2 = "tracediff-$$-2";
|
|||
mkdir($dir1) or die "Can't create dir $dir1\n";
|
||||
mkdir($dir2) or die "Can't create dir $dir2\n";
|
||||
|
||||
$cmd1 = "$sim1 -d $dir1 $simargs 2>&1 |";
|
||||
$cmd2 = "$sim2 -d $dir2 $simargs 2>&1 |";
|
||||
$cmd1 = "$sim1 -d $dir1 $args1 2>&1 |";
|
||||
$cmd2 = "$sim2 -d $dir2 $args2 2>&1 |";
|
||||
|
||||
# This only works if you have rundiff in your path. I just edit it
|
||||
# with an explicit path if necessary.
|
||||
|
|
|
|||
Loading…
Reference in a new issue