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ISA: Set up common trace flags for tracing registers.

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This commit is contained in:
Gabe Black 2009-02-25 10:22:17 -08:00
parent 44d5351071
commit 4633677145
6 changed files with 35 additions and 20 deletions
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5
src/arch/SConscript
View file

@ -126,3 +126,8 @@ else:
emitter = isa_desc_emitter) emitter = isa_desc_emitter)
env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
TraceFlag('IntRegs')
TraceFlag('FloatRegs')
TraceFlag('MiscRegs')
CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])

24
src/arch/sparc/floatregfile.cc
View file

@ -75,7 +75,8 @@ FloatReg FloatRegFile::readReg(int floatReg, int width)
result32 = htog(result32); result32 = htog(result32);
memcpy(&fresult32, &result32, sizeof(result32)); memcpy(&fresult32, &result32, sizeof(result32));
result = fresult32; result = fresult32;
DPRINTF(Sparc, "Read FP32 register %d = [%f]0x%x\n", floatReg, result, result32); DPRINTF(FloatRegs, "Read FP32 register %d = [%f]0x%x\n",
floatReg, result, result32);
break; break;
case DoubleWidth: case DoubleWidth:
uint64_t result64; uint64_t result64;
@ -84,7 +85,8 @@ FloatReg FloatRegFile::readReg(int floatReg, int width)
result64 = htog(result64); result64 = htog(result64);
memcpy(&fresult64, &result64, sizeof(result64)); memcpy(&fresult64, &result64, sizeof(result64));
result = fresult64; result = fresult64;
DPRINTF(Sparc, "Read FP64 register %d = [%f]0x%x\n", floatReg, result, result64); DPRINTF(FloatRegs, "Read FP64 register %d = [%f]0x%x\n",
floatReg, result, result64);
break; break;
case QuadWidth: case QuadWidth:
panic("Quad width FP not implemented."); panic("Quad width FP not implemented.");
@ -107,13 +109,15 @@ FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
uint32_t result32; uint32_t result32;
memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
result = htog(result32); result = htog(result32);
DPRINTF(Sparc, "Read FP32 bits register %d = 0x%x\n", floatReg, result); DPRINTF(FloatRegs, "Read FP32 bits register %d = 0x%x\n",
floatReg, result);
break; break;
case DoubleWidth: case DoubleWidth:
uint64_t result64; uint64_t result64;
memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
result = htog(result64); result = htog(result64);
DPRINTF(Sparc, "Read FP64 bits register %d = 0x%x\n", floatReg, result); DPRINTF(FloatRegs, "Read FP64 bits register %d = 0x%x\n",
floatReg, result);
break; break;
case QuadWidth: case QuadWidth:
panic("Quad width FP not implemented."); panic("Quad width FP not implemented.");
@ -141,14 +145,16 @@ Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
memcpy(&result32, &fresult32, sizeof(result32)); memcpy(&result32, &fresult32, sizeof(result32));
result32 = gtoh(result32); result32 = gtoh(result32);
memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result32); DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n",
floatReg, result32);
break; break;
case DoubleWidth: case DoubleWidth:
fresult64 = val; fresult64 = val;
memcpy(&result64, &fresult64, sizeof(result64)); memcpy(&result64, &fresult64, sizeof(result64));
result64 = gtoh(result64); result64 = gtoh(result64);
memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result64); DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n",
floatReg, result64);
break; break;
case QuadWidth: case QuadWidth:
panic("Quad width FP not implemented."); panic("Quad width FP not implemented.");
@ -171,12 +177,14 @@ Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
case SingleWidth: case SingleWidth:
result32 = gtoh((uint32_t)val); result32 = gtoh((uint32_t)val);
memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result32); DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n",
floatReg, result32);
break; break;
case DoubleWidth: case DoubleWidth:
result64 = gtoh((uint64_t)val); result64 = gtoh((uint64_t)val);
memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result64); DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n",
floatReg, result64);
break; break;
case QuadWidth: case QuadWidth:
panic("Quad width FP not implemented."); panic("Quad width FP not implemented.");

8
src/arch/sparc/intregfile.cc
View file

@ -70,7 +70,7 @@ IntRegFile::IntRegFile()
IntReg IntRegFile::readReg(int intReg) IntReg IntRegFile::readReg(int intReg)
{ {
DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, regs[intReg]); DPRINTF(IntRegs, "Read register %d = 0x%x\n", intReg, regs[intReg]);
return regs[intReg]; return regs[intReg];
/* XXX Currently not used. When used again regView/offset need to be /* XXX Currently not used. When used again regView/offset need to be
* serialized! * serialized!
@ -83,7 +83,7 @@ IntReg IntRegFile::readReg(int intReg)
panic("Tried to read non-existant integer register %d, %d\n", panic("Tried to read non-existant integer register %d, %d\n",
NumIntArchRegs + NumMicroIntRegs + intReg, intReg); NumIntArchRegs + NumMicroIntRegs + intReg, intReg);
DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val); DPRINTF(IntRegs, "Read register %d = 0x%x\n", intReg, val);
return val; return val;
*/ */
} }
@ -92,7 +92,7 @@ void IntRegFile::setReg(int intReg, const IntReg &val)
{ {
if(intReg) if(intReg)
{ {
DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val); DPRINTF(IntRegs, "Wrote register %d = 0x%x\n", intReg, val);
regs[intReg] = val; regs[intReg] = val;
} }
return; return;
@ -100,7 +100,7 @@ void IntRegFile::setReg(int intReg, const IntReg &val)
* serialized! * serialized!
if(intReg) if(intReg)
{ {
DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val); DPRINTF(IntRegs, "Wrote register %d = 0x%x\n", intReg, val);
if(intReg < NumIntArchRegs) if(intReg < NumIntArchRegs)
regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val; regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val;
else if((intReg -= NumIntArchRegs) < NumMicroIntRegs) else if((intReg -= NumIntArchRegs) < NumMicroIntRegs)

4
src/arch/sparc/miscregfile.cc
View file

@ -227,7 +227,7 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg)
/** Floating Point Status Register */ /** Floating Point Status Register */
case MISCREG_FSR: case MISCREG_FSR:
DPRINTF(Sparc, "FSR read as: %#x\n", fsr); DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr);
return fsr; return fsr;
case MISCREG_MMU_P_CONTEXT: case MISCREG_MMU_P_CONTEXT:
@ -446,7 +446,7 @@ void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
/** Floating Point Status Register */ /** Floating Point Status Register */
case MISCREG_FSR: case MISCREG_FSR:
fsr = val; fsr = val;
DPRINTF(Sparc, "FSR written with: %#x\n", fsr); DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr);
break; break;
case MISCREG_MMU_P_CONTEXT: case MISCREG_MMU_P_CONTEXT:

8
src/arch/x86/floatregfile.cc
View file

@ -113,27 +113,27 @@ void FloatRegFile::clear()
FloatReg FloatRegFile::readReg(int floatReg, int width) FloatReg FloatRegFile::readReg(int floatReg, int width)
{ {
FloatReg reg = d[floatReg]; FloatReg reg = d[floatReg];
DPRINTF(X86, "Reading %f from register %d.\n", reg, floatReg); DPRINTF(FloatRegs, "Reading %f from register %d.\n", reg, floatReg);
return reg; return reg;
} }
FloatRegBits FloatRegFile::readRegBits(int floatReg, int width) FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
{ {
FloatRegBits reg = q[floatReg]; FloatRegBits reg = q[floatReg];
DPRINTF(X86, "Reading %#x from register %d.\n", reg, floatReg); DPRINTF(FloatRegs, "Reading %#x from register %d.\n", reg, floatReg);
return reg; return reg;
} }
Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width) Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
{ {
DPRINTF(X86, "Writing %f to register %d.\n", val, floatReg); DPRINTF(FloatRegs, "Writing %f to register %d.\n", val, floatReg);
d[floatReg] = val; d[floatReg] = val;
return NoFault; return NoFault;
} }
Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width) Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
{ {
DPRINTF(X86, "Writing bits %#x to register %d.\n", val, floatReg); DPRINTF(FloatRegs, "Writing bits %#x to register %d.\n", val, floatReg);
q[floatReg] = val; q[floatReg] = val;
return NoFault; return NoFault;
} }

6
src/arch/x86/intregfile.cc
View file

@ -120,13 +120,15 @@ void IntRegFile::clear()
IntReg IntRegFile::readReg(int intReg) IntReg IntRegFile::readReg(int intReg)
{ {
DPRINTF(X86, "Read int reg %d and got value %#x\n", intReg, regs[intReg]); DPRINTF(IntRegs, "Read int reg %d and got value %#x\n",
intReg, regs[intReg]);
return regs[intReg]; return regs[intReg];
} }
void IntRegFile::setReg(int intReg, const IntReg &val) void IntRegFile::setReg(int intReg, const IntReg &val)
{ {
DPRINTF(X86, "Setting int reg %d to value %#x\n", intReg, val); DPRINTF(IntRegs, "Setting int reg %d to value %#x\n",
intReg, val);
regs[intReg] = val; regs[intReg] = val;
} }