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scons: Add missing override to appease clang

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Make clang happy...again.
This commit is contained in:
Andreas Hansson 2016-02-23 03:27:20 -05:00
parent 5a88f0931f
commit 4619f0ee8b
13 changed files with 117 additions and 114 deletions
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60
src/arch/hsail/insts/branch.hh
View file

@ -51,7 +51,7 @@ namespace HsailISA
class BrnInstBase : public HsailGPUStaticInst class BrnInstBase : public HsailGPUStaticInst
{ {
public: public:
void generateDisassembly(); void generateDisassembly() override;
Brig::BrigWidth8_t width; Brig::BrigWidth8_t width;
TargetType target; TargetType target;
@ -69,43 +69,43 @@ namespace HsailISA
uint32_t getTargetPc() override { return target.getTarget(0, 0); } uint32_t getTargetPc() override { return target.getTarget(0, 0); }
bool unconditionalJumpInstruction() override { return true; } bool unconditionalJumpInstruction() override { return true; }
bool isVectorRegister(int operandIndex) { bool isVectorRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isVectorRegister(); return target.isVectorRegister();
} }
bool isCondRegister(int operandIndex) { bool isCondRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isCondRegister(); return target.isCondRegister();
} }
bool isScalarRegister(int operandIndex) { bool isScalarRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isScalarRegister(); return target.isScalarRegister();
} }
bool isSrcOperand(int operandIndex) { bool isSrcOperand(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return true; return true;
} }
bool isDstOperand(int operandIndex) { bool isDstOperand(int operandIndex) override {
return false; return false;
} }
int getOperandSize(int operandIndex) { int getOperandSize(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.opSize(); return target.opSize();
} }
int getRegisterIndex(int operandIndex) { int getRegisterIndex(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.regIndex(); return target.regIndex();
} }
int getNumOperands() { int getNumOperands() override {
return 1; return 1;
} }
void execute(GPUDynInstPtr gpuDynInst); void execute(GPUDynInstPtr gpuDynInst) override;
}; };
template<typename TargetType> template<typename TargetType>
@ -166,7 +166,7 @@ namespace HsailISA
class CbrInstBase : public HsailGPUStaticInst class CbrInstBase : public HsailGPUStaticInst
{ {
public: public:
void generateDisassembly(); void generateDisassembly() override;
Brig::BrigWidth8_t width; Brig::BrigWidth8_t width;
CRegOperand cond; CRegOperand cond;
@ -186,47 +186,47 @@ namespace HsailISA
uint32_t getTargetPc() override { return target.getTarget(0, 0); } uint32_t getTargetPc() override { return target.getTarget(0, 0); }
void execute(GPUDynInstPtr gpuDynInst); void execute(GPUDynInstPtr gpuDynInst) override;
// Assumption: Target is operand 0, Condition Register is operand 1 // Assumption: Target is operand 0, Condition Register is operand 1
bool isVectorRegister(int operandIndex) { bool isVectorRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
if (!operandIndex) if (!operandIndex)
return target.isVectorRegister(); return target.isVectorRegister();
else else
return false; return false;
} }
bool isCondRegister(int operandIndex) { bool isCondRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
if (!operandIndex) if (!operandIndex)
return target.isCondRegister(); return target.isCondRegister();
else else
return true; return true;
} }
bool isScalarRegister(int operandIndex) { bool isScalarRegister(int operandIndex) override {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (!operandIndex) if (!operandIndex)
return target.isScalarRegister(); return target.isScalarRegister();
else else
return false; return false;
} }
bool isSrcOperand(int operandIndex) { bool isSrcOperand(int operandIndex) override {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex == 0) if (operandIndex == 0)
return true; return true;
return false; return false;
} }
// both Condition Register and Target are source operands // both Condition Register and Target are source operands
bool isDstOperand(int operandIndex) { bool isDstOperand(int operandIndex) override {
return false; return false;
} }
int getOperandSize(int operandIndex) { int getOperandSize(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
if (!operandIndex) if (!operandIndex)
return target.opSize(); return target.opSize();
else else
return 1; return 1;
} }
int getRegisterIndex(int operandIndex) { int getRegisterIndex(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
if (!operandIndex) if (!operandIndex)
return target.regIndex(); return target.regIndex();
@ -235,7 +235,7 @@ namespace HsailISA
} }
// Operands = Target, Condition Register // Operands = Target, Condition Register
int getNumOperands() { int getNumOperands() override {
return 2; return 2;
} }
}; };
@ -335,7 +335,7 @@ namespace HsailISA
class BrInstBase : public HsailGPUStaticInst class BrInstBase : public HsailGPUStaticInst
{ {
public: public:
void generateDisassembly(); void generateDisassembly() override;
ImmOperand<uint32_t> width; ImmOperand<uint32_t> width;
TargetType target; TargetType target;
@ -354,33 +354,33 @@ namespace HsailISA
bool unconditionalJumpInstruction() override { return true; } bool unconditionalJumpInstruction() override { return true; }
void execute(GPUDynInstPtr gpuDynInst); void execute(GPUDynInstPtr gpuDynInst) override;
bool isVectorRegister(int operandIndex) { bool isVectorRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isVectorRegister(); return target.isVectorRegister();
} }
bool isCondRegister(int operandIndex) { bool isCondRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isCondRegister(); return target.isCondRegister();
} }
bool isScalarRegister(int operandIndex) { bool isScalarRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isScalarRegister(); return target.isScalarRegister();
} }
bool isSrcOperand(int operandIndex) { bool isSrcOperand(int operandIndex) override {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return true; return true;
} }
bool isDstOperand(int operandIndex) { return false; } bool isDstOperand(int operandIndex) override { return false; }
int getOperandSize(int operandIndex) { int getOperandSize(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.opSize(); return target.opSize();
} }
int getRegisterIndex(int operandIndex) { int getRegisterIndex(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.regIndex(); return target.regIndex();
} }
int getNumOperands() { return 1; } int getNumOperands() override { return 1; }
}; };
template<typename TargetType> template<typename TargetType>

107
src/arch/hsail/insts/mem.hh
View file

@ -102,50 +102,52 @@ namespace HsailISA
addr.init(op_offs, obj); addr.init(op_offs, obj);
} }
int numSrcRegOperands() { return(this->addr.isVectorRegister()); } int numSrcRegOperands() override
int numDstRegOperands() { return dest.isVectorRegister(); } { return(this->addr.isVectorRegister()); }
bool isVectorRegister(int operandIndex) int numDstRegOperands() override
{ return dest.isVectorRegister(); }
bool isVectorRegister(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.isVectorRegister() : return((operandIndex == 0) ? dest.isVectorRegister() :
this->addr.isVectorRegister()); this->addr.isVectorRegister());
} }
bool isCondRegister(int operandIndex) bool isCondRegister(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.isCondRegister() : return((operandIndex == 0) ? dest.isCondRegister() :
this->addr.isCondRegister()); this->addr.isCondRegister());
} }
bool isScalarRegister(int operandIndex) bool isScalarRegister(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.isScalarRegister() : return((operandIndex == 0) ? dest.isScalarRegister() :
this->addr.isScalarRegister()); this->addr.isScalarRegister());
} }
bool isSrcOperand(int operandIndex) bool isSrcOperand(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex > 0) if (operandIndex > 0)
return(this->addr.isVectorRegister()); return(this->addr.isVectorRegister());
return false; return false;
} }
bool isDstOperand(int operandIndex) { bool isDstOperand(int operandIndex) override {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return(operandIndex == 0); return(operandIndex == 0);
} }
int getOperandSize(int operandIndex) int getOperandSize(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.opSize() : return((operandIndex == 0) ? dest.opSize() :
this->addr.opSize()); this->addr.opSize());
} }
int getRegisterIndex(int operandIndex) int getRegisterIndex(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.regIndex() : return((operandIndex == 0) ? dest.regIndex() :
this->addr.regIndex()); this->addr.regIndex());
} }
int getNumOperands() int getNumOperands() override
{ {
if (this->addr.isVectorRegister()) if (this->addr.isVectorRegister())
return 2; return 2;
@ -348,52 +350,53 @@ namespace HsailISA
} }
} }
int numSrcRegOperands() { return(this->addr.isVectorRegister()); } int numSrcRegOperands() override
int numDstRegOperands() { return dest.isVectorRegister(); } { return(this->addr.isVectorRegister()); }
int getNumOperands() int numDstRegOperands() override { return dest.isVectorRegister(); }
int getNumOperands() override
{ {
if (this->addr.isVectorRegister()) if (this->addr.isVectorRegister())
return 2; return 2;
else else
return 1; return 1;
} }
bool isVectorRegister(int operandIndex) bool isVectorRegister(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.isVectorRegister() : return((operandIndex == 0) ? dest.isVectorRegister() :
this->addr.isVectorRegister()); this->addr.isVectorRegister());
} }
bool isCondRegister(int operandIndex) bool isCondRegister(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.isCondRegister() : return((operandIndex == 0) ? dest.isCondRegister() :
this->addr.isCondRegister()); this->addr.isCondRegister());
} }
bool isScalarRegister(int operandIndex) bool isScalarRegister(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.isScalarRegister() : return((operandIndex == 0) ? dest.isScalarRegister() :
this->addr.isScalarRegister()); this->addr.isScalarRegister());
} }
bool isSrcOperand(int operandIndex) bool isSrcOperand(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex > 0) if (operandIndex > 0)
return(this->addr.isVectorRegister()); return(this->addr.isVectorRegister());
return false; return false;
} }
bool isDstOperand(int operandIndex) bool isDstOperand(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return(operandIndex == 0); return(operandIndex == 0);
} }
int getOperandSize(int operandIndex) int getOperandSize(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.opSize() : return((operandIndex == 0) ? dest.opSize() :
this->addr.opSize()); this->addr.opSize());
} }
int getRegisterIndex(int operandIndex) int getRegisterIndex(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.regIndex() : return((operandIndex == 0) ? dest.regIndex() :
@ -410,7 +413,7 @@ namespace HsailISA
{ {
typename DestDataType::OperandType::DestOperand dest_vect[4]; typename DestDataType::OperandType::DestOperand dest_vect[4];
uint16_t num_dest_operands; uint16_t num_dest_operands;
void generateDisassembly(); void generateDisassembly() override;
public: public:
LdInst(const Brig::BrigInstBase *ib, const BrigObject *obj, LdInst(const Brig::BrigInstBase *ib, const BrigObject *obj,
@ -539,7 +542,7 @@ namespace HsailISA
return this->segment == Brig::BRIG_SEGMENT_GROUP; return this->segment == Brig::BRIG_SEGMENT_GROUP;
} }
bool isVectorRegister(int operandIndex) bool isVectorRegister(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if ((num_dest_operands != getNumOperands()) && if ((num_dest_operands != getNumOperands()) &&
@ -555,7 +558,7 @@ namespace HsailISA
} }
return false; return false;
} }
bool isCondRegister(int operandIndex) bool isCondRegister(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if ((num_dest_operands != getNumOperands()) && if ((num_dest_operands != getNumOperands()) &&
@ -569,7 +572,7 @@ namespace HsailISA
AddrOperandType>::dest.isCondRegister(); AddrOperandType>::dest.isCondRegister();
return false; return false;
} }
bool isScalarRegister(int operandIndex) bool isScalarRegister(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if ((num_dest_operands != getNumOperands()) && if ((num_dest_operands != getNumOperands()) &&
@ -583,7 +586,7 @@ namespace HsailISA
AddrOperandType>::dest.isScalarRegister(); AddrOperandType>::dest.isScalarRegister();
return false; return false;
} }
bool isSrcOperand(int operandIndex) bool isSrcOperand(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if ((num_dest_operands != getNumOperands()) && if ((num_dest_operands != getNumOperands()) &&
@ -591,7 +594,7 @@ namespace HsailISA
return(this->addr.isVectorRegister()); return(this->addr.isVectorRegister());
return false; return false;
} }
bool isDstOperand(int operandIndex) bool isDstOperand(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if ((num_dest_operands != getNumOperands()) && if ((num_dest_operands != getNumOperands()) &&
@ -599,7 +602,7 @@ namespace HsailISA
return false; return false;
return true; return true;
} }
int getOperandSize(int operandIndex) int getOperandSize(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if ((num_dest_operands != getNumOperands()) && if ((num_dest_operands != getNumOperands()) &&
@ -613,7 +616,7 @@ namespace HsailISA
AddrOperandType>::dest.opSize()); AddrOperandType>::dest.opSize());
return 0; return 0;
} }
int getRegisterIndex(int operandIndex) int getRegisterIndex(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if ((num_dest_operands != getNumOperands()) && if ((num_dest_operands != getNumOperands()) &&
@ -627,14 +630,14 @@ namespace HsailISA
AddrOperandType>::dest.regIndex()); AddrOperandType>::dest.regIndex());
return -1; return -1;
} }
int getNumOperands() int getNumOperands() override
{ {
if (this->addr.isVectorRegister() || this->addr.isScalarRegister()) if (this->addr.isVectorRegister() || this->addr.isScalarRegister())
return(num_dest_operands+1); return(num_dest_operands+1);
else else
return(num_dest_operands); return(num_dest_operands);
} }
void execute(GPUDynInstPtr gpuDynInst); void execute(GPUDynInstPtr gpuDynInst) override;
}; };
template<typename MemDT, typename DestDT> template<typename MemDT, typename DestDT>
@ -851,48 +854,48 @@ namespace HsailISA
} }
} }
int numDstRegOperands() { return 0; } int numDstRegOperands() override { return 0; }
int numSrcRegOperands() int numSrcRegOperands() override
{ {
return src.isVectorRegister() + this->addr.isVectorRegister(); return src.isVectorRegister() + this->addr.isVectorRegister();
} }
int getNumOperands() int getNumOperands() override
{ {
if (this->addr.isVectorRegister() || this->addr.isScalarRegister()) if (this->addr.isVectorRegister() || this->addr.isScalarRegister())
return 2; return 2;
else else
return 1; return 1;
} }
bool isVectorRegister(int operandIndex) bool isVectorRegister(int operandIndex) override
{ {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return !operandIndex ? src.isVectorRegister() : return !operandIndex ? src.isVectorRegister() :
this->addr.isVectorRegister(); this->addr.isVectorRegister();
} }
bool isCondRegister(int operandIndex) bool isCondRegister(int operandIndex) override
{ {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return !operandIndex ? src.isCondRegister() : return !operandIndex ? src.isCondRegister() :
this->addr.isCondRegister(); this->addr.isCondRegister();
} }
bool isScalarRegister(int operandIndex) bool isScalarRegister(int operandIndex) override
{ {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return !operandIndex ? src.isScalarRegister() : return !operandIndex ? src.isScalarRegister() :
this->addr.isScalarRegister(); this->addr.isScalarRegister();
} }
bool isSrcOperand(int operandIndex) bool isSrcOperand(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return true; return true;
} }
bool isDstOperand(int operandIndex) { return false; } bool isDstOperand(int operandIndex) override { return false; }
int getOperandSize(int operandIndex) int getOperandSize(int operandIndex) override
{ {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return !operandIndex ? src.opSize() : this->addr.opSize(); return !operandIndex ? src.opSize() : this->addr.opSize();
} }
int getRegisterIndex(int operandIndex) int getRegisterIndex(int operandIndex) override
{ {
assert(operandIndex >= 0 && operandIndex < getNumOperands()); assert(operandIndex >= 0 && operandIndex < getNumOperands());
return !operandIndex ? src.regIndex() : this->addr.regIndex(); return !operandIndex ? src.regIndex() : this->addr.regIndex();
@ -910,7 +913,7 @@ namespace HsailISA
public: public:
typename SrcDataType::OperandType::SrcOperand src_vect[4]; typename SrcDataType::OperandType::SrcOperand src_vect[4];
uint16_t num_src_operands; uint16_t num_src_operands;
void generateDisassembly(); void generateDisassembly() override;
StInst(const Brig::BrigInstBase *ib, const BrigObject *obj, StInst(const Brig::BrigInstBase *ib, const BrigObject *obj,
const char *_opcode, int srcIdx) const char *_opcode, int srcIdx)
@ -1045,7 +1048,7 @@ namespace HsailISA
} }
public: public:
bool isVectorRegister(int operandIndex) bool isVectorRegister(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex == num_src_operands) if (operandIndex == num_src_operands)
@ -1058,7 +1061,7 @@ namespace HsailISA
AddrOperandType>::src.isVectorRegister(); AddrOperandType>::src.isVectorRegister();
return false; return false;
} }
bool isCondRegister(int operandIndex) bool isCondRegister(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex == num_src_operands) if (operandIndex == num_src_operands)
@ -1071,7 +1074,7 @@ namespace HsailISA
AddrOperandType>::src.isCondRegister(); AddrOperandType>::src.isCondRegister();
return false; return false;
} }
bool isScalarRegister(int operandIndex) bool isScalarRegister(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex == num_src_operands) if (operandIndex == num_src_operands)
@ -1084,13 +1087,13 @@ namespace HsailISA
AddrOperandType>::src.isScalarRegister(); AddrOperandType>::src.isScalarRegister();
return false; return false;
} }
bool isSrcOperand(int operandIndex) bool isSrcOperand(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return true; return true;
} }
bool isDstOperand(int operandIndex) { return false; } bool isDstOperand(int operandIndex) override { return false; }
int getOperandSize(int operandIndex) int getOperandSize(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex == num_src_operands) if (operandIndex == num_src_operands)
@ -1103,7 +1106,7 @@ namespace HsailISA
AddrOperandType>::src.opSize(); AddrOperandType>::src.opSize();
return 0; return 0;
} }
int getRegisterIndex(int operandIndex) int getRegisterIndex(int operandIndex) override
{ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands())); assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex == num_src_operands) if (operandIndex == num_src_operands)
@ -1116,14 +1119,14 @@ namespace HsailISA
AddrOperandType>::src.regIndex(); AddrOperandType>::src.regIndex();
return -1; return -1;
} }
int getNumOperands() int getNumOperands() override
{ {
if (this->addr.isVectorRegister() || this->addr.isScalarRegister()) if (this->addr.isVectorRegister() || this->addr.isScalarRegister())
return num_src_operands + 1; return num_src_operands + 1;
else else
return num_src_operands; return num_src_operands;
} }
void execute(GPUDynInstPtr gpuDynInst); void execute(GPUDynInstPtr gpuDynInst) override;
}; };
template<typename DataType, typename SrcDataType> template<typename DataType, typename SrcDataType>
@ -1332,7 +1335,7 @@ namespace HsailISA
public MemInst public MemInst
{ {
public: public:
void generateDisassembly(); void generateDisassembly() override;
AtomicInst(const Brig::BrigInstBase *ib, const BrigObject *obj, AtomicInst(const Brig::BrigInstBase *ib, const BrigObject *obj,
const char *_opcode) const char *_opcode)
@ -1376,7 +1379,7 @@ namespace HsailISA
} }
void execute(GPUDynInstPtr gpuDynInst); void execute(GPUDynInstPtr gpuDynInst) override;
bool bool
isLocalMem() const override isLocalMem() const override

8
src/arch/mips/tlb.hh
View file

@ -87,7 +87,7 @@ class TLB : public BaseTLB
MipsISA::PTE *getEntry(unsigned) const; MipsISA::PTE *getEntry(unsigned) const;
virtual ~TLB(); virtual ~TLB();
void takeOverFrom(BaseTLB *otlb) {} void takeOverFrom(BaseTLB *otlb) override {}
int smallPages; int smallPages;
int getsize() const { return size; } int getsize() const { return size; }
@ -95,8 +95,8 @@ class TLB : public BaseTLB
MipsISA::PTE &index(bool advance = true); MipsISA::PTE &index(bool advance = true);
void insert(Addr vaddr, MipsISA::PTE &pte); void insert(Addr vaddr, MipsISA::PTE &pte);
void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages); void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
void flushAll(); void flushAll() override;
void demapPage(Addr vaddr, uint64_t asn) void demapPage(Addr vaddr, uint64_t asn) override
{ {
panic("demapPage unimplemented.\n"); panic("demapPage unimplemented.\n");
} }
@ -110,7 +110,7 @@ class TLB : public BaseTLB
void serialize(CheckpointOut &cp) const override; void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override; void unserialize(CheckpointIn &cp) override;
void regStats(); void regStats() override;
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc, void translateTiming(RequestPtr req, ThreadContext *tc,

8
src/arch/power/tlb.hh
View file

@ -133,7 +133,7 @@ class TLB : public BaseTLB
TLB(const Params *p); TLB(const Params *p);
virtual ~TLB(); virtual ~TLB();
void takeOverFrom(BaseTLB *otlb) {} void takeOverFrom(BaseTLB *otlb) override {}
int probeEntry(Addr vpn,uint8_t) const; int probeEntry(Addr vpn,uint8_t) const;
PowerISA::PTE *getEntry(unsigned) const; PowerISA::PTE *getEntry(unsigned) const;
@ -149,10 +149,10 @@ class TLB : public BaseTLB
PowerISA::PTE &index(bool advance = true); PowerISA::PTE &index(bool advance = true);
void insert(Addr vaddr, PowerISA::PTE &pte); void insert(Addr vaddr, PowerISA::PTE &pte);
void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages); void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages);
void flushAll(); void flushAll() override;
void void
demapPage(Addr vaddr, uint64_t asn) demapPage(Addr vaddr, uint64_t asn) override
{ {
panic("demapPage unimplemented.\n"); panic("demapPage unimplemented.\n");
} }
@ -175,7 +175,7 @@ class TLB : public BaseTLB
void serialize(CheckpointOut &cp) const override; void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override; void unserialize(CheckpointIn &cp) override;
void regStats(); void regStats() override;
}; };
} // namespace PowerISA } // namespace PowerISA

4
src/arch/sparc/system.hh
View file

@ -123,8 +123,8 @@ class SparcSystem : public System
return addFuncEvent<T>(openbootSymtab, lbl); return addFuncEvent<T>(openbootSymtab, lbl);
} }
virtual Addr Addr
fixFuncEventAddr(Addr addr) fixFuncEventAddr(Addr addr) override
{ {
//XXX This may eventually have to do something useful. //XXX This may eventually have to do something useful.
return addr; return addr;

4
src/cpu/checker/cpu.hh
View file

@ -328,13 +328,13 @@ class CheckerCPU : public BaseCPU, public ExecContext
} }
#if THE_ISA == MIPS_ISA #if THE_ISA == MIPS_ISA
MiscReg readRegOtherThread(int misc_reg, ThreadID tid) MiscReg readRegOtherThread(int misc_reg, ThreadID tid) override
{ {
panic("MIPS MT not defined for CheckerCPU.\n"); panic("MIPS MT not defined for CheckerCPU.\n");
return 0; return 0;
} }
void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) override
{ {
panic("MIPS MT not defined for CheckerCPU.\n"); panic("MIPS MT not defined for CheckerCPU.\n");
} }

8
src/dev/mips/malta.hh
View file

@ -87,22 +87,22 @@ class Malta : public Platform
/** /**
* Cause the cpu to post a serial interrupt to the CPU. * Cause the cpu to post a serial interrupt to the CPU.
*/ */
virtual void postConsoleInt(); void postConsoleInt() override;
/** /**
* Clear a posted CPU interrupt (id=55) * Clear a posted CPU interrupt (id=55)
*/ */
virtual void clearConsoleInt(); void clearConsoleInt() override;
/** /**
* Cause the chipset to post a cpi interrupt to the CPU. * Cause the chipset to post a cpi interrupt to the CPU.
*/ */
virtual void postPciInt(int line); void postPciInt(int line) override;
/** /**
* Clear a posted PCI->CPU interrupt * Clear a posted PCI->CPU interrupt
*/ */
virtual void clearPciInt(int line); void clearPciInt(int line) override;
virtual Addr pciToDma(Addr pciAddr) const; virtual Addr pciToDma(Addr pciAddr) const;

4
src/dev/mips/malta_cchip.hh
View file

@ -94,9 +94,9 @@ class MaltaCChip : public BasicPioDevice
*/ */
MaltaCChip(Params *p); MaltaCChip(Params *p);
virtual Tick read(PacketPtr pkt); Tick read(PacketPtr pkt) override;
virtual Tick write(PacketPtr pkt); Tick write(PacketPtr pkt) override;
/** /**
* post an RTC interrupt to the CPU * post an RTC interrupt to the CPU

6
src/dev/mips/malta_io.hh
View file

@ -120,8 +120,8 @@ class MaltaIO : public BasicPioDevice
*/ */
MaltaIO(const Params *p); MaltaIO(const Params *p);
virtual Tick read(PacketPtr pkt); Tick read(PacketPtr pkt) override;
virtual Tick write(PacketPtr pkt); Tick write(PacketPtr pkt) override;
/** Post an Interrupt to the CPU */ /** Post an Interrupt to the CPU */
@ -136,7 +136,7 @@ class MaltaIO : public BasicPioDevice
/** /**
* Start running. * Start running.
*/ */
virtual void startup(); void startup() override;
}; };

4
src/dev/sparc/dtod.hh
View file

@ -60,8 +60,8 @@ class DumbTOD : public BasicPioDevice
return dynamic_cast<const Params *>(_params); return dynamic_cast<const Params *>(_params);
} }
virtual Tick read(PacketPtr pkt); Tick read(PacketPtr pkt) override;
virtual Tick write(PacketPtr pkt); Tick write(PacketPtr pkt) override;
void serialize(CheckpointOut &cp) const override; void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override; void unserialize(CheckpointIn &cp) override;

6
src/dev/sparc/iob.hh
View file

@ -132,14 +132,14 @@ class Iob : public PioDevice
return dynamic_cast<const Params *>(_params); return dynamic_cast<const Params *>(_params);
} }
virtual Tick read(PacketPtr pkt); Tick read(PacketPtr pkt) override;
virtual Tick write(PacketPtr pkt); Tick write(PacketPtr pkt) override;
void generateIpi(Type type, int cpu_id, int vector); void generateIpi(Type type, int cpu_id, int vector);
void receiveDeviceInterrupt(DeviceId devid); void receiveDeviceInterrupt(DeviceId devid);
bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
uint64_t d1); uint64_t d1);
AddrRangeList getAddrRanges() const; AddrRangeList getAddrRanges() const override;
void serialize(CheckpointOut &cp) const override; void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override; void unserialize(CheckpointIn &cp) override;

4
src/dev/sparc/mm_disk.hh
View file

@ -58,8 +58,8 @@ class MmDisk : public BasicPioDevice
return dynamic_cast<const Params *>(_params); return dynamic_cast<const Params *>(_params);
} }
virtual Tick read(PacketPtr pkt); Tick read(PacketPtr pkt) override;
virtual Tick write(PacketPtr pkt); Tick write(PacketPtr pkt) override;
void serialize(CheckpointOut &cp) const override; void serialize(CheckpointOut &cp) const override;
}; };

8
src/mem/ruby/system/DMASequencer.hh
View file

@ -56,11 +56,11 @@ class DMASequencer : public RubyPort
void init() override; void init() override;
/* external interface */ /* external interface */
RequestStatus makeRequest(PacketPtr pkt); RequestStatus makeRequest(PacketPtr pkt) override;
bool busy() { return m_is_busy;} bool busy() { return m_is_busy;}
int outstandingCount() const { return (m_is_busy ? 1 : 0); } int outstandingCount() const override { return (m_is_busy ? 1 : 0); }
bool isDeadlockEventScheduled() const { return false; } bool isDeadlockEventScheduled() const override { return false; }
void descheduleDeadlockEvent() {} void descheduleDeadlockEvent() override {}
/* SLICC callback */ /* SLICC callback */
void dataCallback(const DataBlock & dblk); void dataCallback(const DataBlock & dblk);