Faults: Replace calls to genMachineCheckFault with M5PanicFault.

This commit is contained in:
Gabe Black 2011-09-27 00:24:43 -07:00
parent 2ed3eef9b0
commit 44ed4849d4
9 changed files with 19 additions and 41 deletions

View file

@ -84,11 +84,6 @@ class AlignmentFault : public AlphaFault
bool isAlignmentFault() const {return true;} bool isAlignmentFault() const {return true;}
}; };
static inline Fault genMachineCheckFault()
{
return new MachineCheckFault;
}
class ResetFault : public AlphaFault class ResetFault : public AlphaFault
{ {
private: private:

View file

@ -36,6 +36,7 @@
#include "arch/alpha/faults.hh" #include "arch/alpha/faults.hh"
#include "arch/alpha/pagetable.hh" #include "arch/alpha/pagetable.hh"
#include "arch/alpha/tlb.hh" #include "arch/alpha/tlb.hh"
#include "arch/generic/debugfaults.hh"
#include "base/inifile.hh" #include "base/inifile.hh"
#include "base/str.hh" #include "base/str.hh"
#include "base/trace.hh" #include "base/trace.hh"
@ -434,8 +435,9 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
} }
// check that the physical address is ok (catch bad physical addresses) // check that the physical address is ok (catch bad physical addresses)
if (req->getPaddr() & ~PAddrImplMask) if (req->getPaddr() & ~PAddrImplMask) {
return genMachineCheckFault(); return new MachineCheckFault();
}
return checkCacheability(req, true); return checkCacheability(req, true);
@ -562,8 +564,9 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
} }
// check that the physical address is ok (catch bad physical addresses) // check that the physical address is ok (catch bad physical addresses)
if (req->getPaddr() & ~PAddrImplMask) if (req->getPaddr() & ~PAddrImplMask) {
return genMachineCheckFault(); return new MachineCheckFault();
}
return checkCacheability(req); return checkCacheability(req);
} }

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@ -242,11 +242,6 @@ class FlushPipe : public ArmFaultVals<FlushPipe>
StaticInstPtr inst = StaticInst::nullStaticInstPtr); StaticInstPtr inst = StaticInst::nullStaticInstPtr);
}; };
static inline Fault genMachineCheckFault()
{
return new Reset();
}
// A fault that flushes the pipe, excluding the faulting instructions // A fault that flushes the pipe, excluding the faulting instructions
class ArmSev : public ArmFaultVals<ArmSev> class ArmSev : public ArmFaultVals<ArmSev>
{ {

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@ -128,11 +128,6 @@ class MachineCheckFault : public MipsFault<MachineCheckFault>
bool isMachineCheckFault() { return true; } bool isMachineCheckFault() { return true; }
}; };
static inline Fault genMachineCheckFault()
{
return new MachineCheckFault;
}
class ResetFault : public MipsFault<ResetFault> class ResetFault : public MipsFault<ResetFault>
{ {
public: public:

View file

@ -85,13 +85,6 @@ class AlignmentFault : public PowerFault
} }
}; };
static inline Fault
genMachineCheckFault()
{
return new MachineCheckFault();
}
} // namespace PowerISA } // namespace PowerISA
#endif // __ARCH_POWER_FAULTS_HH__ #endif // __ARCH_POWER_FAULTS_HH__

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@ -287,13 +287,6 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction>
#endif #endif
}; };
static inline Fault
genMachineCheckFault()
{
return new InternalProcessorError;
}
} // namespace SparcISA } // namespace SparcISA
#endif // __SPARC_FAULTS_HH__ #endif // __SPARC_FAULTS_HH__

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@ -363,11 +363,6 @@ namespace X86ISA
{} {}
}; };
static inline Fault genMachineCheckFault()
{
return new MachineCheck;
}
class SIMDFloatingPointFault : public X86Fault class SIMDFloatingPointFault : public X86Fault
{ {
public: public:

View file

@ -38,6 +38,7 @@
#include <queue> #include <queue>
#include "arch/faults.hh" #include "arch/faults.hh"
#include "arch/generic/debugfaults.hh"
#include "arch/isa_traits.hh" #include "arch/isa_traits.hh"
#include "arch/locked_mem.hh" #include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh" #include "arch/mmapped_ipr.hh"
@ -568,7 +569,9 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
delete sreqLow; delete sreqLow;
delete sreqHigh; delete sreqHigh;
} }
return TheISA::genMachineCheckFault(); return new GenericISA::M5PanicFault(
"Uncachable load [sn:%llx] PC %s\n",
load_inst->seqNum, load_inst->pcState());
} }
// Check the SQ for any previous stores that might lead to forwarding // Check the SQ for any previous stores that might lead to forwarding

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@ -41,6 +41,7 @@
* Korey Sewell * Korey Sewell
*/ */
#include "arch/generic/debugfaults.hh"
#include "arch/locked_mem.hh" #include "arch/locked_mem.hh"
#include "base/str.hh" #include "base/str.hh"
#include "config/the_isa.hh" #include "config/the_isa.hh"
@ -539,7 +540,10 @@ LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst)
++lsqMemOrderViolation; ++lsqMemOrderViolation;
return TheISA::genMachineCheckFault(); return new GenericISA::M5PanicFault(
"Detected fault with inst [sn:%lli] and "
"[sn:%lli] at address %#x\n",
inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
} }
} }
@ -563,7 +567,9 @@ LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst)
++lsqMemOrderViolation; ++lsqMemOrderViolation;
return TheISA::genMachineCheckFault(); return new GenericISA::M5PanicFault("Detected fault with "
"inst [sn:%lli] and [sn:%lli] at address %#x\n",
inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
} }
} }