MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly.
arch/alpha/alpha_memory.cc: cpu/base_dyn_inst.cc: dev/alpha_console.cc: dev/pcidev.hh: dev/sinic.cc: MachineCheckFaults are now generated by the ISA, rather than being created directly. --HG-- extra : convert_revision : 34a7da41639e93be21ed70dac681b27480008d19
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7 changed files with 46 additions and 16 deletions
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@ -380,7 +380,7 @@ AlphaITB::translate(MemReqPtr &req) const
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// check that the physical address is ok (catch bad physical addresses)
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// check that the physical address is ok (catch bad physical addresses)
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if (req->paddr & ~PAddrImplMask)
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if (req->paddr & ~PAddrImplMask)
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return new MachineCheckFault;
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return genMachineCheckFault();
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checkCacheability(req);
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checkCacheability(req);
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@ -511,7 +511,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
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fault(req, write ? MM_STAT_WR_MASK : 0);
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fault(req, write ? MM_STAT_WR_MASK : 0);
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DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
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DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
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req->size);
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req->size);
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return new AlignmentFault;
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return genAlignmentFault();
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}
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}
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if (pc & 0x1) {
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if (pc & 0x1) {
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@ -621,7 +621,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
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// check that the physical address is ok (catch bad physical addresses)
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// check that the physical address is ok (catch bad physical addresses)
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if (req->paddr & ~PAddrImplMask)
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if (req->paddr & ~PAddrImplMask)
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return new MachineCheckFault;
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return genMachineCheckFault();
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checkCacheability(req);
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checkCacheability(req);
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@ -32,6 +32,10 @@ FaultName AlphaFault::_name = "alphafault";
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FaultVect AlphaFault::_vect = 0x0000;
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FaultVect AlphaFault::_vect = 0x0000;
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FaultStat AlphaFault::_stat;
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FaultStat AlphaFault::_stat;
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FaultVect AlphaMachineCheckFault::_vect = 0x0401;
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FaultVect AlphaAlignmentFault::_vect = 0x0301;
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FaultName ResetFault::_name = "reset";
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FaultName ResetFault::_name = "reset";
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FaultVect ResetFault::_vect = 0x0001;
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FaultVect ResetFault::_vect = 0x0001;
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FaultStat ResetFault::_stat;
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FaultStat ResetFault::_stat;
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@ -31,7 +31,7 @@
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#include "sim/faults.hh"
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#include "sim/faults.hh"
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// The reasoning behind the name and vect functions is in sim/faults.hh
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// The design of the "name" and "vect" functions is in sim/faults.hh
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typedef const Addr FaultVect;
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typedef const Addr FaultVect;
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@ -47,6 +47,32 @@ class AlphaFault : public FaultBase
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virtual FaultStat & stat() {return _stat;}
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virtual FaultStat & stat() {return _stat;}
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};
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};
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class AlphaMachineCheckFault : public MachineCheckFault
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{
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private:
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static FaultVect _vect;
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public:
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FaultVect vect() {return _vect;}
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};
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class AlphaAlignmentFault : public AlignmentFault
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{
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private:
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static FaultVect _vect;
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public:
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FaultVect vect() {return _vect;}
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};
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static inline Fault genMachineCheckFault()
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{
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return new AlphaMachineCheckFault;
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}
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static inline Fault genAlignmentFault()
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{
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return new AlphaAlignmentFault;
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}
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class ResetFault : public AlphaFault
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class ResetFault : public AlphaFault
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{
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{
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private:
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private:
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@ -215,7 +241,4 @@ class IntegerOverflowFault : public AlphaFault
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FaultStat & stat() {return _stat;}
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FaultStat & stat() {return _stat;}
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};
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};
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//Fault * ListOfFaults[];
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//int NumFaults;
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#endif // __FAULTS_HH__
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#endif // __FAULTS_HH__
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@ -45,6 +45,7 @@
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#include "cpu/o3/alpha_cpu.hh"
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#include "cpu/o3/alpha_cpu.hh"
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using namespace std;
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using namespace std;
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using namespace TheISA;
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#define NOHASH
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#define NOHASH
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#ifndef NOHASH
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#ifndef NOHASH
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@ -325,7 +326,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
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break;
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break;
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default:
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default:
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fault = MachineCheckFault;
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fault = genMachineCheckFault();
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break;
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break;
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}
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}
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@ -182,7 +182,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
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}
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}
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break;
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break;
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default:
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default:
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return new MachineCheckFault;
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return genMachineCheckFault();
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}
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}
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return NoFault;
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return NoFault;
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@ -202,7 +202,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
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val = *(uint64_t *)data;
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val = *(uint64_t *)data;
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break;
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break;
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default:
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default:
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return new MachineCheckFault;
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return genMachineCheckFault();
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}
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}
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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@ -260,6 +260,7 @@ class PciDev : public DmaDevice
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inline Fault
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inline Fault
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PciDev::readBar(MemReqPtr &req, uint8_t *data)
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PciDev::readBar(MemReqPtr &req, uint8_t *data)
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{
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{
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using namespace TheISA;
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if (isBAR(req->paddr, 0))
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if (isBAR(req->paddr, 0))
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return readBar0(req, req->paddr - BARAddrs[0], data);
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return readBar0(req, req->paddr - BARAddrs[0], data);
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if (isBAR(req->paddr, 1))
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if (isBAR(req->paddr, 1))
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@ -272,12 +273,13 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
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return readBar4(req, req->paddr - BARAddrs[4], data);
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return readBar4(req, req->paddr - BARAddrs[4], data);
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if (isBAR(req->paddr, 5))
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if (isBAR(req->paddr, 5))
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return readBar5(req, req->paddr - BARAddrs[5], data);
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return readBar5(req, req->paddr - BARAddrs[5], data);
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return new MachineCheckFault;
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return genMachineCheckFault();
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}
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}
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inline Fault
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inline Fault
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PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
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PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
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{
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{
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using namespace TheISA;
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if (isBAR(req->paddr, 0))
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if (isBAR(req->paddr, 0))
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return writeBar0(req, req->paddr - BARAddrs[0], data);
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return writeBar0(req, req->paddr - BARAddrs[0], data);
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if (isBAR(req->paddr, 1))
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if (isBAR(req->paddr, 1))
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@ -290,7 +292,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
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return writeBar4(req, req->paddr - BARAddrs[4], data);
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return writeBar4(req, req->paddr - BARAddrs[4], data);
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if (isBAR(req->paddr, 5))
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if (isBAR(req->paddr, 5))
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return writeBar5(req, req->paddr - BARAddrs[5], data);
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return writeBar5(req, req->paddr - BARAddrs[5], data);
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return new MachineCheckFault;
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return genMachineCheckFault();
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}
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}
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#endif // __DEV_PCIDEV_HH__
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#endif // __DEV_PCIDEV_HH__
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@ -363,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data)
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assert(config.command & PCI_CMD_MSE);
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assert(config.command & PCI_CMD_MSE);
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Fault fault = readBar(req, data);
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Fault fault = readBar(req, data);
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if (fault->isA<MachineCheckFault>()) {
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if (fault->isMachineCheckFault()) {
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panic("address does not map to a BAR pa=%#x va=%#x size=%d",
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panic("address does not map to a BAR pa=%#x va=%#x size=%d",
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req->paddr, req->vaddr, req->size);
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req->paddr, req->vaddr, req->size);
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return new MachineCheckFault;
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return genMachineCheckFault();
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}
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}
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return fault;
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return fault;
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@ -459,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data)
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assert(config.command & PCI_CMD_MSE);
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assert(config.command & PCI_CMD_MSE);
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Fault fault = writeBar(req, data);
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Fault fault = writeBar(req, data);
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if (fault->isA<MachineCheckFault>()) {
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if (fault->isMachineCheckFault()) {
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panic("address does not map to a BAR pa=%#x va=%#x size=%d",
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panic("address does not map to a BAR pa=%#x va=%#x size=%d",
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req->paddr, req->vaddr, req->size);
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req->paddr, req->vaddr, req->size);
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return new MachineCheckFault;
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return genMachineCheckFault();
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}
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}
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return fault;
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return fault;
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