ARM: Make various bits of the FP control registers read only.
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2d08b8de91
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4398075254
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@ -295,10 +295,43 @@ namespace ArmISA
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case MISCREG_CSSELR:
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case MISCREG_CSSELR:
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warn("The csselr register isn't implemented.\n");
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warn("The csselr register isn't implemented.\n");
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break;
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break;
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case MISCREG_FPSCR:
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{
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const uint32_t ones = (uint32_t)(-1);
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FPSCR fpscrMask = 0;
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fpscrMask.ioc = ones;
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fpscrMask.dzc = ones;
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fpscrMask.ofc = ones;
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fpscrMask.ufc = ones;
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fpscrMask.ixc = ones;
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fpscrMask.idc = ones;
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fpscrMask.len = ones;
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fpscrMask.stride = ones;
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fpscrMask.rMode = ones;
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fpscrMask.fz = ones;
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fpscrMask.dn = ones;
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fpscrMask.ahp = ones;
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fpscrMask.qc = ones;
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fpscrMask.v = ones;
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fpscrMask.c = ones;
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fpscrMask.z = ones;
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fpscrMask.n = ones;
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newVal = (newVal & (uint32_t)fpscrMask) |
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(miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
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}
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break;
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case MISCREG_FPEXC:
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{
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const uint32_t fpexcMask = 0x60000000;
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newVal = (newVal & fpexcMask) |
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(miscRegs[MISCREG_FPEXC] & ~fpexcMask);
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}
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break;
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case MISCREG_TLBTR:
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case MISCREG_TLBTR:
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case MISCREG_MVFR0:
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case MISCREG_MVFR0:
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case MISCREG_MVFR1:
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case MISCREG_MVFR1:
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case MISCREG_MPIDR:
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case MISCREG_MPIDR:
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case MISCREG_FPSID:
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return;
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return;
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}
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}
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return setMiscRegNoEffect(misc_reg, newVal);
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return setMiscRegNoEffect(misc_reg, newVal);
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