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test: Update eio ref outputs due to recent changes

Browse source 
Actual stats updates covering period since original ref outputs
were clobbered.
This commit is contained in:
Steve Reinhardt 2012-07-23 00:39:12 -04:00
parent 882a4b65bd
commit 42596d27e9
13 changed files with 944 additions and 636 deletions
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13
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
View file

@ -16,7 +16,6 @@ load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
readfile=
symbolfile=
work_begin_ckpt_count=0
@ -39,6 +38,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
@ -85,19 +85,20 @@ output=cout
system=system
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false

1
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
View file

@ -1,3 +1,4 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything

6
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
View file

@ -1,8 +1,10 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 29 2012 00:47:21
gem5 started Feb 29 2012 00:51:57
gem5 compiled Jul 22 2012 20:21:46
gem5 started Jul 23 2012 00:28:55
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second

42
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
View file

@ -4,23 +4,35 @@ sim_seconds 0.000250 # Nu
sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3174528 # Simulator instruction rate (inst/s)
host_op_rate 3174125 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1586983445 # Simulator tick rate (ticks/s)
host_mem_usage 203780 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
host_inst_rate 1870393 # Simulator instruction rate (inst/s)
host_op_rate 1870272 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 935134836 # Simulator tick rate (ticks/s)
host_mem_usage 212756 # Number of bytes of host memory used
host_seconds 0.27 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2872676 # Number of bytes read from this memory
system.physmem.bytes_inst_read 2000076 # Number of instructions bytes read from this memory
system.physmem.bytes_written 417562 # Number of bytes written to this memory
system.physmem.num_reads 624454 # Number of read requests responded to by this memory
system.physmem.num_writes 56340 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 11489991621 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 7999808012 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 1670144451 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 13160136072 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 2000076 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 872600 # Number of bytes read from this memory
system.physmem.bytes_read::total 2872676 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2000076 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2000076 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 417562 # Number of bytes written to this memory
system.physmem.bytes_written::total 417562 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 500019 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 124435 # Number of read requests responded to by this memory
system.physmem.num_reads::total 624454 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 56340 # Number of write requests responded to by this memory
system.physmem.num_writes::total 56340 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999808012 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3490183609 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11489991621 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999808012 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999808012 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1670144451 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1670144451 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv

23
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
View file

@ -16,7 +16,6 @@ load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
readfile=
symbolfile=
work_begin_ckpt_count=0
@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@ -88,7 +87,7 @@ size=64
[system.cpu.icache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@ -120,7 +119,7 @@ size=48
[system.cpu.l2cache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@ -144,13 +143,12 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -168,19 +166,20 @@ output=cout
system=system
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false

8
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 29 2012 00:47:21
gem5 started Feb 29 2012 00:51:57
gem5 compiled Jul 22 2012 20:21:46
gem5 started Jul 23 2012 00:28:55
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
49508 bytes wasted
>Exiting @ tick 727929000 because a thread reached the max instruction count
>Exiting @ tick 729729000 because a thread reached the max instruction count

129
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
View file

@ -1,25 +1,32 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000728 # Number of seconds simulated
sim_ticks 727929000 # Number of ticks simulated
final_tick 727929000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.000730 # Number of seconds simulated
sim_ticks 729729000 # Number of ticks simulated
final_tick 729729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1742138 # Simulator instruction rate (inst/s)
host_op_rate 1742023 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2535976572 # Simulator tick rate (ticks/s)
host_mem_usage 212652 # Number of bytes of host memory used
host_seconds 0.29 # Real time elapsed on the host
host_inst_rate 1176795 # Simulator instruction rate (inst/s)
host_op_rate 1176746 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1717342738 # Simulator tick rate (ticks/s)
host_mem_usage 221204 # Number of bytes of host memory used
host_seconds 0.43 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 54848 # Number of bytes read from this memory
system.physmem.bytes_inst_read 25792 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 857 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 75348008 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 35432027 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 75348008 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 29056 # Number of bytes read from this memory
system.physmem.bytes_read::total 54848 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25792 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 857 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 35344628 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39817521 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 75162149 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 35344628 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 35344628 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 35344628 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 39817521 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 75162149 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -53,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 1455858 # number of cpu cycles simulated
system.cpu.numCycles 1459458 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 500001 # Number of instructions committed
@ -72,18 +79,18 @@ system.cpu.num_mem_refs 180793 # nu
system.cpu.num_load_insts 124443 # Number of load instructions
system.cpu.num_store_insts 56350 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1455858 # Number of busy cycles
system.cpu.num_busy_cycles 1459458 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 264.952126 # Cycle average of tags in use
system.cpu.icache.tagsinuse 264.795716 # Cycle average of tags in use
system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 264.952126 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.129371 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.129371 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 264.795716 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.129295 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.129295 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
@ -109,17 +116,23 @@ system.cpu.icache.demand_accesses::total 500020 # nu
system.cpu.icache.overall_accesses::cpu.inst 500020 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000806 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000806 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
@ -135,21 +148,27 @@ system.cpu.icache.demand_mshr_miss_latency::total 21359000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21359000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 21359000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 287.175167 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 286.968386 # Cycle average of tags in use
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 287.175167 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.070111 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.070111 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 286.968386 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.070061 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.070061 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
@ -183,19 +202,27 @@ system.cpu.dcache.demand_accesses::total 180775 # nu
system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
@ -215,25 +242,33 @@ system.cpu.dcache.demand_mshr_miss_latency::total 24062000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 481.419470 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 481.117902 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 264.958770 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 216.460700 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.008086 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.006606 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.014692 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::cpu.inst 264.802343 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 216.315558 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.008081 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.006601 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.014683 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses
@ -269,24 +304,32 @@ system.cpu.l2cache.overall_accesses::cpu.data 454
system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
@ -313,18 +356,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18160000
system.cpu.l2cache.overall_mshr_miss_latency::total 34280000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

39
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
View file

@ -16,7 +16,6 @@ load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
readfile=
symbolfile=
work_begin_ckpt_count=0
@ -39,6 +38,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
@ -62,7 +62,7 @@ icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@ -91,7 +91,7 @@ size=64
[system.cpu0.icache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@ -145,6 +145,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
@ -168,7 +169,7 @@ icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@ -197,7 +198,7 @@ size=64
[system.cpu1.icache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@ -251,6 +252,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu2.interrupts
@ -274,7 +276,7 @@ icache_port=system.cpu2.icache.cpu_side
[system.cpu2.dcache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@ -303,7 +305,7 @@ size=64
[system.cpu2.icache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@ -357,6 +359,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu3.interrupts
@ -380,7 +383,7 @@ icache_port=system.cpu3.icache.cpu_side
[system.cpu3.dcache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@ -409,7 +412,7 @@ size=64
[system.cpu3.icache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@ -454,7 +457,7 @@ system=system
[system.l2c]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
forward_snoops=true
@ -478,19 +481,20 @@ cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[0]
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
width=8
master=system.physmem.port
slave=system.l2c.mem_side system.system_port
[system.physmem]
type=PhysicalMemory
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
@ -499,13 +503,12 @@ zero=false
port=system.membus.master[0]
[system.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side

6
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
View file

@ -1,8 +1,10 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 29 2012 00:47:21
gem5 started Feb 29 2012 00:51:57
gem5 compiled Jul 22 2012 20:21:46
gem5 started Jul 23 2012 00:28:55
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second

133
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
View file

@ -4,22 +4,59 @@ sim_seconds 0.000250 # Nu
sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3384594 # Simulator instruction rate (inst/s)
host_op_rate 3384489 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 423074550 # Simulator tick rate (ticks/s)
host_mem_usage 1140672 # Number of bytes of host memory used
host_seconds 0.59 # Real time elapsed on the host
host_inst_rate 2922206 # Simulator instruction rate (inst/s)
host_op_rate 2922133 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 365280152 # Simulator tick rate (ticks/s)
host_mem_usage 1149344 # Number of bytes of host memory used
host_seconds 0.68 # Real time elapsed on the host
sim_insts 2000004 # Number of instructions simulated
sim_ops 2000004 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 219392 # Number of bytes read from this memory
system.physmem.bytes_inst_read 103168 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 3428 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 877513594 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 412646416 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 877513594 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory
system.physmem.bytes_read::total 219392 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst 103161604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 116216795 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 103161604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 116216795 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 103161604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 116216795 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 103161604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 116216795 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 877513594 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 412646416 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 116216795 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 116216795 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 116216795 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
@ -103,14 +140,17 @@ system.cpu0.icache.demand_accesses::total 500019 # n
system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
@ -148,15 +188,19 @@ system.cpu0.dcache.demand_accesses::total 180775 # n
system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
@ -245,14 +289,17 @@ system.cpu1.icache.demand_accesses::total 500019 # n
system.cpu1.icache.overall_accesses::cpu1.inst 500019 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
@ -290,15 +337,19 @@ system.cpu1.dcache.demand_accesses::total 180775 # n
system.cpu1.dcache.overall_accesses::cpu1.data 180775 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
@ -387,14 +438,17 @@ system.cpu2.icache.demand_accesses::total 500019 # n
system.cpu2.icache.overall_accesses::cpu2.inst 500019 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
@ -432,15 +486,19 @@ system.cpu2.dcache.demand_accesses::total 180775 # n
system.cpu2.dcache.overall_accesses::cpu2.data 180775 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
@ -529,14 +587,17 @@ system.cpu3.icache.demand_accesses::total 500019 # n
system.cpu3.icache.overall_accesses::cpu3.inst 500019 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
@ -574,15 +635,19 @@ system.cpu3.dcache.demand_accesses::total 180775 # n
system.cpu3.dcache.overall_accesses::cpu3.data 180775 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
@ -716,10 +781,12 @@ system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # mi
system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
@ -728,6 +795,7 @@ system.l2c.demand_miss_rate::cpu2.inst 0.870410 # mi
system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
@ -736,12 +804,13 @@ system.l2c.overall_miss_rate::cpu2.inst 0.870410 # mi
system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate

35
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
View file

@ -16,7 +16,6 @@ load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
readfile=
symbolfile=
work_begin_ckpt_count=0
@ -59,7 +58,7 @@ icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@ -88,7 +87,7 @@ size=64
[system.cpu0.icache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@ -162,7 +161,7 @@ icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@ -191,7 +190,7 @@ size=64
[system.cpu1.icache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@ -265,7 +264,7 @@ icache_port=system.cpu2.icache.cpu_side
[system.cpu2.dcache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@ -294,7 +293,7 @@ size=64
[system.cpu2.icache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@ -368,7 +367,7 @@ icache_port=system.cpu3.icache.cpu_side
[system.cpu3.dcache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@ -397,7 +396,7 @@ size=64
[system.cpu3.icache]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@ -442,7 +441,7 @@ system=system
[system.l2c]
type=BaseCache
addr_range=0:18446744073709551615
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
forward_snoops=true
@ -466,19 +465,20 @@ cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[0]
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
width=8
master=system.physmem.port
slave=system.l2c.mem_side system.system_port
[system.physmem]
type=PhysicalMemory
type=SimpleMemory
conf_table_reported=false
file=
in_addr_map=true
latency=30000
latency_var=0
null=false
@ -487,13 +487,12 @@ zero=false
port=system.membus.master[0]
[system.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side

8
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
View file

@ -1,8 +1,10 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 29 2012 00:47:21
gem5 started Feb 29 2012 00:51:57
gem5 compiled Jul 22 2012 20:21:46
gem5 started Jul 23 2012 00:28:55
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
@ -15,4 +17,4 @@ main dictionary has 1245 entries
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
>>>>Exiting @ tick 728920000 because a thread reached the max instruction count
>>>>Exiting @ tick 731328000 because a thread reached the max instruction count

1137
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
View file

File diff suppressed because it is too large Load diff