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X86: Optomize the bit scanning instruction microassembly a little. More can be done.

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--HG--
extra : convert_revision : 3cf6e972f0e41e3529a633ecbb31289e1bd17f0f
This commit is contained in:
Gabe Black 2008-01-23 08:18:27 -05:00
parent 60c2d98fc0
commit 423bbe6499
1 changed files with 87 additions and 126 deletions
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213
src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
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@ -84,6 +84,7 @@
microcode = ''' microcode = '''
def macroop BSF_R_R { def macroop BSF_R_R {
# Determine if the input was zero, and also move it to a temp reg. # Determine if the input was zero, and also move it to a temp reg.
movi t1, t1, t0, dataSize=8
and t1, regm, regm, flags=(ZF,) and t1, regm, regm, flags=(ZF,)
bri t0, label("end"), flags=(CZF,) bri t0, label("end"), flags=(CZF,)
@ -91,43 +92,37 @@ def macroop BSF_R_R {
movi reg, reg, 0x0 movi reg, reg, 0x0
# Bit 6 # Bit 6
limm t2, 0xFFFFFFFF00000000 srli t3, t1, 32, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x20 ori t4, reg, 0x20
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 5 # Bit 5
limm t2, 0xFFFF0000FFFF0000 srli t3, t1, 16, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x10 ori t4, reg, 0x10
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 4 # Bit 4
limm t2, 0xFF00FF00FF00FF00 srli t3, t1, 8, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x8 ori t4, reg, 0x8
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 3 # Bit 3
limm t2, 0xF0F0F0F0F0F0F0F0 srli t3, t1, 4, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x4 ori t4, reg, 0x4
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 2 # Bit 2
limm t2, 0xCCCCCCCCCCCCCCCC srli t3, t1, 2, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x2 ori t4, reg, 0x2
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 1 # Bit 1
limm t2, 0xAAAAAAAAAAAAAAAA srli t3, t1, 1, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x1 ori t4, reg, 0x1
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
@ -138,6 +133,7 @@ end:
def macroop BSF_R_M { def macroop BSF_R_M {
movi t1, t1, t0, dataSize=8
ld t1, seg, sib, disp ld t1, seg, sib, disp
# Determine if the input was zero, and also move it to a temp reg. # Determine if the input was zero, and also move it to a temp reg.
@ -148,43 +144,37 @@ def macroop BSF_R_M {
movi reg, reg, 0x0 movi reg, reg, 0x0
# Bit 6 # Bit 6
limm t2, 0xFFFFFFFF00000000 srli t3, t1, 32, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x20 ori t4, reg, 0x20
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 5 # Bit 5
limm t2, 0xFFFF0000FFFF0000 srli t3, t1, 16, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x10 ori t4, reg, 0x10
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 4 # Bit 4
limm t2, 0xFF00FF00FF00FF00 srli t3, t1, 8, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x8 ori t4, reg, 0x8
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 3 # Bit 3
limm t2, 0xF0F0F0F0F0F0F0F0 srli t3, t1, 4, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x4 ori t4, reg, 0x4
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 2 # Bit 2
limm t2, 0xCCCCCCCCCCCCCCCC srli t3, t1, 2, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x2 ori t4, reg, 0x2
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 1 # Bit 1
limm t2, 0xAAAAAAAAAAAAAAAA srli t3, t1, 1, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x1 ori t4, reg, 0x1
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
@ -196,6 +186,7 @@ end:
def macroop BSF_R_P { def macroop BSF_R_P {
rdip t7 rdip t7
movi t1, t1, t0, dataSize=8
ld t1, seg, riprel, disp ld t1, seg, riprel, disp
# Determine if the input was zero, and also move it to a temp reg. # Determine if the input was zero, and also move it to a temp reg.
@ -206,43 +197,37 @@ def macroop BSF_R_P {
movi reg, reg, 0x0 movi reg, reg, 0x0
# Bit 6 # Bit 6
limm t2, 0xFFFFFFFF00000000 srli t3, t1, 32, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x20 ori t4, reg, 0x20
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 5 # Bit 5
limm t2, 0xFFFF0000FFFF0000 srli t3, t1, 16, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x10 ori t4, reg, 0x10
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 4 # Bit 4
limm t2, 0xFF00FF00FF00FF00 srli t3, t1, 8, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x8 ori t4, reg, 0x8
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 3 # Bit 3
limm t2, 0xF0F0F0F0F0F0F0F0 srli t3, t1, 4, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x4 ori t4, reg, 0x4
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 2 # Bit 2
limm t2, 0xCCCCCCCCCCCCCCCC srli t3, t1, 2, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x2 ori t4, reg, 0x2
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
# Bit 1 # Bit 1
limm t2, 0xAAAAAAAAAAAAAAAA srli t3, t1, 1, dataSize=8, flags=(EZF,)
and t3, t2, t1, flags=(EZF,)
ori t4, reg, 0x1 ori t4, reg, 0x1
mov reg, reg, t4, flags=(nCEZF,) mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,) mov t1, t1, t3, flags=(nCEZF,)
@ -253,53 +238,45 @@ end:
def macroop BSR_R_R { def macroop BSR_R_R {
# Determine if the input was zero, and also move it to a temp reg. # Determine if the input was zero, and also move it to a temp reg.
mov t1, t1, t0, dataSize=8
and t1, regm, regm, flags=(ZF,) and t1, regm, regm, flags=(ZF,)
bri t0, label("end"), flags=(CZF,) bri t0, label("end"), flags=(CZF,)
# Zero out the result register # Zero out the result register
movi reg, reg, 0 movi reg, reg, 0
subi t2, t1, 1
xor t1, t2, t1
# Bit 6 # Bit 6
limm t2, 0x00000000FFFFFFFF srli t3, t1, 32, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 32
ori t4, reg, 0x20 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 5 # Bit 5
limm t2, 0x0000FFFF0000FFFF srli t3, t1, 16, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 16
ori t4, reg, 0x10 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 4 # Bit 4
limm t2, 0x00FF00FF00FF00FF srli t3, t1, 8, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 8
ori t4, reg, 0x8 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 3 # Bit 3
limm t2, 0x0F0F0F0F0F0F0F0F srli t3, t1, 4, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 4
ori t4, reg, 0x4 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 2 # Bit 2
limm t2, 0x3333333333333333 srli t3, t1, 2, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 2
ori t4, reg, 0x2 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 1 # Bit 1
limm t2, 0x5555555555555555 srli t3, t1, 1, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 1
ori t4, reg, 0x1 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
end: end:
fault "NoFault" fault "NoFault"
@ -307,6 +284,7 @@ end:
def macroop BSR_R_M { def macroop BSR_R_M {
mov t1, t1, t0, dataSize=8
ld t1, seg, sib, disp ld t1, seg, sib, disp
# Determine if the input was zero, and also move it to a temp reg. # Determine if the input was zero, and also move it to a temp reg.
@ -316,47 +294,38 @@ def macroop BSR_R_M {
# Zero out the result register # Zero out the result register
mov reg, reg, t0 mov reg, reg, t0
subi t2, t1, 1
xor t1, t2, t1
# Bit 6 # Bit 6
limm t2, 0x00000000FFFFFFFF srli t3, t1, 32, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 32
ori t4, reg, 0x20 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 5 # Bit 5
limm t2, 0x0000FFFF0000FFFF srli t3, t1, 16, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 16
ori t4, reg, 0x10 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 4 # Bit 4
limm t2, 0x00FF00FF00FF00FF srli t3, t1, 8, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 8
ori t4, reg, 0x8 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 3 # Bit 3
limm t2, 0x0F0F0F0F0F0F0F0F srli t3, t1, 4, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 4
ori t4, reg, 0x4 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 2 # Bit 2
limm t2, 0x3333333333333333 srli t3, t1, 2, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 2
ori t4, reg, 0x2 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 1 # Bit 1
limm t2, 0x5555555555555555 srli t3, t1, 1, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 1
ori t4, reg, 0x1 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
end: end:
fault "NoFault" fault "NoFault"
@ -365,6 +334,7 @@ end:
def macroop BSR_R_P { def macroop BSR_R_P {
rdip t7 rdip t7
mov t1, t1, t0, dataSize=8
ld t1, seg, riprel, disp ld t1, seg, riprel, disp
# Determine if the input was zero, and also move it to a temp reg. # Determine if the input was zero, and also move it to a temp reg.
@ -374,47 +344,38 @@ def macroop BSR_R_P {
# Zero out the result register # Zero out the result register
mov reg, reg, t0 mov reg, reg, t0
subi t2, t1, 1
xor t1, t2, t1
# Bit 6 # Bit 6
limm t2, 0x00000000FFFFFFFF srli t3, t1, 32, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 32
ori t4, reg, 0x20 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 5 # Bit 5
limm t2, 0x0000FFFF0000FFFF srli t3, t1, 16, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 16
ori t4, reg, 0x10 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 4 # Bit 4
limm t2, 0x00FF00FF00FF00FF srli t3, t1, 8, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 8
ori t4, reg, 0x8 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 3 # Bit 3
limm t2, 0x0F0F0F0F0F0F0F0F srli t3, t1, 4, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 4
ori t4, reg, 0x4 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 2 # Bit 2
limm t2, 0x3333333333333333 srli t3, t1, 2, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 2
ori t4, reg, 0x2 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 1 # Bit 1
limm t2, 0x5555555555555555 srli t3, t1, 1, dataSize=8
and t3, t2, t1, flags=(EZF,) andi t3, t3, 1
ori t4, reg, 0x1 or reg, reg, t3
mov reg, reg, t4, flags=(CEZF,)
mov t1, t1, t3, flags=(nCEZF,)
end: end:
fault "NoFault" fault "NoFault"