Fix some unset values in the request in the timing CPU.
Properly implement the MSHR allocate function. src/cpu/simple/timing.cc: Set the thread context in the CPU. Need to do this properly, currently I just set it to Cpu=0 Thread=0. This will just cause all the stats in the cache based on these to just yield totals and not a distribution. src/mem/cache/miss/mshr.cc: Properly implement the allocate function for the MSHR. --HG-- extra : convert_revision : bcece518e54ed1404db3196f996a77b4dd5c1c1e
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f4c5609988
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4201ec84b2
2 changed files with 21 additions and 19 deletions
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@ -207,7 +207,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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{
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// need to fill in CPU & thread IDs here
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// need to fill in CPU & thread IDs here
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Request *data_read_req = new Request();
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Request *data_read_req = new Request();
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data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
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data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
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data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
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if (traceData) {
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if (traceData) {
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@ -288,6 +288,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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{
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// need to fill in CPU & thread IDs here
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// need to fill in CPU & thread IDs here
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Request *data_write_req = new Request();
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Request *data_write_req = new Request();
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data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
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data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
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data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
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// translate to physical address
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// translate to physical address
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@ -371,6 +372,7 @@ TimingSimpleCPU::fetch()
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// need to fill in CPU & thread IDs here
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// need to fill in CPU & thread IDs here
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Request *ifetch_req = new Request();
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Request *ifetch_req = new Request();
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ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
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Fault fault = setupFetchRequest(ifetch_req);
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Fault fault = setupFetchRequest(ifetch_req);
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ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
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ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
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34
src/mem/cache/miss/mshr.cc
vendored
34
src/mem/cache/miss/mshr.cc
vendored
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@ -57,26 +57,26 @@ void
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MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
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MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
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Packet * &target)
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Packet * &target)
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{
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{
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assert("NEED TO FIX YET\n" && 0);
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if (target)
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#if 0
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{
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assert(targets.empty());
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//Have a request, just use it
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addr = _addr;
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pkt = new Packet(target->req, cmd, Packet::Broadcast, size);
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asid = _asid;
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pkt = new Packet(); // allocate new memory request
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pkt->addr = addr; //picked physical address for now
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pkt->cmd = cmd;
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pkt->size = size;
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pkt->data = new uint8_t[size];
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pkt->senderState = this;
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//Set the time here for latency calculations
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pkt->time = curTick;
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pkt->time = curTick;
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pkt->allocate();
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if (target) {
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pkt->senderState = (Packet::SenderState *)this;
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pkt->req = target->req;
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allocateTarget(target);
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allocateTarget(target);
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}
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}
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#endif
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else
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{
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//need a request first
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Request * req = new Request();
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req->setPhys(addr, size, 0);
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//Thread context??
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pkt = new Packet(req, cmd, Packet::Broadcast, size);
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pkt->time = curTick;
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pkt->allocate();
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pkt->senderState = (Packet::SenderState *)this;
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}
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}
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}
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// Since we aren't sure if data is being used, don't copy here.
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// Since we aren't sure if data is being used, don't copy here.
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