arch: Pass faults by const reference where possible
This patch changes how faults are passed between methods in an attempt to copy as few reference-counting pointer instances as possible. This should avoid unecessary copies being created, contributing to the increment/decrement of the reference counters.
This commit is contained in:
parent
619c5519fe
commit
41fc8a573e
36 changed files with 71 additions and 69 deletions
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@ -171,7 +171,7 @@ Stage2LookUp::mergeTe(RequestPtr req, BaseTLB::Mode mode)
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}
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}
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void
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void
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Stage2LookUp::finish(Fault _fault, RequestPtr req,
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Stage2LookUp::finish(const Fault &_fault, RequestPtr req,
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ThreadContext *tc, BaseTLB::Mode mode)
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ThreadContext *tc, BaseTLB::Mode mode)
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{
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{
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fault = _fault;
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fault = _fault;
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@ -97,7 +97,7 @@ class Stage2LookUp : public BaseTLB::Translation
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void markDelayed() {}
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void markDelayed() {}
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void finish(Fault fault, RequestPtr req, ThreadContext *tc,
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void finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
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BaseTLB::Mode mode);
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BaseTLB::Mode mode);
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};
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};
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@ -114,8 +114,8 @@ Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent,
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}
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}
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void
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void
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Stage2MMU::Stage2Translation::finish(Fault _fault, RequestPtr req, ThreadContext *tc,
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Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req,
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BaseTLB::Mode mode)
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ThreadContext *tc, BaseTLB::Mode mode)
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{
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{
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fault = _fault;
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fault = _fault;
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@ -78,7 +78,7 @@ class Stage2MMU : public SimObject
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markDelayed() {}
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markDelayed() {}
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void
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void
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finish(Fault fault, RequestPtr req, ThreadContext *tc,
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finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
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BaseTLB::Mode mode);
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BaseTLB::Mode mode);
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void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
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void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
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@ -426,7 +426,7 @@ class Checker : public CheckerCPU
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void switchOut();
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void switchOut();
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void takeOverFrom(BaseCPU *oldCPU);
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void takeOverFrom(BaseCPU *oldCPU);
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void advancePC(Fault fault);
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void advancePC(const Fault &fault);
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void verify(DynInstPtr &inst);
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void verify(DynInstPtr &inst);
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@ -69,7 +69,7 @@ using namespace TheISA;
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template <class Impl>
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template <class Impl>
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void
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void
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Checker<Impl>::advancePC(Fault fault)
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Checker<Impl>::advancePC(const Fault &fault)
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{
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{
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if (fault != NoFault) {
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if (fault != NoFault) {
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curMacroStaticInst = StaticInst::nullStaticInstPtr;
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curMacroStaticInst = StaticInst::nullStaticInstPtr;
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@ -128,8 +128,8 @@ InOrderCPU::TickEvent::description() const
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}
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}
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InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
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InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
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Fault fault, ThreadID _tid, DynInstPtr inst,
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const Fault &fault, ThreadID _tid,
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CPUEventPri event_pri)
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DynInstPtr inst, CPUEventPri event_pri)
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: Event(event_pri), cpu(_cpu)
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: Event(event_pri), cpu(_cpu)
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{
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{
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setEvent(e_type, fault, _tid, inst);
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setEvent(e_type, fault, _tid, inst);
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@ -910,7 +910,7 @@ InOrderCPU::getInterrupts()
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}
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}
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void
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void
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InOrderCPU::processInterrupts(Fault interrupt)
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InOrderCPU::processInterrupts(const Fault &interrupt)
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{
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{
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// Check for interrupts here. For now can copy the code that
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// Check for interrupts here. For now can copy the code that
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// exists within isa_fullsys_traits.hh. Also assume that thread 0
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// exists within isa_fullsys_traits.hh. Also assume that thread 0
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@ -928,7 +928,7 @@ InOrderCPU::processInterrupts(Fault interrupt)
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}
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}
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void
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void
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InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
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InOrderCPU::trapContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
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Cycles delay)
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Cycles delay)
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{
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{
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scheduleCpuEvent(Trap, fault, tid, inst, delay);
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scheduleCpuEvent(Trap, fault, tid, inst, delay);
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@ -936,7 +936,7 @@ InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
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}
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}
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void
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void
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InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
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InOrderCPU::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
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{
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{
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fault->invoke(tcBase(tid), inst->staticInst);
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fault->invoke(tcBase(tid), inst->staticInst);
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removePipelineStalls(tid);
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removePipelineStalls(tid);
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@ -970,7 +970,7 @@ InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
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}
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}
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void
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void
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InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
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InOrderCPU::scheduleCpuEvent(CPUEventType c_event, const Fault &fault,
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ThreadID tid, DynInstPtr inst,
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ThreadID tid, DynInstPtr inst,
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Cycles delay, CPUEventPri event_pri)
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Cycles delay, CPUEventPri event_pri)
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{
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{
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@ -1847,7 +1847,7 @@ InOrderCPU::wakeup()
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}
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}
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void
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void
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InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
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InOrderCPU::syscallContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
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Cycles delay)
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Cycles delay)
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{
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{
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// Syscall must be non-speculative, so squash from last stage
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// Syscall must be non-speculative, so squash from last stage
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@ -263,11 +263,11 @@ class InOrderCPU : public BaseCPU
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public:
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public:
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/** Constructs a CPU event. */
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/** Constructs a CPU event. */
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CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
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CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, const Fault &fault,
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ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
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ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
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/** Set Type of Event To Be Scheduled */
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/** Set Type of Event To Be Scheduled */
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void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
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void setEvent(CPUEventType e_type, const Fault &_fault, ThreadID _tid,
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DynInstPtr _inst)
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DynInstPtr _inst)
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{
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{
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fault = _fault;
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fault = _fault;
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@ -291,7 +291,8 @@ class InOrderCPU : public BaseCPU
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};
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};
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/** Schedule a CPU Event */
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/** Schedule a CPU Event */
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void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
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void scheduleCpuEvent(CPUEventType cpu_event, const Fault &fault,
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ThreadID tid,
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DynInstPtr inst, Cycles delay = Cycles(0),
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DynInstPtr inst, Cycles delay = Cycles(0),
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CPUEventPri event_pri = InOrderCPU_Pri);
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CPUEventPri event_pri = InOrderCPU_Pri);
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@ -471,7 +472,7 @@ class InOrderCPU : public BaseCPU
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Fault getInterrupts();
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Fault getInterrupts();
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/** Processes any an interrupt fault. */
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/** Processes any an interrupt fault. */
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void processInterrupts(Fault interrupt);
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void processInterrupts(const Fault &interrupt);
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/** Halts the CPU. */
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/** Halts the CPU. */
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void halt() { panic("Halt not implemented!\n"); }
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void halt() { panic("Halt not implemented!\n"); }
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@ -483,18 +484,18 @@ class InOrderCPU : public BaseCPU
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bool validDataAddr(Addr addr) { return true; }
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bool validDataAddr(Addr addr) { return true; }
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/** Schedule a syscall on the CPU */
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/** Schedule a syscall on the CPU */
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void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
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void syscallContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
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Cycles delay = Cycles(0));
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Cycles delay = Cycles(0));
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/** Executes a syscall.*/
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/** Executes a syscall.*/
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void syscall(int64_t callnum, ThreadID tid);
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void syscall(int64_t callnum, ThreadID tid);
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/** Schedule a trap on the CPU */
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/** Schedule a trap on the CPU */
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void trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
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void trapContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
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Cycles delay = Cycles(0));
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Cycles delay = Cycles(0));
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/** Perform trap to Handle Given Fault */
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/** Perform trap to Handle Given Fault */
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void trap(Fault fault, ThreadID tid, DynInstPtr inst);
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void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
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/** Schedule thread activation on the CPU */
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/** Schedule thread activation on the CPU */
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void activateContext(ThreadID tid, Cycles delay = Cycles(0));
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void activateContext(ThreadID tid, Cycles delay = Cycles(0));
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@ -298,7 +298,7 @@ InOrderDynInst::hwrei()
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void
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void
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InOrderDynInst::trap(Fault fault)
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InOrderDynInst::trap(const Fault &fault)
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{
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{
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this->cpu->trap(fault, this->threadNumber, this);
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this->cpu->trap(fault, this->threadNumber, this);
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}
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}
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@ -524,7 +524,7 @@ class InOrderDynInst : public ExecContext, public RefCounted
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/** Calls hardware return from error interrupt. */
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/** Calls hardware return from error interrupt. */
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Fault hwrei();
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Fault hwrei();
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/** Traps to handle specified fault. */
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/** Traps to handle specified fault. */
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void trap(Fault fault);
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void trap(const Fault &fault);
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bool simPalCheck(int palFunc);
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bool simPalCheck(int palFunc);
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short syscallNum;
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short syscallNum;
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@ -104,7 +104,7 @@ class Resource {
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virtual void instGraduated(InstSeqNum seq_num, ThreadID tid) { }
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virtual void instGraduated(InstSeqNum seq_num, ThreadID tid) { }
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/** Post-processsing for Trap Generated from this instruction */
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/** Post-processsing for Trap Generated from this instruction */
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virtual void trap(Fault fault, ThreadID tid, DynInstPtr inst) { }
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virtual void trap(const Fault &fault, ThreadID tid, DynInstPtr inst) { }
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/** Request usage of this resource. Returns a ResourceRequest object
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/** Request usage of this resource. Returns a ResourceRequest object
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* with all the necessary resource information
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* with all the necessary resource information
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@ -206,7 +206,7 @@ ResourcePool::squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
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}
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}
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void
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void
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ResourcePool::trap(Fault fault, ThreadID tid, DynInstPtr inst)
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ResourcePool::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
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{
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{
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DPRINTF(Resource, "[tid:%i] Broadcasting Trap to all "
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DPRINTF(Resource, "[tid:%i] Broadcasting Trap to all "
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"resources.\n", tid);
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"resources.\n", tid);
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@ -193,7 +193,7 @@ class ResourcePool {
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void instGraduated(InstSeqNum seq_num, ThreadID tid);
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void instGraduated(InstSeqNum seq_num, ThreadID tid);
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/** Broadcast trap to all resources */
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/** Broadcast trap to all resources */
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void trap(Fault fault, ThreadID tid, DynInstPtr inst);
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void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
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/** The number of instructions available that a resource can
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/** The number of instructions available that a resource can
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* can still process.
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* can still process.
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@ -405,7 +405,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
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}
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}
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void
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void
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CacheUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
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CacheUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
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{
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{
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tlbBlocked[tid] = false;
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tlbBlocked[tid] = false;
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}
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}
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@ -113,7 +113,7 @@ class CacheUnit : public Resource
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bool processSquash(CacheReqPacket *cache_pkt);
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bool processSquash(CacheReqPacket *cache_pkt);
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void trap(Fault fault, ThreadID tid, DynInstPtr inst);
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void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
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void recvRetry();
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void recvRetry();
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@ -304,7 +304,7 @@ FetchSeqUnit::suspendThread(ThreadID tid)
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}
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}
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void
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void
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FetchSeqUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
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FetchSeqUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
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{
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{
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pcValid[tid] = true;
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pcValid[tid] = true;
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pc[tid] = cpu->pcState(tid);
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pc[tid] = cpu->pcState(tid);
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InstSeqNum squash_seq_num, ThreadID tid);
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InstSeqNum squash_seq_num, ThreadID tid);
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/** Update to correct PC from a trap */
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/** Update to correct PC from a trap */
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void trap(Fault fault, ThreadID tid, DynInstPtr inst);
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void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
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protected:
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protected:
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unsigned instSize;
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unsigned instSize;
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@ -574,7 +574,7 @@ FetchUnit::squashCacheRequest(CacheReqPtr req_ptr)
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}
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}
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void
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void
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FetchUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
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FetchUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
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{
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{
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//@todo: per thread?
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//@todo: per thread?
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decoder[tid]->reset();
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decoder[tid]->reset();
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/** Executes one of the commands from the "Command" enum */
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/** Executes one of the commands from the "Command" enum */
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void execute(int slot_num);
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void execute(int slot_num);
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void trap(Fault fault, ThreadID tid, DynInstPtr inst);
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void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
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TheISA::Decoder *decoder[ThePipeline::MaxThreads];
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TheISA::Decoder *decoder[ThePipeline::MaxThreads];
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@ -204,8 +204,8 @@ Fetch1::FetchRequest::makePacket()
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}
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}
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void
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void
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Fetch1::FetchRequest::finish(
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Fetch1::FetchRequest::finish(const Fault &fault_, RequestPtr request_,
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Fault fault_, RequestPtr request_, ThreadContext *tc, BaseTLB::Mode mode)
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ThreadContext *tc, BaseTLB::Mode mode)
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{
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{
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fault = fault_;
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fault = fault_;
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@ -163,8 +163,8 @@ class Fetch1 : public Named
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/** Interface for ITLB responses. Populates self and then passes
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/** Interface for ITLB responses. Populates self and then passes
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* the request on to the ports' handleTLBResponse member
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* the request on to the ports' handleTLBResponse member
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* function */
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* function */
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void finish(Fault fault_, RequestPtr request_, ThreadContext *tc,
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void finish(const Fault &fault_, RequestPtr request_,
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BaseTLB::Mode mode);
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ThreadContext *tc, BaseTLB::Mode mode);
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public:
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public:
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FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) :
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FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) :
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@ -226,8 +226,8 @@ LSQ::clearMemBarrier(MinorDynInstPtr inst)
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}
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}
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void
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void
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LSQ::SingleDataRequest::finish(Fault fault_, RequestPtr request_,
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LSQ::SingleDataRequest::finish(const Fault &fault_, RequestPtr request_,
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ThreadContext *tc, BaseTLB::Mode mode)
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ThreadContext *tc, BaseTLB::Mode mode)
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{
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{
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fault = fault_;
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fault = fault_;
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@ -273,8 +273,8 @@ LSQ::SingleDataRequest::retireResponse(PacketPtr packet_)
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}
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}
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void
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void
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LSQ::SplitDataRequest::finish(Fault fault_, RequestPtr request_,
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LSQ::SplitDataRequest::finish(const Fault &fault_, RequestPtr request_,
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ThreadContext *tc, BaseTLB::Mode mode)
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ThreadContext *tc, BaseTLB::Mode mode)
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{
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{
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fault = fault_;
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fault = fault_;
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@ -268,8 +268,8 @@ class LSQ : public Named
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{
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{
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protected:
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protected:
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/** TLB interace */
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/** TLB interace */
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void finish(Fault fault_, RequestPtr request_, ThreadContext *tc,
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void finish(const Fault &fault_, RequestPtr request_,
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BaseTLB::Mode mode)
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ThreadContext *tc, BaseTLB::Mode mode)
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{ }
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{ }
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public:
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public:
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@ -329,8 +329,8 @@ class LSQ : public Named
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{
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{
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protected:
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protected:
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/** TLB interace */
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/** TLB interace */
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void finish(Fault fault_, RequestPtr request_, ThreadContext *tc,
|
void finish(const Fault &fault_, RequestPtr request_,
|
||||||
BaseTLB::Mode mode);
|
ThreadContext *tc, BaseTLB::Mode mode);
|
||||||
|
|
||||||
/** Has my only packet been sent to the memory system but has not
|
/** Has my only packet been sent to the memory system but has not
|
||||||
* yet been responded to */
|
* yet been responded to */
|
||||||
|
@ -415,8 +415,8 @@ class LSQ : public Named
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
/** TLB response interface */
|
/** TLB response interface */
|
||||||
void finish(Fault fault_, RequestPtr request_, ThreadContext *tc,
|
void finish(const Fault &fault_, RequestPtr request_,
|
||||||
BaseTLB::Mode mode);
|
ThreadContext *tc, BaseTLB::Mode mode);
|
||||||
|
|
||||||
public:
|
public:
|
||||||
SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_,
|
SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_,
|
||||||
|
|
|
@ -1095,7 +1095,7 @@ FullO3CPU<Impl>::getInterrupts()
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullO3CPU<Impl>::processInterrupts(Fault interrupt)
|
FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
|
||||||
{
|
{
|
||||||
// Check for interrupts here. For now can copy the code that
|
// Check for interrupts here. For now can copy the code that
|
||||||
// exists within isa_fullsys_traits.hh. Also assume that thread 0
|
// exists within isa_fullsys_traits.hh. Also assume that thread 0
|
||||||
|
@ -1112,7 +1112,7 @@ FullO3CPU<Impl>::processInterrupts(Fault interrupt)
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
|
FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, StaticInstPtr inst)
|
||||||
{
|
{
|
||||||
// Pass the thread's TC into the invoke method.
|
// Pass the thread's TC into the invoke method.
|
||||||
fault->invoke(this->threadContexts[tid], inst);
|
fault->invoke(this->threadContexts[tid], inst);
|
||||||
|
|
|
@ -498,7 +498,7 @@ class FullO3CPU : public BaseO3CPU
|
||||||
{ return globalSeqNum++; }
|
{ return globalSeqNum++; }
|
||||||
|
|
||||||
/** Traps to handle given fault. */
|
/** Traps to handle given fault. */
|
||||||
void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
|
void trap(const Fault &fault, ThreadID tid, StaticInstPtr inst);
|
||||||
|
|
||||||
/** HW return from error interrupt. */
|
/** HW return from error interrupt. */
|
||||||
Fault hwrei(ThreadID tid);
|
Fault hwrei(ThreadID tid);
|
||||||
|
@ -509,7 +509,7 @@ class FullO3CPU : public BaseO3CPU
|
||||||
Fault getInterrupts();
|
Fault getInterrupts();
|
||||||
|
|
||||||
/** Processes any an interrupt fault. */
|
/** Processes any an interrupt fault. */
|
||||||
void processInterrupts(Fault interrupt);
|
void processInterrupts(const Fault &interrupt);
|
||||||
|
|
||||||
/** Halts the CPU. */
|
/** Halts the CPU. */
|
||||||
void halt() { panic("Halt not implemented!\n"); }
|
void halt() { panic("Halt not implemented!\n"); }
|
||||||
|
|
|
@ -230,7 +230,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
|
||||||
/** Calls hardware return from error interrupt. */
|
/** Calls hardware return from error interrupt. */
|
||||||
Fault hwrei();
|
Fault hwrei();
|
||||||
/** Traps to handle specified fault. */
|
/** Traps to handle specified fault. */
|
||||||
void trap(Fault fault);
|
void trap(const Fault &fault);
|
||||||
bool simPalCheck(int palFunc);
|
bool simPalCheck(int palFunc);
|
||||||
|
|
||||||
/** Emulates a syscall. */
|
/** Emulates a syscall. */
|
||||||
|
|
|
@ -225,7 +225,7 @@ BaseO3DynInst<Impl>::hwrei()
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
BaseO3DynInst<Impl>::trap(Fault fault)
|
BaseO3DynInst<Impl>::trap(const Fault &fault)
|
||||||
{
|
{
|
||||||
this->cpu->trap(fault, this->threadNumber, this->staticInst);
|
this->cpu->trap(fault, this->threadNumber, this->staticInst);
|
||||||
}
|
}
|
||||||
|
|
|
@ -100,7 +100,7 @@ class DefaultFetch
|
||||||
{}
|
{}
|
||||||
|
|
||||||
void
|
void
|
||||||
finish(Fault fault, RequestPtr req, ThreadContext *tc,
|
finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
|
||||||
BaseTLB::Mode mode)
|
BaseTLB::Mode mode)
|
||||||
{
|
{
|
||||||
assert(mode == BaseTLB::Execute);
|
assert(mode == BaseTLB::Execute);
|
||||||
|
@ -294,7 +294,7 @@ class DefaultFetch
|
||||||
* @return Any fault that occured.
|
* @return Any fault that occured.
|
||||||
*/
|
*/
|
||||||
bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
|
bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
|
||||||
void finishTranslation(Fault fault, RequestPtr mem_req);
|
void finishTranslation(const Fault &fault, RequestPtr mem_req);
|
||||||
|
|
||||||
|
|
||||||
/** Check if an interrupt is pending and that we need to handle
|
/** Check if an interrupt is pending and that we need to handle
|
||||||
|
|
|
@ -633,7 +633,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
|
DefaultFetch<Impl>::finishTranslation(const Fault &fault, RequestPtr mem_req)
|
||||||
{
|
{
|
||||||
ThreadID tid = mem_req->threadId();
|
ThreadID tid = mem_req->threadId();
|
||||||
Addr fetchBufferBlockPC = mem_req->getVaddr();
|
Addr fetchBufferBlockPC = mem_req->getVaddr();
|
||||||
|
|
|
@ -255,7 +255,7 @@ OzoneDynInst<Impl>::hwrei()
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
void
|
void
|
||||||
OzoneDynInst<Impl>::trap(Fault fault)
|
OzoneDynInst<Impl>::trap(const Fault &fault)
|
||||||
{
|
{
|
||||||
fault->invoke(this->thread->getTC());
|
fault->invoke(this->thread->getTC());
|
||||||
}
|
}
|
||||||
|
|
|
@ -555,7 +555,7 @@ BaseSimpleCPU::postExecute()
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
BaseSimpleCPU::advancePC(Fault fault)
|
BaseSimpleCPU::advancePC(const Fault &fault)
|
||||||
{
|
{
|
||||||
const bool branching(thread->pcState().branching());
|
const bool branching(thread->pcState().branching());
|
||||||
|
|
||||||
|
|
|
@ -168,7 +168,7 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
|
||||||
void setupFetchRequest(Request *req);
|
void setupFetchRequest(Request *req);
|
||||||
void preExecute();
|
void preExecute();
|
||||||
void postExecute();
|
void postExecute();
|
||||||
void advancePC(Fault fault);
|
void advancePC(const Fault &fault);
|
||||||
|
|
||||||
virtual void deallocateContext(ThreadID thread_num);
|
virtual void deallocateContext(ThreadID thread_num);
|
||||||
virtual void haltContext(ThreadID thread_num);
|
virtual void haltContext(ThreadID thread_num);
|
||||||
|
|
|
@ -328,7 +328,7 @@ TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
TimingSimpleCPU::translationFault(Fault fault)
|
TimingSimpleCPU::translationFault(const Fault &fault)
|
||||||
{
|
{
|
||||||
// fault may be NoFault in cases where a fault is suppressed,
|
// fault may be NoFault in cases where a fault is suppressed,
|
||||||
// for instance prefetches.
|
// for instance prefetches.
|
||||||
|
@ -576,7 +576,8 @@ TimingSimpleCPU::fetch()
|
||||||
|
|
||||||
|
|
||||||
void
|
void
|
||||||
TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
|
TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
|
||||||
|
ThreadContext *tc)
|
||||||
{
|
{
|
||||||
if (fault == NoFault) {
|
if (fault == NoFault) {
|
||||||
DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
|
DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
|
||||||
|
@ -608,7 +609,7 @@ TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
|
||||||
|
|
||||||
|
|
||||||
void
|
void
|
||||||
TimingSimpleCPU::advanceInst(Fault fault)
|
TimingSimpleCPU::advanceInst(const Fault &fault)
|
||||||
{
|
{
|
||||||
if (_status == Faulting)
|
if (_status == Faulting)
|
||||||
return;
|
return;
|
||||||
|
|
|
@ -123,7 +123,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
finish(Fault fault, RequestPtr req, ThreadContext *tc,
|
finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
|
||||||
BaseTLB::Mode mode)
|
BaseTLB::Mode mode)
|
||||||
{
|
{
|
||||||
cpu->sendFetch(fault, req, tc);
|
cpu->sendFetch(fault, req, tc);
|
||||||
|
@ -135,7 +135,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
|
||||||
void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
|
void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
|
||||||
uint8_t *data, bool read);
|
uint8_t *data, bool read);
|
||||||
|
|
||||||
void translationFault(Fault fault);
|
void translationFault(const Fault &fault);
|
||||||
|
|
||||||
void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
|
void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
|
||||||
void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
|
void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
|
||||||
|
@ -280,10 +280,10 @@ class TimingSimpleCPU : public BaseSimpleCPU
|
||||||
Addr addr, unsigned flags, uint64_t *res);
|
Addr addr, unsigned flags, uint64_t *res);
|
||||||
|
|
||||||
void fetch();
|
void fetch();
|
||||||
void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
|
void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
|
||||||
void completeIfetch(PacketPtr );
|
void completeIfetch(PacketPtr );
|
||||||
void completeDataAccess(PacketPtr pkt);
|
void completeDataAccess(PacketPtr pkt);
|
||||||
void advanceInst(Fault fault);
|
void advanceInst(const Fault &fault);
|
||||||
|
|
||||||
/** This function is used by the page table walker to determine if it could
|
/** This function is used by the page table walker to determine if it could
|
||||||
* translate the a pending request or if the underlying request has been
|
* translate the a pending request or if the underlying request has been
|
||||||
|
|
|
@ -111,7 +111,7 @@ class WholeTranslationState
|
||||||
* request to make it easier to access them later on.
|
* request to make it easier to access them later on.
|
||||||
*/
|
*/
|
||||||
bool
|
bool
|
||||||
finish(Fault fault, int index)
|
finish(const Fault &fault, int index)
|
||||||
{
|
{
|
||||||
assert(outstanding);
|
assert(outstanding);
|
||||||
faults[index] = fault;
|
faults[index] = fault;
|
||||||
|
@ -249,7 +249,7 @@ class DataTranslation : public BaseTLB::Translation
|
||||||
* translation is complete if the state says so.
|
* translation is complete if the state says so.
|
||||||
*/
|
*/
|
||||||
void
|
void
|
||||||
finish(Fault fault, RequestPtr req, ThreadContext *tc,
|
finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
|
||||||
BaseTLB::Mode mode)
|
BaseTLB::Mode mode)
|
||||||
{
|
{
|
||||||
assert(state);
|
assert(state);
|
||||||
|
|
|
@ -104,8 +104,8 @@ class BaseTLB : public SimObject
|
||||||
* be responsible for cleaning itself up which will happen in this
|
* be responsible for cleaning itself up which will happen in this
|
||||||
* function. Once it's called, the object is no longer valid.
|
* function. Once it's called, the object is no longer valid.
|
||||||
*/
|
*/
|
||||||
virtual void finish(Fault fault, RequestPtr req, ThreadContext *tc,
|
virtual void finish(const Fault &fault, RequestPtr req,
|
||||||
Mode mode) = 0;
|
ThreadContext *tc, Mode mode) = 0;
|
||||||
|
|
||||||
/** This function is used by the page table walker to determine if it
|
/** This function is used by the page table walker to determine if it
|
||||||
* should translate the a pending request or if the underlying request
|
* should translate the a pending request or if the underlying request
|
||||||
|
|
Loading…
Reference in a new issue