diff --git a/src/sim/System.py b/src/sim/System.py index 3caa907d7..d34a043c1 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -37,8 +37,9 @@ from PhysicalMemory import * class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] -class System(SimObject): +class System(MemObject): type = 'System' + system_port = Port("System port") @classmethod def export_method_cxx_predecls(cls, code): diff --git a/src/sim/system.cc b/src/sim/system.cc index 556a919d5..bff98ace7 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 ARM Limited + * Copyright (c) 2011-2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -78,7 +78,9 @@ vector System::systemList; int System::numSystemsRunning = 0; System::System(Params *p) - : SimObject(p), physmem(p->physmem), _numContexts(0), + : MemObject(p), _systemPort("system_port", this), + physmem(p->physmem), + _numContexts(0), #if FULL_SYSTEM init_param(p->init_param), loadAddrMask(p->load_addr_mask), @@ -190,6 +192,13 @@ System::~System() delete workItemStats[j]; } +Port* +System::getPort(const std::string &if_name, int idx) +{ + // no need to distinguish at the moment (besides checking) + return &_systemPort; +} + void System::setMemoryMode(Enums::MemoryMode mode) { diff --git a/src/sim/system.hh b/src/sim/system.hh index 44383c399..9efe37651 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2012 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2002-2005 The Regents of The University of Michigan * Copyright (c) 2011 Regents of the University of California * All rights reserved. @@ -44,9 +56,9 @@ #include "config/full_system.hh" #include "cpu/pc_event.hh" #include "enums/MemoryMode.hh" +#include "mem/mem_object.hh" #include "mem/port.hh" #include "params/System.hh" -#include "sim/sim_object.hh" #if FULL_SYSTEM #include "kern/system_events.hh" @@ -65,10 +77,54 @@ class VirtualPort; class GDBListener; class BaseRemoteGDB; -class System : public SimObject +class System : public MemObject { + private: + + /** + * Private class for the system port which is only used as a + * master for debug access and for non-structural entities that do + * not have a port of their own. + */ + class SystemPort : public Port + { + public: + + /** + * Create a system port with a name and an owner. + */ + SystemPort(const std::string &_name, MemObject *_owner) + : Port(_name, _owner) + { } + bool recvTiming(PacketPtr pkt) + { panic("SystemPort does not receive timing!\n"); return false; } + Tick recvAtomic(PacketPtr pkt) + { panic("SystemPort does not receive atomic!\n"); return 0; } + void recvFunctional(PacketPtr pkt) + { panic("SystemPort does not receive functional!\n"); } + void recvStatusChange(Status status) { } + + }; + + SystemPort _systemPort; + public: + /** + * Get a pointer to the system port that can be used by + * non-structural simulation objects like processes or threads, or + * external entities like loaders and debuggers, etc, to access + * the memory system. + * + * @return a pointer to the system port we own + */ + Port* getSystemPort() { return &_systemPort; } + + /** + * Additional function to return the Port of a memory object. + */ + Port *getPort(const std::string &if_name, int idx = -1); + static const char *MemoryModeStrings[3]; Enums::MemoryMode