ARM: Implement VCVT between double and single width FP.
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2 changed files with 34 additions and 2 deletions
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@ -616,8 +616,15 @@ let {{
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return new WarnUnimplemented("vcmp, vcmpe", machInst);
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return new WarnUnimplemented("vcmp, vcmpe", machInst);
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case 0x7:
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case 0x7:
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if (opc3 == 0x3) {
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if (opc3 == 0x3) {
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// Between double and single precision.
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if (single) {
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return new WarnUnimplemented("vcvt", machInst);
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vm = (IntRegIndex)(bits(machInst, 5) |
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(bits(machInst, 3, 0) << 1));
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return new VcvtFpSFpD(machInst, vd, vm);
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} else {
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vd = (IntRegIndex)(bits(machInst, 22) |
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(bits(machInst, 15, 12) << 1));
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return new VcvtFpDFpS(machInst, vd, vm);
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}
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}
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}
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break;
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break;
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case 0x8:
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case 0x8:
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@ -678,4 +678,29 @@ let {{
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header_output += RegRegOpDeclare.subst(vcvtFpSIntDIop);
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header_output += RegRegOpDeclare.subst(vcvtFpSIntDIop);
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decoder_output += RegRegOpConstructor.subst(vcvtFpSIntDIop);
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decoder_output += RegRegOpConstructor.subst(vcvtFpSIntDIop);
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exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
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exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
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vcvtFpSFpDCode = '''
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IntDoubleUnion cDest;
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cDest.fp = FpOp1;
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "RegRegOp",
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{ "code": vcvtFpSFpDCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(vcvtFpSFpDIop);
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decoder_output += RegRegOpConstructor.subst(vcvtFpSFpDIop);
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exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
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vcvtFpDFpSCode = '''
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IntDoubleUnion cOp1;
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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FpDest = cOp1.fp;
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'''
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vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "RegRegOp",
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{ "code": vcvtFpDFpSCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(vcvtFpDFpSIop);
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decoder_output += RegRegOpConstructor.subst(vcvtFpDFpSIop);
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exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
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}};
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}};
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