mem: Change accessor function names to match the port interface

This patch changes the names of the cache accessor functions to be in
line with those used by the ports. This is done to avoid confusion and
get closer to a one-to-one correspondence between the interface of the
memory object (the cache in this case) and the port itself.

The member function timingAccess has been split into a snoop/non-snoop
part to avoid branching on the isResponse() of the packet.

src/mem/cache/cache.hh

@@ -234,6 +234,54 @@ class Cache : public BaseCache
     BlkType *handleFill(PacketPtr pkt, BlkType *blk,
                         PacketList &writebacks);
 
+
+    /**
+     * Performs the access specified by the request.
+     * @param pkt The request to perform.
+     * @return The result of the access.
+     */
+    bool recvTimingReq(PacketPtr pkt);
+
+    /**
+     * Handles a response (cache line fill/write ack) from the bus.
+     * @param pkt The response packet
+     */
+    void recvTimingResp(PacketPtr pkt);
+
+    /**
+     * Snoops bus transactions to maintain coherence.
+     * @param pkt The current bus transaction.
+     */
+    void recvTimingSnoopReq(PacketPtr pkt);
+
+    /**
+     * Handle a snoop response.
+     * @param pkt Snoop response packet
+     */
+    void recvTimingSnoopResp(PacketPtr pkt);
+
+    /**
+     * Performs the access specified by the request.
+     * @param pkt The request to perform.
+     * @return The number of cycles required for the access.
+     */
+    Cycles recvAtomic(PacketPtr pkt);
+
+    /**
+     * Snoop for the provided request in the cache and return the estimated
+     * time of completion.
+     * @param pkt The memory request to snoop
+     * @return The number of cycles required for the snoop.
+     */
+    Cycles recvAtomicSnoop(PacketPtr pkt);
+
+    /**
+     * Performs the access specified by the request.
+     * @param pkt The request to perform.
+     * @param fromCpuSide from the CPU side port or the memory side port
+     */
+    void functionalAccess(PacketPtr pkt, bool fromCpuSide);
+
     void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
                                bool deferred_response = false,
                                bool pending_downgrade = false);
@@ -290,47 +338,6 @@ class Cache : public BaseCache
      */
     void uncacheableFlush(PacketPtr pkt);
 
-    /**
-     * Performs the access specified by the request.
-     * @param pkt The request to perform.
-     * @return The result of the access.
-     */
-    bool timingAccess(PacketPtr pkt);
-
-    /**
-     * Performs the access specified by the request.
-     * @param pkt The request to perform.
-     * @return The number of ticks required for the access.
-     */
-    Tick atomicAccess(PacketPtr pkt);
-
-    /**
-     * Performs the access specified by the request.
-     * @param pkt The request to perform.
-     * @param fromCpuSide from the CPU side port or the memory side port
-     */
-    void functionalAccess(PacketPtr pkt, bool fromCpuSide);
-
-    /**
-     * Handles a response (cache line fill/write ack) from the bus.
-     * @param pkt The request being responded to.
-     */
-    void handleResponse(PacketPtr pkt);
-
-    /**
-     * Snoops bus transactions to maintain coherence.
-     * @param pkt The current bus transaction.
-     */
-    void snoopTiming(PacketPtr pkt);
-
-    /**
-     * Snoop for the provided request in the cache and return the estimated
-     * time of completion.
-     * @param pkt The memory request to snoop
-     * @return The number of cycles required for the snoop.
-     */
-    Cycles snoopAtomic(PacketPtr pkt);
-
     /**
      * Squash all requests associated with specified thread.
      * intended for use by I-cache.

src/mem/cache/cache_impl.hh

@@ -356,10 +356,37 @@ class ForwardResponseRecord : public Packet::SenderState
     {}
 };
 
+template<class TagStore>
+void
+Cache<TagStore>::recvTimingSnoopResp(PacketPtr pkt)
+{
+    Tick time = clockEdge(hitLatency);
+
+    assert(pkt->isResponse());
+
+    // must be cache-to-cache response from upper to lower level
+    ForwardResponseRecord *rec =
+        dynamic_cast<ForwardResponseRecord *>(pkt->popSenderState());
+    assert(!system->bypassCaches());
+
+    if (rec == NULL) {
+        assert(pkt->cmd == MemCmd::HardPFResp);
+        // Check if it's a prefetch response and handle it. We shouldn't
+        // get any other kinds of responses without FRRs.
+        DPRINTF(Cache, "Got prefetch response from above for addr %#x\n",
+                pkt->getAddr());
+        recvTimingResp(pkt);
+        return;
+    }
+
+    pkt->setDest(rec->prevSrc);
+    delete rec;
+    memSidePort->schedTimingSnoopResp(pkt, time);
+}
 
 template<class TagStore>
 bool
-Cache<TagStore>::timingAccess(PacketPtr pkt)
+Cache<TagStore>::recvTimingReq(PacketPtr pkt)
 {
 //@todo Add back in MemDebug Calls
 //    MemDebug::cacheAccess(pkt);
@@ -374,28 +401,6 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
     // we charge hitLatency for doing just about anything here
     Tick time = clockEdge(hitLatency);
 
-    if (pkt->isResponse()) {
-        // must be cache-to-cache response from upper to lower level
-        ForwardResponseRecord *rec =
-            dynamic_cast<ForwardResponseRecord *>(pkt->popSenderState());
-        assert(!system->bypassCaches());
-
-        if (rec == NULL) {
-            assert(pkt->cmd == MemCmd::HardPFResp);
-            // Check if it's a prefetch response and handle it. We shouldn't
-            // get any other kinds of responses without FRRs.
-            DPRINTF(Cache, "Got prefetch response from above for addr %#x\n",
-                    pkt->getAddr());
-            handleResponse(pkt);
-            return true;
-        }
-
-        pkt->setDest(rec->prevSrc);
-        delete rec;
-        memSidePort->schedTimingSnoopResp(pkt, time);
-        return true;
-    }
-
     assert(pkt->isRequest());
 
     // Just forward the packet if caches are disabled.
@@ -616,8 +621,8 @@ Cache<TagStore>::getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
 
 
 template<class TagStore>
-Tick
+Cycles
-Cache<TagStore>::atomicAccess(PacketPtr pkt)
+Cache<TagStore>::recvAtomic(PacketPtr pkt)
 {
     Cycles lat = hitLatency;
 
@@ -626,7 +631,7 @@ Cache<TagStore>::atomicAccess(PacketPtr pkt)
 
     // Forward the request if the system is in cache bypass mode.
     if (system->bypassCaches())
-        return memSidePort->sendAtomic(pkt);
+        return ticksToCycles(memSidePort->sendAtomic(pkt));
 
     if (pkt->memInhibitAsserted()) {
         assert(!pkt->req->isUncacheable());
@@ -816,8 +821,10 @@ Cache<TagStore>::functionalAccess(PacketPtr pkt, bool fromCpuSide)
 
 template<class TagStore>
 void
-Cache<TagStore>::handleResponse(PacketPtr pkt)
+Cache<TagStore>::recvTimingResp(PacketPtr pkt)
 {
+    assert(pkt->isResponse());
+
     Tick time = clockEdge(hitLatency);
     MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
     bool is_error = pkt->isError();
@@ -1366,7 +1373,7 @@ Cache<TagStore>::handleSnoop(PacketPtr pkt, BlkType *blk,
 
 template<class TagStore>
 void
-Cache<TagStore>::snoopTiming(PacketPtr pkt)
+Cache<TagStore>::recvTimingSnoopReq(PacketPtr pkt)
 {
     // Snoops shouldn't happen when bypassing caches
     assert(!system->bypassCaches());
@@ -1447,13 +1454,13 @@ bool
 Cache<TagStore>::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
 {
     // Express snoop responses from master to slave, e.g., from L1 to L2
-    cache->timingAccess(pkt);
+    cache->recvTimingSnoopResp(pkt);
     return true;
 }
 
 template<class TagStore>
 Cycles
-Cache<TagStore>::snoopAtomic(PacketPtr pkt)
+Cache<TagStore>::recvAtomicSnoop(PacketPtr pkt)
 {
     // Snoops shouldn't happen when bypassing caches
     assert(!system->bypassCaches());
@@ -1578,7 +1585,7 @@ Cache<TagStore>::getTimingPacket()
         pkt->cmd = MemCmd::UpgradeFailResp;
         pkt->senderState = mshr;
         pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
-        handleResponse(pkt);
+        recvTimingResp(pkt);
         return NULL;
     } else if (mshr->isForwardNoResponse()) {
         // no response expected, just forward packet as it is
@@ -1709,7 +1716,7 @@ Cache<TagStore>::CpuSidePort::recvTimingReq(PacketPtr pkt)
         return false;
     }
 
-    cache->timingAccess(pkt);
+    cache->recvTimingReq(pkt);
     return true;
 }
 
@@ -1717,8 +1724,9 @@ template<class TagStore>
 Tick
 Cache<TagStore>::CpuSidePort::recvAtomic(PacketPtr pkt)
 {
-    // atomic request
+    // @todo: Note that this is currently using cycles instead of
-    return cache->atomicAccess(pkt);
+    // ticks and will be fixed in a future patch
+    return cache->recvAtomic(pkt);
 }
 
 template<class TagStore>
@@ -1747,7 +1755,7 @@ template<class TagStore>
 bool
 Cache<TagStore>::MemSidePort::recvTimingResp(PacketPtr pkt)
 {
-    cache->handleResponse(pkt);
+    cache->recvTimingResp(pkt);
     return true;
 }
 
@@ -1757,15 +1765,16 @@ void
 Cache<TagStore>::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
 {
     // handle snooping requests
-    cache->snoopTiming(pkt);
+    cache->recvTimingSnoopReq(pkt);
 }
 
 template<class TagStore>
 Tick
 Cache<TagStore>::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
 {
-    // atomic snoop
+    // @todo: Note that this is using cycles and not ticks and will be
-    return cache->snoopAtomic(pkt);
+    // fixed in a future patch
+    return cache->recvAtomicSnoop(pkt);
 }
 
 template<class TagStore>